60106 lines
3.9 MiB
60106 lines
3.9 MiB
; --------------------------------------------------------------------------------
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; @Title: AT91SAM9G10/20/45/15/25/35/46 On-Chip Peripherals
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; @Props: Released
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; @Author: BOB, ZAK, ZUB
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; @Changelog:
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; 2008-04-24
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; 2009-10-12
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; 2012-09-26
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: 6062.pdf (2006-02-03); 6062s.pdf (2006-02-03); doc6221.pdf (2006-09-22)
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; doc6249.pdf (2006-12-14); Migrate_from_AT91SAM9260_to_AT91SAM9G20.pdf
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; doc6462.pdf (2009-06-03); doc6438.pdf (2009-10-13); 6438.pdf 19-Apr-11
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; doc6462.pdf 6-Sep-11; doc11028.pdf (2012-07-13); doc11032.pdf (2011-07-27)
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; ...............; doc11052.pdf (2011-11-21); doc11053.pdf (2011-09-22)
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; @Core: ARM926EJ-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perat91sam9g.per 17347 2024-01-19 09:09:16Z kwisniewski $
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;Known problems:
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; LCD_WPMR no adrres LCD Controller AT91SAM9G10. Register not implemented
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config 16. 8.
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width 0x0b
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base ad:0x00000000
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
|
|
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
|
|
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
|
|
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
|
|
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
|
|
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "BSC (Boot Sequence Controller)"
|
|
base ad:0xfffffe54
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BSC_CR,Boot Sequence Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BOOTKEY ,Valid boot key"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BOOT ,Boot media sequence"
|
|
width 0xB
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0xfffff000
|
|
width 11.
|
|
tree "Source Mode Registers"
|
|
group.long 0x00++0x7f
|
|
line.long 0x0 "AIC_SMR0,AIC Source Mode Register 0"
|
|
bitfld.long 0x0 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x0 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
endif
|
|
line.long 0x4 "AIC_SMR1,AIC Source Mode Register 1"
|
|
bitfld.long 0x4 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x8 "AIC_SMR2,AIC Source Mode Register 2"
|
|
bitfld.long 0x8 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x8 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0xC "AIC_SMR3,AIC Source Mode Register 3"
|
|
bitfld.long 0xC 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0xC 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x10 "AIC_SMR4,AIC Source Mode Register 4"
|
|
bitfld.long 0x10 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x10 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x14 "AIC_SMR5,AIC Source Mode Register 5"
|
|
bitfld.long 0x14 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x14 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x18 "AIC_SMR6,AIC Source Mode Register 6"
|
|
bitfld.long 0x18 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x18 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x1C "AIC_SMR7,AIC Source Mode Register 7"
|
|
bitfld.long 0x1C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x1C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x20 "AIC_SMR8,AIC Source Mode Register 8"
|
|
bitfld.long 0x20 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x20 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x24 "AIC_SMR9,AIC Source Mode Register 9"
|
|
bitfld.long 0x24 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x24 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x28 "AIC_SMR10,AIC Source Mode Register 10"
|
|
bitfld.long 0x28 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x28 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x2C "AIC_SMR11,AIC Source Mode Register 11"
|
|
bitfld.long 0x2C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x2C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x30 "AIC_SMR12,AIC Source Mode Register 12"
|
|
bitfld.long 0x30 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x30 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x34 "AIC_SMR13,AIC Source Mode Register 13"
|
|
bitfld.long 0x34 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x34 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x38 "AIC_SMR14,AIC Source Mode Register 14"
|
|
bitfld.long 0x38 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x38 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x3C "AIC_SMR15,AIC Source Mode Register 15"
|
|
bitfld.long 0x3C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x3C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x40 "AIC_SMR16,AIC Source Mode Register 16"
|
|
bitfld.long 0x40 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x40 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x44 "AIC_SMR17,AIC Source Mode Register 17"
|
|
bitfld.long 0x44 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x44 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x48 "AIC_SMR18,AIC Source Mode Register 18"
|
|
bitfld.long 0x48 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x48 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x4C "AIC_SMR19,AIC Source Mode Register 19"
|
|
bitfld.long 0x4C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x50 "AIC_SMR20,AIC Source Mode Register 20"
|
|
bitfld.long 0x50 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x50 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x54 "AIC_SMR21,AIC Source Mode Register 21"
|
|
bitfld.long 0x54 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x54 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x58 "AIC_SMR22,AIC Source Mode Register 22"
|
|
bitfld.long 0x58 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x58 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x5C "AIC_SMR23,AIC Source Mode Register 23"
|
|
bitfld.long 0x5C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x5C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x60 "AIC_SMR24,AIC Source Mode Register 24"
|
|
bitfld.long 0x60 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x60 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x64 "AIC_SMR25,AIC Source Mode Register 25"
|
|
bitfld.long 0x64 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x64 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x68 "AIC_SMR26,AIC Source Mode Register 26"
|
|
bitfld.long 0x68 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x68 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x6C "AIC_SMR27,AIC Source Mode Register 27"
|
|
bitfld.long 0x6C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x6C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x70 "AIC_SMR28,AIC Source Mode Register 28"
|
|
bitfld.long 0x70 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x70 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x74 "AIC_SMR29,AIC Source Mode Register 29"
|
|
bitfld.long 0x74 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x74 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x78 "AIC_SMR30,AIC Source Mode Register 30"
|
|
bitfld.long 0x78 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x78 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x7C "AIC_SMR31,AIC Source Mode Register 31"
|
|
bitfld.long 0x7C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x7C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
tree.end
|
|
tree "Source Vector Registers"
|
|
group.long 0x80++0x7f
|
|
textline ""
|
|
line.long 0x0 "AIC_SVR0 ,AIC Source Vector Register 0 "
|
|
textline ""
|
|
line.long 0x4 "AIC_SVR1 ,AIC Source Vector Register 1 "
|
|
textline ""
|
|
line.long 0x8 "AIC_SVR2 ,AIC Source Vector Register 2 "
|
|
textline ""
|
|
line.long 0xC "AIC_SVR3 ,AIC Source Vector Register 3 "
|
|
textline ""
|
|
line.long 0x10 "AIC_SVR4 ,AIC Source Vector Register 4 "
|
|
textline ""
|
|
line.long 0x14 "AIC_SVR5 ,AIC Source Vector Register 5 "
|
|
textline ""
|
|
line.long 0x18 "AIC_SVR6 ,AIC Source Vector Register 6 "
|
|
textline ""
|
|
line.long 0x1C "AIC_SVR7 ,AIC Source Vector Register 7 "
|
|
textline ""
|
|
line.long 0x20 "AIC_SVR8 ,AIC Source Vector Register 8 "
|
|
textline ""
|
|
line.long 0x24 "AIC_SVR9 ,AIC Source Vector Register 9 "
|
|
textline ""
|
|
line.long 0x28 "AIC_SVR10,AIC Source Vector Register 10"
|
|
textline ""
|
|
line.long 0x2C "AIC_SVR11,AIC Source Vector Register 11"
|
|
textline ""
|
|
line.long 0x30 "AIC_SVR12,AIC Source Vector Register 12"
|
|
textline ""
|
|
line.long 0x34 "AIC_SVR13,AIC Source Vector Register 13"
|
|
textline ""
|
|
line.long 0x38 "AIC_SVR14,AIC Source Vector Register 14"
|
|
textline ""
|
|
line.long 0x3C "AIC_SVR15,AIC Source Vector Register 15"
|
|
textline ""
|
|
line.long 0x40 "AIC_SVR16,AIC Source Vector Register 16"
|
|
textline ""
|
|
line.long 0x44 "AIC_SVR17,AIC Source Vector Register 17"
|
|
textline ""
|
|
line.long 0x48 "AIC_SVR18,AIC Source Vector Register 18"
|
|
textline ""
|
|
line.long 0x4C "AIC_SVR19,AIC Source Vector Register 19"
|
|
textline ""
|
|
line.long 0x50 "AIC_SVR20,AIC Source Vector Register 20"
|
|
textline ""
|
|
line.long 0x54 "AIC_SVR21,AIC Source Vector Register 21"
|
|
textline ""
|
|
line.long 0x58 "AIC_SVR22,AIC Source Vector Register 22"
|
|
textline ""
|
|
line.long 0x5C "AIC_SVR23,AIC Source Vector Register 23"
|
|
textline ""
|
|
line.long 0x60 "AIC_SVR24,AIC Source Vector Register 24"
|
|
textline ""
|
|
line.long 0x64 "AIC_SVR25,AIC Source Vector Register 25"
|
|
textline ""
|
|
line.long 0x68 "AIC_SVR26,AIC Source Vector Register 26"
|
|
textline ""
|
|
line.long 0x6C "AIC_SVR27,AIC Source Vector Register 27"
|
|
textline ""
|
|
line.long 0x70 "AIC_SVR28,AIC Source Vector Register 28"
|
|
textline ""
|
|
line.long 0x74 "AIC_SVR29,AIC Source Vector Register 29"
|
|
textline ""
|
|
line.long 0x78 "AIC_SVR30,AIC Source Vector Register 30"
|
|
textline ""
|
|
line.long 0x7C "AIC_SVR31,AIC Source Vector Register 31"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "AIC_IVR,AIC Interrupt Vector Register"
|
|
line.long 0x04 "AIC_FVR,AIC FIQ Vector Register"
|
|
line.long 0x08 "AIC_ISR,AIC Interrupt Status Register"
|
|
bitfld.long 0x08 0.--4. " IRQID ,Current Interrupt Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x07
|
|
line.long 0x0 "AIC_IPR,AIC Interrupt Pending Register"
|
|
setclrfld.long 0x0 31. 0x20 31. 0x1C 31. " PID31_set/clr ,Interrupt 31 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 30. 0x20 30. 0x1C 30. " PID30_set/clr ,Interrupt 30 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x20 29. 0x1C 29. " PID29_set/clr ,Interrupt 29 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 28. 0x20 28. 0x1C 28. " PID28_set/clr ,Interrupt 28 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x20 27. 0x1C 27. " PID27_set/clr ,Interrupt 27 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 26. 0x20 26. 0x1C 26. " PID26_set/clr ,Interrupt 26 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x20 25. 0x1C 25. " PID25_set/clr ,Interrupt 25 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 24. 0x20 24. 0x1C 24. " PID24_set/clr ,Interrupt 24 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x20 23. 0x1C 23. " PID23_set/clr ,Interrupt 23 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 22. 0x20 22. 0x1C 22. " PID22_set/clr ,Interrupt 22 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x20 21. 0x1C 21. " PID21_set/clr ,Interrupt 21 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 20. 0x20 20. 0x1C 20. " PID20_set/clr ,Interrupt 20 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x20 19. 0x1C 19. " PID19_set/clr ,Interrupt 19 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 18. 0x20 18. 0x1C 18. " PID18_set/clr ,Interrupt 18 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x20 17. 0x1C 17. " PID17_set/clr ,Interrupt 17 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 16. 0x20 16. 0x1C 16. " PID16_set/clr ,Interrupt 16 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x20 15. 0x1C 15. " PID15_set/clr ,Interrupt 15 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 14. 0x20 14. 0x1C 14. " PID14_set/clr ,Interrupt 14 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x20 13. 0x1C 13. " PID13_set/clr ,Interrupt 13 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 12. 0x20 12. 0x1C 12. " PID12_set/clr ,Interrupt 12 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x20 11. 0x1C 11. " PID11_set/clr ,Interrupt 11 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 10. 0x20 10. 0x1C 10. " PID10_set/clr ,Interrupt 10 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x20 9. 0x1C 9. " PID9_set/clr ,Interrupt 9 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 8. 0x20 8. 0x1C 8. " PID8_set/clr ,Interrupt 8 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x20 7. 0x1C 7. " PID7_set/clr ,Interrupt 7 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 6. 0x20 6. 0x1C 6. " PID6_set/clr ,Interrupt 6 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x20 5. 0x1C 5. " PID5_set/clr ,Interrupt 5 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 4. 0x20 4. 0x1C 4. " PID4_set/clr ,Interrupt 4 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x20 3. 0x1C 3. " PID3_set/clr ,Interrupt 3 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 2. 0x20 2. 0x1C 2. " PID2_set/clr ,Interrupt 2 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x20 1. 0x1C 1. " SYS_set/clr ,SYS Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 0. 0x20 0. 0x1C 0. " FIQ_set/clr ,FIQ Interrupt Pending" "Not pending,Pending"
|
|
line.long 0x4 "AIC_IMR,AIC Interrupt Mask Register"
|
|
setclrfld.long 0x4 31. 0x14 31. 0x18 31. " PID31_set/clr ,Interrupt 31 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x14 30. 0x18 30. " PID30_set/clr ,Interrupt 30 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x14 29. 0x18 29. " PID29_set/clr ,Interrupt 29 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x14 28. 0x18 28. " PID28_set/clr ,Interrupt 28 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x14 27. 0x18 27. " PID27_set/clr ,Interrupt 27 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x14 26. 0x18 26. " PID26_set/clr ,Interrupt 26 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x14 25. 0x18 25. " PID25_set/clr ,Interrupt 25 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x14 24. 0x18 24. " PID24_set/clr ,Interrupt 24 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x14 23. 0x18 23. " PID23_set/clr ,Interrupt 23 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x14 22. 0x18 22. " PID22_set/clr ,Interrupt 22 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x14 21. 0x18 21. " PID21_set/clr ,Interrupt 21 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x14 20. 0x18 20. " PID20_set/clr ,Interrupt 20 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x14 19. 0x18 19. " PID19_set/clr ,Interrupt 19 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x14 18. 0x18 18. " PID18_set/clr ,Interrupt 18 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x14 17. 0x18 17. " PID17_set/clr ,Interrupt 17 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x14 16. 0x18 16. " PID16_set/clr ,Interrupt 16 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x14 15. 0x18 15. " PID15_set/clr ,Interrupt 15 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x14 14. 0x18 14. " PID14_set/clr ,Interrupt 14 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x14 13. 0x18 13. " PID13_set/clr ,Interrupt 13 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x14 12. 0x18 12. " PID12_set/clr ,Interrupt 12 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x14 11. 0x18 11. " PID11_set/clr ,Interrupt 11 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x14 10. 0x18 10. " PID10_set/clr ,Interrupt 10 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x14 9. 0x18 9. " PID9_set/clr ,Interrupt 9 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x14 8. 0x18 8. " PID8_set/clr ,Interrupt 8 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x14 7. 0x18 7. " PID7_set/clr ,Interrupt 7 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x14 6. 0x18 6. " PID6_set/clr ,Interrupt 6 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x14 5. 0x18 5. " PID5_set/clr ,Interrupt 5 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x14 4. 0x18 4. " PID4_set/clr ,Interrupt 4 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x14 3. 0x18 3. " PID3_set/clr ,Interrupt 3 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x14 2. 0x18 2. " PID2_set/clr ,Interrupt 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x14 1. 0x18 1. " SYS_set/clr ,SYS Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 0. 0x14 0. 0x18 0. " FIQ_set/clr ,FIQ Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "AIC_CISR,AIC Core Interrupt Status Register"
|
|
bitfld.long 0x0 1. " NIRQ ,NIRQ Status" "Deactivated,Activated"
|
|
bitfld.long 0x0 0. " NFIQ ,NFIQ Status" "Deactivated,Activated"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x0 "AIC_EOICR,AIC End of Interrupt Command Register"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "AIC_SPU,AIC Spurious Interrupt Vector Register"
|
|
line.long 0x04 "AIC_DEBUG,AIC Debug Control Register"
|
|
bitfld.long 0x04 1. " GMSK ,General Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " PROT ,Protection Mode" "Disabled,Enabled"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "AIC_FFSR,Fast Forcing Status Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " PID31_set/clr ,Interrupt 31 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " PID30_set/clr ,Interrupt 30 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " PID29_set/clr ,Interrupt 29 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " PID28_set/clr ,Interrupt 28 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " PID27_set/clr ,Interrupt 27 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " PID26_set/clr ,Interrupt 26 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " PID25_set/clr ,Interrupt 25 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " PID24_set/clr ,Interrupt 24 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " PID23_set/clr ,Interrupt 23 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " PID22_set/clr ,Interrupt 22 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " PID21_set/clr ,Interrupt 21 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " PID20_set/clr ,Interrupt 20 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " PID19_set/clr ,Interrupt 19 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " PID18_set/clr ,Interrupt 18 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " PID17_set/clr ,Interrupt 17 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " PID16_set/clr ,Interrupt 16 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " PID15_set/clr ,Interrupt 15 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " PID14_set/clr ,Interrupt 14 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " PID13_set/clr ,Interrupt 13 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " PID12_set/clr ,Interrupt 12 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " PID11_set/clr ,Interrupt 11 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " PID10_set/clr ,Interrupt 10 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " PID9_set/clr ,Interrupt 9 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " PID8_set/clr ,Interrupt 8 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PID7_set/clr ,Interrupt 7 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " PID6_set/clr ,Interrupt 6 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " PID5_set/clr ,Interrupt 5 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " PID4_set/clr ,Interrupt 4 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " PID3_set/clr ,Interrupt 3 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " PID2_set/clr ,Interrupt 2 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " SYS_set/clr ,SYS Interrupt Fast Forcing Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "AIC_WPMR,AIC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "AIC_WPSR,AIC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "RSTC (Reset Controller)"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xfffffe00
|
|
else
|
|
base ad:0xfffffd00
|
|
endif
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "RSTC_CR,Reset Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
bitfld.long 0x00 17. " SRCMP ,Software Reset Command in Progress" "Not performed/ready,Performed/busy"
|
|
bitfld.long 0x00 16. " NRSTL ,NRST Pin Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RSTTYP ,Reset Type" "General Reset,Wake Up Reset,Watchdog Reset,Software Reset,User Reset,?..."
|
|
bitfld.long 0x00 0. " URSTS ,User Reset Status" "No high-to-low edge,High-to-low transition"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
in
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RSTC_MR,Reset Controller Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 16. " BODIEN , Brownout Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2-cycles,4-cycles,8-cycles,16-cycles,32-cycles,64-cycles,128-cycles,256-cycles,512-cycles,1024-cycles,2048-cycles,4096-cycles,8192-cycles,16384-cycles,32768-cycles,65536-cycles"
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "RTT (Real-Time Timer)"
|
|
base ad:0xfffffd20
|
|
width 11.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTT_MR,Real-Time Timer Mode Register"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "No effect,Restarted"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value"
|
|
line.long 0x4 "RTT_AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "RTT_VR,Real-Time Timer Value Register"
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "RTT_SR,Real-time Timer Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0xfffffdb0
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--17. " CEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,Hour Mode Register"
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)&&((data.long(ad:0xfffffdb0+0x08)&0x300000)==0x100000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x04)&0x00000001)==0x00000000)&&((data.long(ad:0xfffffdb0+0x08)&0x300000)==0x200000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
if ((data.long(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 16.--21. " HOUR ,Current Hour" "-,1,2,3,4,5,6,7,8,9,10,11,12,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 16.--21. " HOUR ,Current Hour" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffdb0+0x0c)&0x100000)==0x100000)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (cpu()=="AT91SAM9M11")
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CENT ,Current Century" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((d.l(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)&&((d.l(ad:0xfffffdb0+0x10)&0x300000)==0x100000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.l(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0xfffffdb0+0x04)&0x00000001)==0x00000000)&&((d.l(ad:0xfffffdb0+0x10)&0x300000)==0x200000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
if ((d.l(ad:0xfffffdb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffdb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffdb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffdb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffdb0+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
endif
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
sif (cpu()=="AT91SAM9261")
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Cleared"
|
|
else
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL_Set/Clr ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM_Set/Clr ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC_Set/Clr ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR_Set/Clr ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK_Set/Clr ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RTC_VER,Valid Entry Register"
|
|
in
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RTC_VER,Valid Entry Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 3. " NVCALALR ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTIMALR ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVCAL ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVTIM ,Non-Valid Time" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0xfffffeb0
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--17. " CEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,Hour Mode Register"
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)&&((data.long(ad:0xfffffeb0+0x08)&0x300000)==0x100000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x04)&0x00000001)==0x00000000)&&((data.long(ad:0xfffffeb0+0x08)&0x300000)==0x200000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
if ((data.long(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 16.--21. " HOUR ,Current Hour" "-,1,2,3,4,5,6,7,8,9,10,11,12,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 16.--21. " HOUR ,Current Hour" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x0c)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x0c)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffeb0+0x0c)&0x100000)==0x100000)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (cpu()=="AT91SAM9M11")
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CENT ,Current Century" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((d.l(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)&&((d.l(ad:0xfffffeb0+0x10)&0x300000)==0x100000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.l(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0xfffffeb0+0x04)&0x00000001)==0x00000000)&&((d.l(ad:0xfffffeb0+0x10)&0x300000)==0x200000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
if ((d.l(ad:0xfffffeb0+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
if (((data.long(ad:0xfffffeb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)==0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x100000)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x10000||0x30000||0x50000||0x70000||0x80000||0x100000||0x120000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(ad:0xfffffeb0+0x14)&0x30000000)!=0x30000000)&&((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x0)&&((data.long(ad:0xfffffeb0+0x14)&0x1f0000)==(0x40000||0x60000||0x90000||0x110000)))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((data.long(ad:0xfffffeb0+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "-,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
endif
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
sif (cpu()=="AT91SAM9261")
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Cleared"
|
|
else
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL_Set/Clr ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM_Set/Clr ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC_Set/Clr ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR_Set/Clr ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK_Set/Clr ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RTC_VER,Valid Entry Register"
|
|
in
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RTC_VER,Valid Entry Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x00 3. " NVCALALR ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTIMALR ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVCAL ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVTIM ,Non-Valid Time" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "PIT (Periodic Interval Timer)"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xfffffe30
|
|
else
|
|
base ad:0xfffffd30
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PIT_MR,Periodic Interval Timer Mode Register"
|
|
bitfld.long 0x00 25. " PITIEN ,Periodic Interval Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PITEN ,Period Interval Timer Enabled" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. 1. " PIV ,Periodic Interval Value"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "PIT_SR,Periodic Interval Timer Status Register"
|
|
in
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register"
|
|
in
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register"
|
|
in
|
|
else
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIT_SR,Periodic Interval Timer Status Register"
|
|
bitfld.long 0x00 0. " PITS ,Periodic Interval Timer Status" "Not reached,Reached"
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register"
|
|
in
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register"
|
|
hexmask.long.word 0x0 20.--31. 1. " PICNT ,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. " CPIV ,Current Periodic Interval Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xfffffe40
|
|
else
|
|
base ad:0xfffffd40
|
|
endif
|
|
width 8.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "WDT_CR,Watchdog Timer Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "WDT_MR,Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Running,Stopped"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Processor Reset" "All,Processor"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "WDT_SR,Watchdog Timer Status Register"
|
|
bitfld.long 0x00 1. " WDERR ,Watchdog Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " WDUNF ,Watchdog Underflow" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "WDT_SR,Status Register"
|
|
in
|
|
endif
|
|
;wgroup 0x0++0x0
|
|
width 0xb
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xfffffe10
|
|
else
|
|
base ad:0xfffffd10
|
|
endif
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "SHDW_CR,Shutdown Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " SHDW ,Shut Down Command" "No effect,Shut down"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SHDW_MR,Shutdown Mode Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
bitfld.long 0x00 17. " RTCWKEN ,Real-time Clock Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 16. " RTTWKEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CPTWK0 ,Counter on Wake-Up 0" "1 cycle,17 cycles,33 cycles,49 cycles,65 cycles,81 cycles,97 cycles,113 cycles,129 cycles,145 cycles,161 cycles,177 cycles,193 cycles,209 cycles,225 cycles,241 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WKMODE0 ,Wake-Up Mode 0" "No wake-up,Low/high,High/low,Both"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SHDW_SR,Shutdown Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
sif (cpu()=="AT91SAM9G10")
|
|
base ad:0xfffffd50
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffffd60
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xfffffe60
|
|
endif
|
|
width 11.
|
|
group.long 0x00++0xf
|
|
line.long 0x0 "SYS_GPBR0,General Purpose Backup Register 0"
|
|
line.long 0x4 "SYS_GPBR1,General Purpose Backup Register 1"
|
|
line.long 0x8 "SYS_GPBR2,General Purpose Backup Register 2"
|
|
line.long 0xC "SYS_GPBR3,General Purpose Backup Register 3"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "SCKC (Slow Clock Controller)"
|
|
base ad:0xFFFFFE50
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCKCR,Slow Clock Configuration Register"
|
|
bitfld.long 0x00 3. " OSCSEL ,Slow Clock Selector" "Internal RC,32768Hz oscillator"
|
|
bitfld.long 0x00 2. " OSC32BYP ,32768Hz Oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OSC32EN ,32768Hz Oscillator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCEN ,Internal RC" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xFFFFFC00
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Host OHCI Clocks Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMDCK_set/clr ,SMD Clock Status" "Disabled,Enabled"
|
|
sif (cpu()!="AT91SAM9G25")
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDCK_set/clr ,LCD Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " DDRCK_set/clr ,DDR Clock Status" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Disable" "No effect,Disable"
|
|
sif (cpu()=="AT91SAM9G25")
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " SSC_set/clr ,Synchronous Serial Controller" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " HSMCI1_set/clr ,High Speed Multimedia Card (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDC_set/clr ,LCD Controller (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMAC1_set/clr ,DMA Controller 1 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC0_set/clr ,DMA Controller 0 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " ADC_set/clr ,ADC Controller(Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TC_set/clr ,Timer Counter (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " UART1_set/clr ,UART1 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " UART0_set/clr ,UART0 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_set/clr ,Serial Peripheral Interface 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " SPI0_set/clr ,Serial Peripheral Interface 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " HSMCI0_set/clr ,High Speed Multimedia Card (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWI2_set/clr ,Two-Wire Interface 2 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " USART2_set/clr ,USART 2 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " USART1_set/clr ,USART 1 (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " USART0_set/clr ,USART 0 (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMD_set/clr ,SMD Soft Modem (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOC/PIOD_set/clr ,Parallel I/O Controller C and D (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA/PIOB_set/clr ,Parallel I/O Controller A and B (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9G15")
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " SSC_set/clr ,Synchronous Serial Controller" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " HSMCI1_set/clr ,High Speed Multimedia Card (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDC_set/clr ,LCD Controller (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMAC1_set/clr ,DMA Controller 1 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC0_set/clr ,DMA Controller 0 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " ADC_set/clr ,ADC Controller(Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TC_set/clr ,Timer Counter (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " UART1_set/clr ,UART1 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " UART0_set/clr ,UART0 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_set/clr ,Serial Peripheral Interface 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " SPI0_set/clr ,Serial Peripheral Interface 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " HSMCI0_set/clr ,High Speed Multimedia Card (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWI2_set/clr ,Two-Wire Interface 2 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " USART2_set/clr ,USART 2 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " USART1_set/clr ,USART 1 (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " USART0_set/clr ,USART 0 (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMD_set/clr ,SMD Soft Modem (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOC/PIOD_set/clr ,Parallel I/O Controller C and D (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA/PIOB_set/clr ,Parallel I/O Controller A and B (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " SSC_set/clr ,Synchronous Serial Controller" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " HSMCI1_set/clr ,High Speed Multimedia Card (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " ISI_set/clr ,Image Sensor Interface (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " EMAC_set/clr ,Ethernet MAC (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMAC1_set/clr ,DMA Controller 1 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC0_set/clr ,DMA Controller 0 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " ADC_set/clr ,ADC Controller(Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TC_set/clr ,Timer Counter (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " UART1_set/clr ,UART1 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " UART0_set/clr ,UART0 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_set/clr ,Serial Peripheral Interface 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " SPI0_set/clr ,Serial Peripheral Interface 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " HSMCI0_set/clr ,High Speed Multimedia Card (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWI2_set/clr ,Two-Wire Interface 2 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " USART3_set/clr ,USART 3 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " USART2_set/clr ,USART 2 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " USART1_set/clr ,USART 1 (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " USART0_set/clr ,USART 0 (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMD_set/clr ,SMD Soft Modem (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOC/PIOD_set/clr ,Parallel I/O Controller C and D (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA/PIOB_set/clr ,Parallel I/O Controller A and B (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 28.--31. " BIASCOUNT ,UTMI BIAS Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24. " BIASEN ,UTMI BIAS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT ,UTMI PLL Start-up Time" "0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120"
|
|
bitfld.long 0x00 16. " UPLLEN ,UTMI PLL Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,Main Oscillator Register"
|
|
bitfld.long 0x04 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MOSCSEL ,Main Oscillator Selection" "On-Chip RC,Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MOSCRCEN ,On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MOSCXTBY ,Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MOSCXTEN ,Crystal Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,Processor Clock Division" "Clock,Clock/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,Clock/3"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
bitfld.long 0x00 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
else
|
|
bitfld.long 0x00 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
endif
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB OHCI Clock" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0. " USBS ,USB OHCI Input clock selection" "PLLA,UPLL"
|
|
line.long 0x04 "PMC_SMD,SMD Clock Register"
|
|
bitfld.long 0x04 8.--12. " SMDDIV ,Divider for SMD Clock" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x04 0. " SMDS ,SMD input clock selection" "PLLA,UPLL"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLL,Master,?..."
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLL,Master,?..."
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 18. -0xc 18. -0x8 18. " CFDEV_set/clr ,Clock Failure Detector Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0xc 17. -0x8 17. " MOSCRCS_set/clr ,Main On-Chip RC Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0xc 16. -0x8 16. " MOSCSELS_set/clr ,Main Oscillator Selection Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
bitfld.long 0x00 20. " FOS ,Clock Failure Detector Fault Output Status" "Inactive,Active"
|
|
bitfld.long 0x00 19. " CFDS ,Clock Failure Detector Status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CFDEV ,Clock Failure Detector Event" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " MOSCRCS ,Main On-Chip RC Oscillator Status" "Not stabilized,Stabilized"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OSCSELS ,Slow Clock Oscillator Selection" "Internal-RC,External-32kHz"
|
|
bitfld.long 0x00 6. " LOCKU ,UPLL Clock Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCXTS ,Main XTAL Oscillator Status" "Not stabilized,Stabilized"
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,PLL Charge Pump Current Register"
|
|
bitfld.long 0x00 0. " ICPLLA ,Charge Pump Current" "Low,High"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PMC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
in
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 28. " EN ,Selected Peripheral clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor Value" "MCK,MCK/2,MCK/4,MCK/8"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read mode,Write mode"
|
|
sif (cpu()=="AT91SAM9G15")
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" "AIC,SYS,PIOA|PIOB,PIOC|PIOD,SMD,USART0,USART1,USART2,Reserved,TWI0,TWI1,TWI2,HSMCI0,SPI0,SPI1,UART0,UART1,TC0|TC1,PWM,ADC,DMAC0,DMAC1,UHPHS,UDPHS,Reserved,LCDC,HSMCI1,Reserved,SSC,Reserved,Reserved,AIC,?..."
|
|
elif (cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" "AIC,SYS,PIOA|PIOB,PIOC|PIOD,SMD,USART0,USART1,USART2,USART3,TWI0,TWI1,TWI2,HSMCI0,SPI0,SPI1,UART0,UART1,TC0|TC1,PWM,ADC,DMAC0,DMAC1,UHPHS,UDPHS,EMAC,ISI,HSMCI1,Reserved,SSC,Reserved,Reserved,AIC,?..."
|
|
elif (cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" "AIC,SYS,PIOA|PIOB,PIOC|PIOD,SMD,USART0,USART1,USART2,Reserved,TWI0,TWI1,TWI2,HSMCI0,SPI0,SPI1,UART0,UART1,TC0|TC1,PWM,ADC,DMAC0,DMAC1,UHPHS,UDPHS,EMAC,LCDC,HSMCI1,Reserved,SSC,Reserved,Reserved,AIC,?..."
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G35")
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
tree "PIOA"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOA_ABCDSR1,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "TWCK0/ETXEN,SPI1_NPCS2/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "TWD0/EMDC,SPI1_NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "TIOB2/Reserved,RF/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "TIOB1/Reserved,RK/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "TIOB0/Reserved,RD/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "TCLK2/Reserved,TD/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "TCLK1/Reserved,TF/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "TCLK0/Reserved,TK/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "TIOA2/Reserved,SPI1_SPCK/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "TIOA1/Reserved,SPI1_MOSI/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "TIOA0/Reserved,SPI1_MISO/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "SPI0_SPCK/Reserved,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "SPI0_MOSI/Reserved,MCI1_CDA/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "SPI0_MISO/Reserved,MCI1_DA0/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "RXD2/Reserved,SPI1_NPCS0/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "TXD2/Reserved,SPI0_NPCS1/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "SCK0/Reserved,MCI1_DA3/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "CTS0/ETX1,MCI1_DA2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "RTS0/ETX0,MCI1_DA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "RXD0/Reserved,SPI0_NPCS2/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "TXD0/Reserved,SPI1_NPCS1/D"
|
|
line.long 0x04 "PIOA_ABCDSR2,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "TWCK0/SPI1_NPCS2,ETXEN/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "TWD0/SPI1_NPCS3,EMDC/D"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "TIOB2/RF,High"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "TIOB1/RK,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "TIOB0/RD,High"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "TCLK2/TD,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "TCLK1/TF,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "TCLK0/TK,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "TIOA2/SPI1_SPCK,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "TIOA1/SPI1_MOSI,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "TIOA0/SPI1_MISO,High"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "SPI0_SPCK/MCI1_CK,High"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "SPI0_MOSI/MCI1_CDA,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "SPI0_MISO/MCI1_DA0,High"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "RXD2/SPI1_NPCS0,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "TXD2/SPI0_NPCS1,High"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "SCK0/MCI1_DA3,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "CTS0/MCI1_DA2,ETX1/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "RTS0/MCI1_DA1,ETX0/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "RXD0/SPI0_NPCS2,High"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "TXD0/SPI1_NPCS1,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOA_IFSCSR,PIOA Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOA_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOA_PPDSR,PIOA Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOA_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOA_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOA_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOA_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOA_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOA_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOA_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOA_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOB_ABCDSR1,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "IRQ/Reserved,ADTRG/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "Low,PWM3/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "Low,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "Low,PWM1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "Low,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "ETX1/Reserved,PCK0/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "ETX0/Reserved,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "ETXEN/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "EMDC/Reserved,High"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "EMDIO/Reserved,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "ETXCK/Reserved,TWD2/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "ERXER/Reserved,SPI0_NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "RTS0/ETX0,MCI1_DA1/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "ERX1/Reserved,CTS2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "ERX0/Reserved,RTS2/D"
|
|
line.long 0x04 "PIOB_ABCDSR2,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "IRQ/ADTRG,High"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "Reserved/PWM3,High"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "Reserved/PWM2,High"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "Reserved/PWM1,High"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "Reserved/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "ETX1/PCK0,High"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "ETX0/PCK1,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "ETXEN/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "EMDC/Reserved,High"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "EMDIO/TWCK2,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "ETXCK/TWD2,High"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "ERXDV/SPI0_NPCS3,High"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "ERXER/SCK2,High"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "ERX1/CTS2,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "ERX0/RTS2,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOB_IFSCSR,PIOB Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOB_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOB_PPDSR,PIOB Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOB_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOB_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOB_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOB_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOB_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOB_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOB_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOB_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOC_ABCDSR1,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "FIQ/PCK1,High"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "LCDPCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "LCDDEN/SCK1,High"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "LCDHSYNC/CTS1,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "LCDVSYNC/RTS1,High"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "LCDPWM/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "LCDDISP/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "LCDDAT23/Reserved,High"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "LCDDAT22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "LCDDAT21/PWM3,High"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "LCDDAT20/PWM2,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "LCDDAT19/PWM1,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "LCDDAT18/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "LCDDAT17/URXD1,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "LCDDAT16/UTXD1,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "LCDDAT15/PCK0,High"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "LCDDAT14/TCLK5,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "LCDDAT13/TIOB5,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "LCDDAT12/TIOA5,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "LCDDAT11/PWM1,MCI1_DA0/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "LCDDAT10/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "LCDDAT9/URXD0,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "LCDDAT8/UTXD0,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "LCDDAT7/TCLK4,SPI0_NPCS1/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "LCDDAT6/TIOB4,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "LCDDAT5/TIOA4,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "LCDDAT4/TCLK3,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "LCDDAT3/TIOB3,High"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "LCDDAT2/TIOA3,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "LCDDAT1/TWCK1,High"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "LCDDAT0/TWD1,High"
|
|
line.long 0x04 "PIOC_ABCDSR2,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "FIQ/Reserved,PCK1/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "LCDPCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "LCDDEN/Reserved,SCK1/D"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "LCDHSYNC/Reserved,CTS1/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "LCDVSYNC/Reserved,RTS1"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "LCDPWM/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "LCDDISP/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "LCDDAT23/Reserved,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "LCDDAT22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "LCDDAT21/Reserved,PWM3/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "LCDDAT20/Reserved,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "LCDDAT19/Reserved,PWM1/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "LCDDAT18/Reserved,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "LCDDAT17/Reserved,URXD1/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "LCDDAT16/Reserved,UTXD1/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "LCDDAT15/Reserved,PCK0/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "LCDDAT14/Reserved,TCLK5/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "LCDDAT13/Reserved,TIOB5/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "LCDDAT12/Reserved,TIOA5/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "LCDDAT11/Reserved,PWM1/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "LCDDAT10/Reserved,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "LCDDAT9/Reserved,URXD0/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "LCDDAT8/Reserved,UTXD0/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "LCDDAT7/Reserved,TCLK4/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "LCDDAT6/Reserved,TIOB4/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "LCDDAT5/Reserved,TIOA4/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "LCDDAT4/Reserved,TCLK3/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "LCDDAT3/Reserved,TIOB3/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "LCDDAT2/Reserved,TIOA3/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "LCDDAT1/Reserved,TWCK1/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "LCDDAT0/Reserved,TWD1/D"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOC_IFSCSR,PIOC Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOC_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOC_PPDSR,PIOC Pad Pull Down Status Register"
|
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setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOC_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOC_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOC_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOC_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOC_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOC_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOC_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOC_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xfffffA00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOD_ABCDSR1,PIOD Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "D31/Reserved,NCS5/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "D30/Reserved,NCS4/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "D29/Reserved,NCS2/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "D28/Reserved,A25/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "D27/Reserved,A24/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "D26/Reserved,A23/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "D25/Reserved,A20/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "D24/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "D23/Reserved,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "D22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "D21/Reserved,High"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "D20/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "D19/Reserved,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "D18/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "D17/Reserved,High"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "D16/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "NWAIT/Reserved,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "NCS3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "A22|NANDCLE/Reserved,High"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "A21|NANDALE/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "NANDWE/Reserved,High"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "NANDOE/Reserved,High"
|
|
line.long 0x04 "PIOD_ABCDSR2,PIOD Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "D31/NCS5,High"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "D30/NCS4,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "D29/NCS2,High"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "D28/A25,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "D27/A24,High"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "D26/A23,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "D25/A20,High"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "D24/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "D23/Reserved,High"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "D22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "D21/Reserved,High"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "D20/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "D19/Reserved,High"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "D18/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "D17/Reserved,High"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "D16/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "NWAIT/Reserved,High"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "NCS3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "A22|NANDCLE/Reserved,High"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "A21|NANDALE/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "NANDWE/Reserved,High"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "NANDOE/Reserved,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOD_IFSCSR,PIOD Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOD_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOD_PPDSR,PIOD Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOD_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOD_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOD_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOD_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOD_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOD_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOD_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOD_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G25")
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
tree "PIOA"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOA_ABCDSR1,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "TWCK0/ETXEN,SPI1_NPCS2/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "TWD0/EMDC,SPI1_NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "TIOB2/Reserved,RF/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "TIOB1/Reserved,RK/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "TIOB0/Reserved,RD/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "TCLK2/Reserved,TD/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "TCLK1/Reserved,TF/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "TCLK0/Reserved,TK/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "TIOA2/Reserved,SPI1_SPCK/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "TIOA1/Reserved,SPI1_MOSI/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "TIOA0/Reserved,SPI1_MISO/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "SPI0_SPCK/Reserved,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "SPI0_MOSI/Reserved,MCI1_CDA/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "SPI0_MISO/Reserved,MCI1_DA0/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "RXD2/Reserved,SPI1_NPCS0/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "TXD2/Reserved,SPI0_NPCS1/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "SCK0/ETXER,MCI1_DA3/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "CTS0/ETX1,MCI1_DA2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "RTS0/ETX0,MCI1_DA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "RXD0/Reserved,SPI0_NPCS2/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "TXD0/Reserved,SPI1_NPCS1/D"
|
|
line.long 0x04 "PIOA_ABCDSR2,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "TWCK0/SPI1_NPCS2,ETXEN/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "TWD0/SPI1_NPCS3,EMDC/D"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "TIOB2/RF,High"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "TIOB1/RK,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "TIOB0/RD,High"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "TCLK2/TD,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "TCLK1/TF,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "TCLK0/TK,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "TIOA2/SPI1_SPCK,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "TIOA1/SPI1_MOSI,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "TIOA0/SPI1_MISO,High"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "SPI0_SPCK/MCI1_CK,High"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "SPI0_MOSI/MCI1_CDA,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "SPI0_MISO/MCI1_DA0,High"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "RXD2/SPI1_NPCS0,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "TXD2/SPI0_NPCS1,High"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "SCK0/MCI1_DA3,ETXER/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "CTS0/MCI1_DA2,ETX1/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "RTS0/MCI1_DA1,ETX0/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "RXD0/SPI0_NPCS2,High"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "TXD0/SPI1_NPCS1,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOA_IFSCSR,PIOA Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOA_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOA_PPDSR,PIOA Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOA_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOA_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOA_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOA_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOA_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOA_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOA_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOA_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
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|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
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|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOB_ABCDSR1,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "IRQ/Reserved,ADTRG/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "ECOL/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "ECRS/Reserved,High"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "ERXCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "ERX3/Reserved,PWM3/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "ERX2/Reserved,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "ETX3/Reserved,PWM1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "Low,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "ETX1/Reserved,PCK0/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "ETX0/Reserved,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "ETXER/Reserved,High"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "ETXEN/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "EMDC/Reserved,High"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "EMDIO/Reserved,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "ETXCK/Reserved,TWD2/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "ERXER/Reserved,SPI0_NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "RTS0/ETX0,MCI1_DA1/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "ERX1/Reserved,CTS2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "ERX0/Reserved,RTS2/D"
|
|
line.long 0x04 "PIOB_ABCDSR2,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "IRQ/ADTRG,High"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "ECOL/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "ECRS/Reserved,High"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "ERXCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "ERX3/PWM3,High"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "ERX2/PWM2,High"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "ETX3/PWM1,High"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "ETX2/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "ETX1/PCK0,High"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "ETX0/PCK1,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "ETXER/Reserved,High"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "ETXEN/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "EMDC/Reserved,High"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "EMDIO/TWCK2,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "ETXCK/TWD2,High"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "ERXDV/SPI0_NPCS3,High"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "ERXER/SCK2,High"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "ERX1/CTS2,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "ERX0/RTS2,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOB_IFSCSR,PIOB Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOB_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOB_PPDSR,PIOB Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOB_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOB_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOB_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOB_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOB_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOB_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOB_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOB_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOC_ABCDSR1,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "FIQ/PCK1,High"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "Reserved/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "Reserved/SCK1,High"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "Reserved/CTS1,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "Reserved/RTS1,High"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "Reserved/Reserved,SCK3/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "Reserved/Low,CTS3/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "Reserved/Reserved,RTS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "Reserved/Reserved,RXD3/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "Reserved/Reserved,TXD3/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "Reserved/PWM3,High"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "Reserved/PWM2,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "Reserved/PWM1,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "Reserved/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "Reserved/URXD1,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "Reserved/UTXD1,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "Reserved/PCK0,ISI_MCK/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "Reserved/TCLK5,ISI_HSYNC/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "Reserved/TIOB5,ISI_VSYNC/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "Reserved/TIOA5,ISI_PCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "Reserved/PWM1,ISI_D11/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "Reserved/PWM0,ISI_D10/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "Reserved/URXD0,ISI_D9/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "Reserved/UTXD0,ISI_D8/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "Reserved/TCLK4,ISI_D7/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "Reserved/TIOB4,ISI_D6/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "Reserved/TIOA4,ISI_D5/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "Reserved/TCLK3,ISI_D4/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "Reserved/TIOB3,ISI_D3/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "Reserved/TIOA3,ISI_D2/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "Reserved/TWCK1,ISI_D1/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "Reserved/TWD1,ISI_D0/D"
|
|
line.long 0x04 "PIOC_ABCDSR2,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "FIQ/Reserved,PCK1/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "Low,SCK1/D"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "Low,CTS1/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "Low,RTS1"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "Reserved/SCK3,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "Reserved/CTS3,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "Reserved/RTS3,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "Reserved/RXD3,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "Reserved/TXD3,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "Low,PWM3/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "Low,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "Low,PWM1/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "Low,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "Low,URXD1/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "Low,UTXD1/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_MCK,PCK0/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_HSYNC,TCLK5/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_VSYNC,TIOB5/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_PCK,TIOA5/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_PCK,PWM1/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D11,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D10,URXD0/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D9,UTXD0/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D8,TCLK4/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D6,TIOB4/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D5,TIOA4/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D4,TCLK3/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D3,TIOB3/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D2,TIOA3/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D1,TWCK1/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "Reserved/ISI_D0,TWD1/D"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOC_IFSCSR,PIOC Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOC_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOC_PPDSR,PIOC Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOC_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOC_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOC_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOC_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOC_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOC_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOC_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOC_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xfffffA00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOD_ABCDSR1,PIOD Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "D31/Reserved,NCS5/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "D30/Reserved,NCS4/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "D29/Reserved,NCS2/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "D28/Reserved,A25/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "D27/Reserved,A24/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "D26/Reserved,A23/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "D25/Reserved,A20/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "D24/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "D23/Reserved,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "D22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "D21/Reserved,High"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "D20/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "D19/Reserved,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "D18/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "D17/Reserved,High"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "D16/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "NWAIT/Reserved,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "NCS3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "A22|NANDCLE/Reserved,High"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "A21|NANDALE/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "NANDWE/Reserved,High"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "NANDOE/Reserved,High"
|
|
line.long 0x04 "PIOD_ABCDSR2,PIOD Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "D31/NCS5,High"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "D30/NCS4,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "D29/NCS2,High"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "D28/A25,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "D27/A24,High"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "D26/A23,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "D25/A20,High"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "D24/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "D23/Reserved,High"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "D22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "D21/Reserved,High"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "D20/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "D19/Reserved,High"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "D18/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "D17/Reserved,High"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "D16/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "NWAIT/Reserved,High"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "NCS3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "A22|NANDCLE/Reserved,High"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "A21|NANDALE/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "NANDWE/Reserved,High"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "NANDOE/Reserved,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOD_IFSCSR,PIOD Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOD_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOD_PPDSR,PIOD Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOD_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOD_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOD_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOD_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOD_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOD_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOD_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOD_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G15")
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
tree "PIOA"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
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|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
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|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOA_ABCDSR1,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "TWCK0/Reserved,SPI1_NPCS2/D"
|
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bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "TWD0/Reserved,SPI1_NPCS3/D"
|
|
textline " "
|
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bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "TIOB2/Reserved,RF/D"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "TIOB1/Reserved,RK/D"
|
|
textline " "
|
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bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "TIOB0/Reserved,RD/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "TCLK2/Reserved,TD/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "TCLK1/Reserved,TF/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "TCLK0/Reserved,TK/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "TIOA2/Reserved,SPI1_SPCK/D"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "TIOA1/Reserved,SPI1_MOSI/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "TIOA0/Reserved,SPI1_MISO/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "SPI0_SPCK/Reserved,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "SPI0_MOSI/Reserved,MCI1_CDA/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "SPI0_MISO/Reserved,MCI1_DA0/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "RXD2/Reserved,SPI1_NPCS0/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "TXD2/Reserved,SPI0_NPCS1/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "SCK0/Reserved,MCI1_DA3/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "CTS0/Reserved,MCI1_DA2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "RTS0/Reserved,MCI1_DA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "RXD0/Reserved,SPI0_NPCS2/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "TXD0/Reserved,SPI1_NPCS1/D"
|
|
line.long 0x04 "PIOA_ABCDSR2,PIOA Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "TWCK0/SPI1_NPCS2,High"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "TWD0/SPI1_NPCS3,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "TIOB2/RF,High"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "TIOB1/RK,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "TIOB0/RD,High"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "TCLK2/TD,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "TCLK1/TF,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "TCLK0/TK,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "TIOA2/SPI1_SPCK,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "TIOA1/SPI1_MOSI,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "TIOA0/SPI1_MISO,High"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "MCI0_DA3/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "MCI0_DA2/Reserved,High"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "MCI0_DA1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "MCI0_CK/Reserved,High"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "MCI0_CDA/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "MCI0_DA0/Reserved,High"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "SPI0_NPCS0/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "SPI0_SPCK/MCI1_CK,High"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "SPI0_MOSI/MCI1_CDA,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "SPI0_MISO/MCI1_DA0,High"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "DTXD/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "DRXD/Reserved,High"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "RXD2/SPI1_NPCS0,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "TXD2/SPI0_NPCS1,High"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "RXD1/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "TXD1/Reserved,High"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "SCK0/MCI1_DA3,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "CTS0/MCI1_DA2,High"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "RTS0/MCI1_DA1,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "RXD0/SPI0_NPCS2,High"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "TXD0/SPI1_NPCS1,High"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOA_IFSCSR,PIOA Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOA_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOA_PPDSR,PIOA Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
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textline " "
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
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line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
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setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
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setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
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setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
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setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOA_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOA_ELSR,Edge/Level Status Register"
|
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setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOA_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOA_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOA_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOA_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOA_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOA_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOB_ABCDSR1,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "IRQ/Reserved,ADTRG/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "Low,PWM3/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "Low,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "Low,PWM1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "Low,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "Low,PCK0/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "Low,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "Low,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "Low,TWD2/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "Low,SPI0_NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "Low,SCK2/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "Low,CTS2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "Low,RTS2/D"
|
|
line.long 0x04 "PIOB_ABCDSR2,PIOB Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "IRQ/ADTRG,High"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "Low,High"
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textline " "
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bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "Reserved/PWM3,High"
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bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "Reserved/PWM2,High"
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textline " "
|
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bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "Reserved/PWM1,High"
|
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bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "Reserved/PWM0,High"
|
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textline " "
|
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bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "Reserved/PCK0,High"
|
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bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "Reserved/PCK1,High"
|
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textline " "
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bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "Low,High"
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bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "Low,High"
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textline " "
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bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "Low,High"
|
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bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "Reserved/TWCK2,High"
|
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textline " "
|
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bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "Reserved/TWD2,High"
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bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "Reserved/SPI0_NPCS3,High"
|
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textline " "
|
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bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "Reserved/SCK2,High"
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bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "Reserved/CTS2,High"
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textline " "
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bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "Reserved/RTS2,High"
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group.long 0x88++0x3
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line.long 0x0 "PIOB_IFSCSR,PIOB Input Filter Slow Clock Status Register"
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
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textline " "
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
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setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
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textline " "
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
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setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
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textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
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setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
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textline " "
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
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setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
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textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
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setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
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textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
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textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
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textline " "
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
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group.long 0x8C++0x03
|
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line.long 0x00 "PIOB_SCDR,Slow Clock Divider Debouncing Register"
|
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hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
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group.long 0x98++0x3
|
|
line.long 0x0 "PIOB_PPDSR,PIOB Pad Pull Down Status Register"
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
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textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOB_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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group.long 0xC8++0x3
|
|
line.long 0x0 "PIOB_ELSR,Edge/Level Status Register"
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOB_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOB_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOB_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOB_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOB_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOB_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOC_ABCDSR1,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select (A/C|B/D)" "FIQ/PCK1,High"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select (A/C|B/D)" "LCDPCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select (A/C|B/D)" "LCDDEN/SCK1,High"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select (A/C|B/D)" "LCDHSYNC/CTS1,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select (A/C|B/D)" "LCDVSYNC/RTS1,High"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select (A/C|B/D)" "LCDPWM/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select (A/C|B/D)" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select (A/C|B/D)" "LCDDISP/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select (A/C|B/D)" "LCDDAT23/Reserved,High"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select (A/C|B/D)" "LCDDAT22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "LCDDAT21/PWM3,High"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "LCDDAT20/PWM2,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "LCDDAT19/PWM1,High"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "LCDDAT18/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "LCDDAT17/URXD1,High"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "LCDDAT16/UTXD1,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "LCDDAT15/PCK0,High"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "LCDDAT14/TCLK5,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "LCDDAT13/TIOB5,MCI1_CK/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "LCDDAT12/TIOA5,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "LCDDAT11/PWM1,High"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "LCDDAT10/PWM0,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "LCDDAT9/URXD0,High"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "LCDDAT8/UTXD0,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "LCDDAT7/TCLK4,High"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "LCDDAT6/TIOB4,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "LCDDAT5/TIOA4,High"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "LCDDAT4/TCLK3,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "LCDDAT3/TIOB3,High"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "LCDDAT2/TIOA3,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "LCDDAT1/TWCK1,High"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "LCDDAT0/TWD1,High"
|
|
line.long 0x04 "PIOC_ABCDSR2,PIOC Peripheral A B C D Status Register"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select (A/B|C/D)" "FIQ/Reserved,PCK1/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select (A/B|C/D)" "LCDPCK/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select (A/B|C/D)" "LCDDEN/Reserved,SCK1/D"
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select (A/B|C/D)" "LCDHSYNC/Reserved,CTS1/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select (A/B|C/D)" "LCDVSYNC/Reserved,RTS1"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select (A/B|C/D)" "LCDPWM/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select (A/B|C/D)" "Low,High"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select (A/B|C/D)" "LCDDISP/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select (A/B|C/D)" "LCDDAT23/Reserved,High"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select (A/B|C/D)" "LCDDAT22/Reserved,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "LCDDAT21/Reserved,PWM3/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "LCDDAT20/Reserved,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "LCDDAT19/Reserved,PWM1/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "LCDDAT18/Reserved,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "LCDDAT17/Reserved,URXD1/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "LCDDAT16/Reserved,UTXD1/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "LCDDAT15/Reserved,PCK0/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "LCDDAT14/Reserved,TCLK5/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "LCDDAT13/Reserved,TIOB5/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "LCDDAT12/Reserved,TIOA5/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "LCDDAT11/Reserved,PWM1/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "LCDDAT10/Reserved,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "LCDDAT9/Reserved,URXD0/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "LCDDAT8/Reserved,UTXD0/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "LCDDAT7/Reserved,TCLK4/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "LCDDAT6/Reserved,TIOB4/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "LCDDAT5/Reserved,TIOA4/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "LCDDAT4/Reserved,TCLK3/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "LCDDAT3/Reserved,TIOB3/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "LCDDAT2/Reserved,TIOA3/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "LCDDAT1/Reserved,TWCK1/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "LCDDAT0/Reserved,TWD1/D"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PIOC_IFSCSR,PIOC Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIOC_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PIOC_PPDSR,PIOC Pad Pull Down Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Down Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Down Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Down Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Down Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Down Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Down Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Down Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Down Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Down Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Down Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
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setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
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setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOC_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Peripheral CD Status 31" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Peripheral CD Status 30" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Peripheral CD Status 29" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Peripheral CD Status 28" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Peripheral CD Status 27" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Peripheral CD Status 26" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Peripheral CD Status 25" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Peripheral CD Status 24" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Peripheral CD Status 23" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Peripheral CD Status 22" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOC_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOC_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Edge /Level Interrupt Source Selection 31" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Edge /Level Interrupt Source Selection 30" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Edge /Level Interrupt Source Selection 29" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Edge /Level Interrupt Source Selection 28" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Edge /Level Interrupt Source Selection 27" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Edge /Level Interrupt Source Selection 26" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Edge /Level Interrupt Source Selection 25" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Edge /Level Interrupt Source Selection 24" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Edge /Level Interrupt Source Selection 23" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Edge /Level Interrupt Source Selection 22" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOC_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status 30" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Lock Status 29" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,Lock Status 28" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Lock Status 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status 24" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Lock Status 23" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,Lock Status 22" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOC_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOC_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOC_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOC_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 30.--31. " LINE31 ,Drive of PIO line 31" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 28.--29. " LINE30 ,Drive of PIO line 30" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " LINE29 ,Drive of PIO line 29" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 24.--25. " LINE28 ,Drive of PIO line 28" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " LINE27 ,Drive of PIO line 27" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 20.--21. " LINE26 ,Drive of PIO line 26" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " LINE25 ,Drive of PIO line 25" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 16.--17. " LINE24 ,Drive of PIO line 24" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " LINE23 ,Drive of PIO line 23" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 12.--13. " LINE22 ,Drive of PIO line 22" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xfffffA00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x70++0x07
|
|
line.long 0x0 "PIOD_ABCDSR1,PIOD Peripheral A B C D Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select (A/C|B/D)" "D31/Reserved,NCS5/D"
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bitfld.long 0x00 20. " P20 ,Peripheral Select (A/C|B/D)" "D30/Reserved,NCS4/D"
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textline " "
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bitfld.long 0x00 19. " P19 ,Peripheral Select (A/C|B/D)" "D29/Reserved,NCS2/D"
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bitfld.long 0x00 18. " P18 ,Peripheral Select (A/C|B/D)" "D28/Reserved,A25/D"
|
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textline " "
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bitfld.long 0x00 17. " P17 ,Peripheral Select (A/C|B/D)" "D27/Reserved,A24/D"
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bitfld.long 0x00 16. " P16 ,Peripheral Select (A/C|B/D)" "D26/Reserved,A23/D"
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textline " "
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bitfld.long 0x00 15. " P15 ,Peripheral Select (A/C|B/D)" "D25/Reserved,A20/D"
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bitfld.long 0x00 14. " P14 ,Peripheral Select (A/C|B/D)" "D24/Reserved,High"
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textline " "
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bitfld.long 0x00 13. " P13 ,Peripheral Select (A/C|B/D)" "D23/Reserved,MCI1_CK/D"
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bitfld.long 0x00 12. " P12 ,Peripheral Select (A/C|B/D)" "D22/Reserved,High"
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textline " "
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bitfld.long 0x00 11. " P11 ,Peripheral Select (A/C|B/D)" "D21/Reserved,High"
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bitfld.long 0x00 10. " P10 ,Peripheral Select (A/C|B/D)" "D20/Reserved,High"
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textline " "
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bitfld.long 0x00 9. " P9 ,Peripheral Select (A/C|B/D)" "D19/Reserved,High"
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bitfld.long 0x00 8. " P8 ,Peripheral Select (A/C|B/D)" "D18/Reserved,High"
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textline " "
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bitfld.long 0x00 7. " P7 ,Peripheral Select (A/C|B/D)" "D17/Reserved,High"
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bitfld.long 0x00 6. " P6 ,Peripheral Select (A/C|B/D)" "D16/Reserved,High"
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textline " "
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bitfld.long 0x00 5. " P5 ,Peripheral Select (A/C|B/D)" "NWAIT/Reserved,High"
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bitfld.long 0x00 4. " P4 ,Peripheral Select (A/C|B/D)" "NCS3/Reserved,High"
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textline " "
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bitfld.long 0x00 3. " P3 ,Peripheral Select (A/C|B/D)" "A22|NANDCLE/Reserved,High"
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bitfld.long 0x00 2. " P2 ,Peripheral Select (A/C|B/D)" "A21|NANDALE/Reserved,High"
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textline " "
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bitfld.long 0x00 1. " P1 ,Peripheral Select (A/C|B/D)" "NANDWE/Reserved,High"
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bitfld.long 0x00 0. " P0 ,Peripheral Select (A/C|B/D)" "NANDOE/Reserved,High"
|
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line.long 0x04 "PIOD_ABCDSR2,PIOD Peripheral A B C D Status Register"
|
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bitfld.long 0x04 21. " P21 ,Peripheral Select (A/B|C/D)" "D31/NCS5,High"
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bitfld.long 0x04 20. " P20 ,Peripheral Select (A/B|C/D)" "D30/NCS4,High"
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textline " "
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bitfld.long 0x04 19. " P19 ,Peripheral Select (A/B|C/D)" "D29/NCS2,High"
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bitfld.long 0x04 18. " P18 ,Peripheral Select (A/B|C/D)" "D28/A25,High"
|
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textline " "
|
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bitfld.long 0x04 17. " P17 ,Peripheral Select (A/B|C/D)" "D27/A24,High"
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bitfld.long 0x04 16. " P16 ,Peripheral Select (A/B|C/D)" "D26/A23,High"
|
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textline " "
|
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bitfld.long 0x04 15. " P15 ,Peripheral Select (A/B|C/D)" "D25/A20,High"
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bitfld.long 0x04 14. " P14 ,Peripheral Select (A/B|C/D)" "D24/Reserved,High"
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textline " "
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bitfld.long 0x04 13. " P13 ,Peripheral Select (A/B|C/D)" "D23/Reserved,High"
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bitfld.long 0x04 12. " P12 ,Peripheral Select (A/B|C/D)" "D22/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 11. " P11 ,Peripheral Select (A/B|C/D)" "D21/Reserved,High"
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bitfld.long 0x04 10. " P10 ,Peripheral Select (A/B|C/D)" "D20/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 9. " P9 ,Peripheral Select (A/B|C/D)" "D19/Reserved,High"
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bitfld.long 0x04 8. " P8 ,Peripheral Select (A/B|C/D)" "D18/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 7. " P7 ,Peripheral Select (A/B|C/D)" "D17/Reserved,High"
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bitfld.long 0x04 6. " P6 ,Peripheral Select (A/B|C/D)" "D16/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 5. " P5 ,Peripheral Select (A/B|C/D)" "NWAIT/Reserved,High"
|
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bitfld.long 0x04 4. " P4 ,Peripheral Select (A/B|C/D)" "NCS3/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 3. " P3 ,Peripheral Select (A/B|C/D)" "A22|NANDCLE/Reserved,High"
|
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bitfld.long 0x04 2. " P2 ,Peripheral Select (A/B|C/D)" "A21|NANDALE/Reserved,High"
|
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textline " "
|
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bitfld.long 0x04 1. " P1 ,Peripheral Select (A/B|C/D)" "NANDWE/Reserved,High"
|
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bitfld.long 0x04 0. " P0 ,Peripheral Select (A/B|C/D)" "NANDOE/Reserved,High"
|
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group.long 0x88++0x3
|
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line.long 0x0 "PIOD_IFSCSR,PIOD Input Filter Slow Clock Status Register"
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
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setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
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setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
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group.long 0x8C++0x03
|
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line.long 0x00 "PIOD_SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
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group.long 0x98++0x3
|
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line.long 0x0 "PIOD_PPDSR,PIOD Pad Pull Down Status Register"
|
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setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Down Status 21" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Down Status 20" "Enabled,Disabled"
|
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setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Down Status 19" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Down Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Down Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Down Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Down Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Down Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Down Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Down Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Down Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Down Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Down Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Down Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Down Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Down Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Down Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Down Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Down Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Down Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Down Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Down Status 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PIOD_AIMMR,Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Peripheral CD Status 21" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Peripheral CD Status 20" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Peripheral CD Status 19" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Peripheral CD Status 18" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Peripheral CD Status 17" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Peripheral CD Status 16" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Peripheral CD Status 15" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Peripheral CD Status 14" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Peripheral CD Status 13" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Peripheral CD Status 12" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Peripheral CD Status 11" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Peripheral CD Status 10" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Peripheral CD Status 9" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Peripheral CD Status 8" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Peripheral CD Status 7" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Peripheral CD Status 6" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Peripheral CD Status 5" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Peripheral CD Status 4" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Peripheral CD Status 3" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Peripheral CD Status 2" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Peripheral CD Status 1" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Peripheral CD Status 0" "Both Edge detection,PIO_ELSR & PIO_FRLHSR"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PIOD_ELSR,Edge/Level Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PIOD_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Edge /Level Interrupt Source Selection 21" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Edge /Level Interrupt Source Selection 20" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Edge /Level Interrupt Source Selection 19" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Edge /Level Interrupt Source Selection 18" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Edge /Level Interrupt Source Selection 17" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Edge /Level Interrupt Source Selection 16" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Edge /Level Interrupt Source Selection 15" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Edge /Level Interrupt Source Selection 14" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Edge /Level Interrupt Source Selection 13" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Edge /Level Interrupt Source Selection 12" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Edge /Level Interrupt Source Selection 11" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Edge /Level Interrupt Source Selection 10" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Edge /Level Interrupt Source Selection 9" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Edge /Level Interrupt Source Selection 8" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Edge /Level Interrupt Source Selection 7" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Edge /Level Interrupt Source Selection 6" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Edge /Level Interrupt Source Selection 5" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Edge /Level Interrupt Source Selection 4" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Edge /Level Interrupt Source Selection 3" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Edge /Level Interrupt Source Selection 2" "Faling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Edge /Level Interrupt Source Selection 1" "Faling/Low,Rising/High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Edge /Level Interrupt Source Selection 0" "Faling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIOD_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status 21" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Lock Status 20" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " P19 ,Lock Status 19" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Lock Status 18" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Lock Status 17" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,Lock Status 16" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Lock Status 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status 12" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status 10" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Lock Status 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status 4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Lock Status 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status 0" "Not locked,Locked"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIOD_SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0" "Enabled,Disabled"
|
|
group.long 0x110++0x0B
|
|
line.long 0x00 "PIOD_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIOD_DRIVER1,PIO I/O Drive Register 1"
|
|
bitfld.long 0x04 30.--31. " LINE15 ,Drive of PIO line 15" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 28.--29. " LINE14 ,Drive of PIO line 14" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " LINE13 ,Drive of PIO line 13" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 24.--25. " LINE12 ,Drive of PIO line 12" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " LINE11 ,Drive of PIO line 11" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 20.--21. " LINE10 ,Drive of PIO line 10" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LINE9 ,Drive of PIO line 9" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 16.--17. " LINE8 ,Drive of PIO line 8" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " LINE7 ,Drive of PIO line 7" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 12.--13. " LINE6 ,Drive of PIO line 6" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " LINE5 ,Drive of PIO line 5" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 8.--9. " LINE4 ,Drive of PIO line 4" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " LINE3 ,Drive of PIO line 3" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 4.--5. " LINE2 ,Drive of PIO line 2" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " LINE1 ,Drive of PIO line 1" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x04 0.--1. " LINE0 ,Drive of PIO line 0" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
line.long 0x08 "PIOD_DRIVER2,PIO I/O Drive Register 2"
|
|
bitfld.long 0x08 10.--11. " LINE21 ,Drive of PIO line 21" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " LINE20 ,Drive of PIO line 20" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 6.--7. " LINE19 ,Drive of PIO line 19" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LINE18 ,Drive of PIO line 18" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " LINE17 ,Drive of PIO line 17" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
bitfld.long 0x08 0.--1. " LINE16 ,Drive of PIO line 16" "HI_DRIVE,ME_DRIVE,LO_DRIVE,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "DBGU (Debug Unit)"
|
|
base ad:0xfffff200
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGU_CR,Debug Unit Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBGU_MR,Debug Unit Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,No parity,No parity"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DBGU_IMR,Debug Unit Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " COMMRX_set/clr ,Mask COMMRX Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " COMMTX_set/clr ,Mask COMMTX Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " TXEMPTY_set/clr ,Mask TXEMPTY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PARE_set/clr ,Mask Parity Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " FRAME_set/clr ,Mask Framing Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRE_set/clr ,Mask Overrun Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXRDY_set/clr ,Disable TXRDY Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RXRDY_set/clr ,Mask RXRDY Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x14--0x17
|
|
line.long 0x0 "DBGU_SR,Debug Unit Status Register"
|
|
bitfld.long 0x0 31. " COMMRX ,Debug Communication Channel Read Status" "Inactive,Active"
|
|
bitfld.long 0x0 30. " COMMTX ,Debug Communication Channel Write Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 7. " PARE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x0 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
hgroup.long 0x18--0x1B
|
|
hide.long 0x0 "DBGU_RHR,Debug Unit Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "DBGU_THR,Debug Unit Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DBGU_BRGR,Debug Unit Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "DBGU_CIDR,Debug Unit Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "Not extended,Extended"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMless/on-chip Flash,Embedded Flash,ROM and Embedded,SRAM em ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "Reserved,1K bytes,2K bytes,6K bytes,112K bytes,4K bytes,80K bytes,160K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,96K bytes,512K bytes"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "None,8K bytes,16K bytes,32K bytes,Reserved,64K bytes,Reserved,128K bytes,Reserved,256K bytes,512K bytes,Reserved,1024K bytes,Reserved,2048K bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Reserved,ARM946ES,ARM7TDMI,Reserved,ARM920T,ARM926EJS,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Version of the Device"
|
|
line.long 0x4 "DBGU_EXID,Debug Unit Chip ID Extension Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DBGU_FNR,Debug Unit Force NTRST Register"
|
|
bitfld.long 0x00 0. " FNTRST ,Force NTRST" "Power-on reset,Held low"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "MATRIX (Bus Matrix)"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xffffea00
|
|
width 14.
|
|
group.long 0x00++0x2b
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x18 "MATRIX_MCFG6,Bus Matrix Master Configuration Register 6"
|
|
bitfld.long 0x18 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x1C "MATRIX_MCFG7,Bus Matrix Master Configuration Register 7"
|
|
bitfld.long 0x1C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x20 "MATRIX_MCFG8,Bus Matrix Master Configuration Register 8"
|
|
bitfld.long 0x20 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x24 "MATRIX_MCFG9,Bus Matrix Master Configuration Register 9"
|
|
bitfld.long 0x24 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x28 "MATRIX_MCFG10,Bus Matrix Master Configuration Register 10"
|
|
bitfld.long 0x28 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MATRIX_MCFG11,Bus Matrix Master Configuration Register 11"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS0,Bus Matrix Priority Register B for Slave 0 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS1,Bus Matrix Priority Register B for Slave 1 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS2,Bus Matrix Priority Register B for Slave 2 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x98++0x7
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS3,Bus Matrix Priority Register B for Slave 3 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x7
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS4,Bus Matrix Priority Register B for Slave 4 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA8++0x7
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A for Slave 5 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS5,Bus Matrix Priority Register B for Slave 5 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB0++0x7
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A for Slave 6 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS6,Bus Matrix Priority Register B for Slave 6 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB8++0x7
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A for Slave 7 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS7,Bus Matrix Priority Register B for Slave 7 Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x04 10.--11. " M11PR ,Master 11 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
bitfld.long 0x00 11. " RCB11 ,Remap Command Bit for Master 11" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " RCB10 ,Remap Command Bit for Master 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCB9 ,Remap Command Bit for Master 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RCB8 ,Remap Command Bit for Master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RCB7 ,Remap Command Bit for Master 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RCB6 ,Remap Command Bit for Master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for Master 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for Master 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for Master 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for Master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for Master 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for Master 0" "Disabled,Enabled"
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25")
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "CCFG_TCMR,Bus Matrix TCM Configuration Register"
|
|
bitfld.long 0x00 11. " TCM_NWS ,TCM Wait State" "0 wait state,1 wait state"
|
|
bitfld.long 0x00 4.--7. " DTCM_SIZE ,DTCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,Reserved,32-KB,64-KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ITCM_SIZE ,ITCM Enabled Memory Block Size" "0-KB,Reserved,Reserved,Reserved,Reserved,Reserved,32-KB,?..."
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "CCFG_VMCR,Bus Matrix Video Mode Configuration Register"
|
|
bitfld.long 0x00 0. " VDEC_SEL ,Video Mode Selection" "OFF,ON"
|
|
else
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "CCFG_DDRMPR,DDR Multi-Port Register"
|
|
bitfld.long 0x00 0. " DDRMP_DIS ,DDR Multi-Port Disable" "No,Yes"
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CCFG_EBICSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x00 25. " DDR_MP_EN ,DDR Multi-port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " NFD0_ON_D16 ,NAND Flash Databus Selection" "D0-D15,D16-D31"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EBI_DRIVE ,EBI I/O Drive Configuration" "Low,High"
|
|
bitfld.long 0x00 9. " EBI_DBPDC ,EBI Data Bus Pull-Down Configuration" "Pulled-down,Not pulled-down"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
bitfld.long 0x00 3. " EBI_CS3A ,EBI Chip Select 3 Assignment" "Only to SMC,SMC"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EBI_CS1A ,EBI Chip Select 1 Assignment" "SMC,DDR2SDR"
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25")
|
|
group.long 0x128++0x3
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46")
|
|
line.long 0x0 "CCFG_EBICSA,EBI Chip Select Assignment Register"
|
|
else
|
|
line.long 0x0 "EBI1_CSA,EBI Chip Select Assignment Register"
|
|
endif
|
|
bitfld.long 0x0 18. " DDR_DRIVE ,DDR2 dedicated port I/O slew rate selection" "Low,High"
|
|
bitfld.long 0x0 16.--17. " EBI_DRIVE ,EBI I/O Drive Configuration" "1.8V Low,3.3V Low,1.8V High,3.3V High"
|
|
textline " "
|
|
bitfld.long 0x0 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL1"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL0"
|
|
else
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
endif
|
|
bitfld.long 0x0 3. " EBI_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EBI_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
endif
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
rgroup.long 0x1e8++0x3
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xffffde00
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x18 "MATRIX_MCFG6,Bus Matrix Master Configuration Register 6"
|
|
bitfld.long 0x18 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x1C "MATRIX_MCFG7,Bus Matrix Master Configuration Register 7"
|
|
bitfld.long 0x1C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x20 "MATRIX_MCFG8,Bus Matrix Master Configuration Register 8"
|
|
bitfld.long 0x20 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
line.long 0x24 "MATRIX_MCFG9,Bus Matrix Master Configuration Register 9"
|
|
bitfld.long 0x24 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
group.long 0x28++0x03
|
|
line.long 0x0 "MATRIX_MCFG$2,Bus Matrix Master Configuration Register $2"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
group.long 0x40++0x27
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x4 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x14 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x14 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x18 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x18 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x1C "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x1C 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x1C 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x20 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
bitfld.long 0x20 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
line.long 0x24 "MATRIX_SCFG9,Bus Matrix Slave Configuration Register 9"
|
|
bitfld.long 0x24 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS0,Bus Matrix Priority Register B for Slave 0 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS1,Bus Matrix Priority Register B for Slave 1 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS2,Bus Matrix Priority Register B for Slave 2 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x98++0x7
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS3,Bus Matrix Priority Register B for Slave 3 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x7
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS4,Bus Matrix Priority Register B for Slave 4 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xA8++0x7
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A for Slave 5 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS5,Bus Matrix Priority Register B for Slave 5 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB0++0x7
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A for Slave 6 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS6,Bus Matrix Priority Register B for Slave 6 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xB8++0x7
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A for Slave 7 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS7,Bus Matrix Priority Register B for Slave 7 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xC0++0x7
|
|
line.long 0x00 "MATRIX_PRAS8,Bus Matrix Priority Register A for Slave 8 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS8,Bus Matrix Priority Register B for Slave 8 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0xC8++0x7
|
|
line.long 0x00 "MATRIX_PRAS9,Bus Matrix Priority Register A for Slave 9 Register"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x04 "MATRIX_PRBS9,Bus Matrix Priority Register B for Slave 9 Register"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
bitfld.long 0x04 8.--9. " M10PR ,Master 9 Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
bitfld.long 0x00 10. " RCB10 ,Remap Command Bit for Master 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RCB9 ,Remap Command Bit for Master 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RCB8 ,Remap Command Bit for Master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RCB7 ,Remap Command Bit for Master 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RCB6 ,Remap Command Bit for Master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for Master 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for Master 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for Master 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for Master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for Master 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for Master 0" "Disabled,Enabled"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CCFG_EBICSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x0 25. " DDR_MP_EN ,DDR Multi-port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " NFD0_ON_D16 ,NAND Flash Databus Selection" "D0-D15,D16-D31"
|
|
textline " "
|
|
bitfld.long 0x0 17. " EBI_DRIVE ,EBI I/O Drive Configuration" "Low,High"
|
|
bitfld.long 0x0 9. " EBI_DBPDC ,EBI1 Data Bus Pull-Down Configuration" "Pulled-down,Not pulled-down"
|
|
textline " "
|
|
bitfld.long 0x0 8. " EBI_DBPUC ,EBI1 Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
bitfld.long 0x0 3. " EBI_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/NAND flash logic"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EBI_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,DDR2SDR"
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G10")
|
|
base ad:0xffffee00
|
|
width 14.
|
|
sif (cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MATRIX_MCFG,Bus Matrix Master Configuration Register"
|
|
bitfld.long 0x00 1. " RCB1 ,AHB Master 1 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 0. " RCB0 ,AHB Master 0 Remap Command Bit" "No effect,Remapped"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "MATRIX_MCFG,Bus Matrix Master Configuration Register"
|
|
bitfld.long 0x00 4. " RCB4 ,AHB Master 4 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 3. " RCB3 ,AHB Master 3 Remap Command Bit" "No effect,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RCB2 ,AHB Master 2 Remap Command Bit" "No effect,Remapped"
|
|
bitfld.long 0x00 1. " RCB1 ,AHB Master 1 Remap Command Bit" "No effect,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCB0 ,AHB Master 0 Remap Command Bit" "No effect,Remapped"
|
|
line.long 0x4 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x14 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x14 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "EBI_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x00 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
bitfld.long 0x00 3. " EBI_CS3A ,EBI Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EBI_CS1A ,EBI Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
line.long 0x4 "USB_PUCR,USB Pad Pull-Up Control Register"
|
|
bitfld.long 0x4 30. " UDP_PUP_ON ,UDP Pad Pull-Up Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
else
|
|
base ad:0xffffea00
|
|
width 14.
|
|
group.long 0x00++0x17
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x0 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x0 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x0 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x4 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x4 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x4 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x4 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x8 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x8 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x8 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x8 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0xC "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0xC 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0xC 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0xC 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
line.long 0x10 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x10 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
bitfld.long 0x10 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3"
|
|
width 14.
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for AHB Master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for AHB Master 0" "Disabled,Enabled"
|
|
group.long 0x11c++3
|
|
line.long 0x0 "EBI1_CSA,EBI Chip Select Assignment Register"
|
|
bitfld.long 0x0 17. " IOSR ,I/O Slew Rate selection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 16. " VDDIOMSEL ,Memory voltage selection" "1.8V,3.3V"
|
|
bitfld.long 0x0 8. " EBI1_DBPUC ,EBI1 Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC,SMC/CFL2"
|
|
bitfld.long 0x0 4. " EBI1_CS4A ,EBI1 Chip Select 4 Assignment" "SMC,SMC/CFL1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EBI1_CS3A ,EBI1 Chip Select 3 Assignment" "SMC,SMC/SML"
|
|
bitfld.long 0x0 1. " EBI1_CS1A ,EBI1 Chip Select 1 Assignment" "SMC,SDRAMC"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
tree "PMECC (Programmable Multibit ECC Controller)"
|
|
base ad:0xFFFFE000
|
|
width 15.
|
|
if ((d.l(ad:0xFFFFE000)&0x10000)==0x10000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMECC_CFG,PMECC Configuration Register"
|
|
bitfld.long 0x00 20. " AUTO ,Automatic Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPAREEN ,Spare Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NANDWR ,NAND Write Access" "Read,Write"
|
|
bitfld.long 0x00 8.--9. " PAGESIZE ,Number of Sectors in the Page" "1 sector,2 sectors,4 sectors,8 sectors"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SECTORSZ ,Sector Size" "512 bytes,1024 bytes"
|
|
bitfld.long 0x00 0.--2. " BCH_ERR ,Error Correct Capability" "2 errors,4 errors,8 errors,12 errors,24 errors,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMECC_CFG,PMECC Configuration Register"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPAREEN ,Spare Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NANDWR ,NAND Write Access" "Read,Write"
|
|
bitfld.long 0x00 8.--9. " PAGESIZE ,Number of Sectors in the Page" "1 sector,2 sectors,4 sectors,8 sectors"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SECTORSZ ,Sector Size" "512 bytes,1024 bytes"
|
|
bitfld.long 0x00 0.--2. " BCH_ERR ,Error Correct Capability" "2 errors,4 errors,8 errors,12 errors,24 errors,?..."
|
|
endif
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "PMECC_SAREA,PMECC Spare Area Size Register"
|
|
hexmask.long.word 0x00 0.--8. 1. 1. " SPARESIZE ,Spare Area Size"
|
|
line.long 0x04 "PMECC_SADDR,PMECC Start Address Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " STARTADDR ,ECC Area Start Address"
|
|
line.long 0x08 "PMECC_EADDR,PMECC End Address Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " ENDADDR ,ECC Area End Address"
|
|
line.long 0x0C "PMECC_CLK,PMECC Clock Control Register"
|
|
bitfld.long 0x0C 0.--2. " CLKCTRL ,Clock Control Register" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "PMECC_CTRL,PMECC Control Register"
|
|
bitfld.long 0x00 5. " DISABLE ,PMECC Module Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " ENABLE ,PMECC Module Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " USER ,Start a User Mode Phase" "No effect,Start"
|
|
bitfld.long 0x00 1. " DATA ,Start a Data Phase" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RST ,Reset the PMECC Module" "No effect,Reset"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMECC_SR,PMECC Status Register"
|
|
bitfld.long 0x00 4. " ENABLE ,PMECC Module Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSY ,The Kernel of the PMECC is Busy" "Idle,Busy"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PMECC_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ERRIM_set/clr ,Error Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "PMECC_ISR,PMECC Interrupt Status Register"
|
|
bitfld.long 0x00 7. " ERRIS[7] ,Error Interrupt Status bit7" "No error,Error"
|
|
bitfld.long 0x00 6. " ERRIS[6] ,Error Interrupt Status bit6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERRIS[5] ,Error Interrupt Status bit5" "No error,Error"
|
|
bitfld.long 0x00 4. " ERRIS[4] ,Error Interrupt Status bit4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERRIS[3] ,Error Interrupt Status bit3" "No error,Error"
|
|
bitfld.long 0x00 2. " ERRIS[2] ,Error Interrupt Status bit2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERRIS[1] ,Error Interrupt Status bit1" "No error,Error"
|
|
bitfld.long 0x00 0. " ERRIS[0] ,Error Interrupt Status bit0" "No error,Error"
|
|
tree "PMECC ECC Registers"
|
|
rgroup.long 0x40++0x2B
|
|
line.long 0x0 "PMECC_ECC0_0,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_0,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_0,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_0,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_0,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_0,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_0,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_0,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_0,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_0,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_0,PMECC ECC 10 Register"
|
|
rgroup.long 0x80++0x2B
|
|
line.long 0x0 "PMECC_ECC0_1,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_1,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_1,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_1,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_1,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_1,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_1,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_1,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_1,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_1,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_1,PMECC ECC 10 Register"
|
|
rgroup.long 0xC0++0x2B
|
|
line.long 0x0 "PMECC_ECC0_2,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_2,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_2,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_2,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_2,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_2,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_2,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_2,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_2,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_2,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_2,PMECC ECC 10 Register"
|
|
rgroup.long 0x100++0x2B
|
|
line.long 0x0 "PMECC_ECC0_3,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_3,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_3,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_3,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_3,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_3,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_3,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_3,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_3,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_3,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_3,PMECC ECC 10 Register"
|
|
rgroup.long 0x140++0x2B
|
|
line.long 0x0 "PMECC_ECC0_4,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_4,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_4,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_4,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_4,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_4,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_4,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_4,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_4,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_4,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_4,PMECC ECC 10 Register"
|
|
rgroup.long 0x180++0x2B
|
|
line.long 0x0 "PMECC_ECC0_5,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_5,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_5,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_5,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_5,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_5,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_5,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_5,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_5,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_5,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_5,PMECC ECC 10 Register"
|
|
rgroup.long 0x1C0++0x2B
|
|
line.long 0x0 "PMECC_ECC0_6,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_6,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_6,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_6,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_6,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_6,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_6,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_6,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_6,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_6,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_6,PMECC ECC 10 Register"
|
|
rgroup.long 0x200++0x2B
|
|
line.long 0x0 "PMECC_ECC0_7,PMECC ECC 0 Register"
|
|
line.long 0x4 "PMECC_ECC1_7,PMECC ECC 1 Register"
|
|
line.long 0x8 "PMECC_ECC2_7,PMECC ECC 2 Register"
|
|
line.long 0xC "PMECC_ECC3_7,PMECC ECC 3 Register"
|
|
line.long 0x10 "PMECC_ECC4_7,PMECC ECC 4 Register"
|
|
line.long 0x14 "PMECC_ECC5_7,PMECC ECC 5 Register"
|
|
line.long 0x18 "PMECC_ECC6_7,PMECC ECC 6 Register"
|
|
line.long 0x1C "PMECC_ECC7_7,PMECC ECC 7 Register"
|
|
line.long 0x20 "PMECC_ECC8_7,PMECC ECC 8 Register"
|
|
line.long 0x24 "PMECC_ECC9_7,PMECC ECC 9 Register"
|
|
line.long 0x28 "PMECC_ECC10_7,PMECC ECC 10 Register"
|
|
tree.end
|
|
tree "PMECC Remainder Register"
|
|
rgroup.long 0x240++0x2F
|
|
line.long 0x0 "PMECC_REM0_0,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x4 "PMECC_REM1_0,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x8 "PMECC_REM2_0,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0xC "PMECC_REM3_0,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x10 "PMECC_REM4_0,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x14 "PMECC_REM5_0,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x18 "PMECC_REM6_0,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x1C "PMECC_REM7_0,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x20 "PMECC_REM8_0,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x24 "PMECC_REM9_0,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x28 "PMECC_REM10_0,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
line.long 0x2C "PMECC_REM11_0,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+1"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+3"
|
|
rgroup.long 0x280++0x2F
|
|
line.long 0x0 "PMECC_REM0_1,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_1,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_1,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_1,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_1,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_1,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_1,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_1,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_1,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_1,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_1,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_1,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x2C0++0x2F
|
|
line.long 0x0 "PMECC_REM0_2,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_2,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_2,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_2,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_2,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_2,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_2,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_2,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_2,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_2,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_2,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_2,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x300++0x2F
|
|
line.long 0x0 "PMECC_REM0_3,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_3,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_3,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_3,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_3,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_3,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_3,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_3,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_3,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_3,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_3,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_3,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x340++0x2F
|
|
line.long 0x0 "PMECC_REM0_4,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_4,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_4,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_4,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_4,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_4,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_4,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_4,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_4,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_4,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_4,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_4,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x380++0x2F
|
|
line.long 0x0 "PMECC_REM0_5,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_5,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_5,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_5,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_5,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_5,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_5,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_5,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_5,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_5,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_5,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_5,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x3C0++0x2F
|
|
line.long 0x0 "PMECC_REM0_6,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_6,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_6,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_6,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_6,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_6,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_6,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_6,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_6,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_6,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_6,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_6,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
rgroup.long 0x400++0x2F
|
|
line.long 0x0 "PMECC_REM0_7,PMECC Remainder 0 Register"
|
|
hexmask.long.word 0x0 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x0 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x4 "PMECC_REM1_7,PMECC Remainder 1 Register"
|
|
hexmask.long.word 0x4 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x4 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x8 "PMECC_REM2_7,PMECC Remainder 2 Register"
|
|
hexmask.long.word 0x8 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x8 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0xC "PMECC_REM3_7,PMECC Remainder 3 Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0xC 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x10 "PMECC_REM4_7,PMECC Remainder 4 Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x10 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x14 "PMECC_REM5_7,PMECC Remainder 5 Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x14 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x18 "PMECC_REM6_7,PMECC Remainder 6 Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x18 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x1C "PMECC_REM7_7,PMECC Remainder 7 Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x1C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x20 "PMECC_REM8_7,PMECC Remainder 8 Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x20 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x24 "PMECC_REM9_7,PMECC Remainder 9 Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x24 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x28 "PMECC_REM10_7,PMECC Remainder 10 Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x28 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
line.long 0x2C "PMECC_REM11_7,PMECC Remainder 11 Register"
|
|
hexmask.long.word 0x2C 16.--29. 1. " REM2NP3 ,BCH Remainder 2*N+3"
|
|
hexmask.long.word 0x2C 0.--13. 1. " REM2NP1 ,BCH Remainder 2*N+1"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "PMERRLOC (Programmable Multibit ECC Error Location User Interface)"
|
|
base ad:0xFFFFE600
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMERRLOC_ELCFG,Error Location Configuration Register"
|
|
hexmask.long.byte 0x00 16.--20. 1. " ERRNUM ,Number of Errors"
|
|
bitfld.long 0x00 0. " SECTORSZ ,Sector Size" "512-bytes,1024-bytes"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PMERRLOC_ELPRIM,Error Location Primitive Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PRIMITIV ,Primitive Polynomial"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PMERRLOC_ELEN,Error Location Enable Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ENINIT ,Initial Number of Bits in the Codeword"
|
|
line.long 0x04 "PMERRLOC_ELDIS,Error Location Disable Register"
|
|
bitfld.long 0x04 0. " DIS ,Disable Error Location Engine" "No,Yes"
|
|
line.long 0x08 "PMERRLOC_ELSR,Error Location Status Register"
|
|
bitfld.long 0x08 0. " BUSY ,Error Location Engine Busy" "Idle,Busy"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PMERRLOC_ELIMR,Error Location Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DONE_set/clr ,Computation Terminated Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PMERRLOC_ELISR,Error Location Interrupt Status Register"
|
|
hexmask.long.byte 0x00 8.--12. 1. " ERR_CNT ,Error Counter value"
|
|
bitfld.long 0x00 0. " DONE ,Computation Terminated Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0x28++0x63
|
|
line.long 0x0 "PMERRLOC_SIGMA0,Error Location SIGMA0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. " SIGMA0 ,Coefficient of degree 0 in the SIGMA Polynomial"
|
|
line.long 0x4 "PMERRLOC_SIGMA1,Error Location SIGMA1 Register"
|
|
hexmask.long.word 0x4 0.--13. 1. " SIGMA1 ,Coefficient of degree 1 in the SIGMA Polynomial"
|
|
line.long 0x8 "PMERRLOC_SIGMA2,Error Location SIGMA2 Register"
|
|
hexmask.long.word 0x8 0.--13. 1. " SIGMA2 ,Coefficient of degree 2 in the SIGMA Polynomial"
|
|
line.long 0xC "PMERRLOC_SIGMA3,Error Location SIGMA3 Register"
|
|
hexmask.long.word 0xC 0.--13. 1. " SIGMA3 ,Coefficient of degree 3 in the SIGMA Polynomial"
|
|
line.long 0x10 "PMERRLOC_SIGMA4,Error Location SIGMA4 Register"
|
|
hexmask.long.word 0x10 0.--13. 1. " SIGMA4 ,Coefficient of degree 4 in the SIGMA Polynomial"
|
|
line.long 0x14 "PMERRLOC_SIGMA5,Error Location SIGMA5 Register"
|
|
hexmask.long.word 0x14 0.--13. 1. " SIGMA5 ,Coefficient of degree 5 in the SIGMA Polynomial"
|
|
line.long 0x18 "PMERRLOC_SIGMA6,Error Location SIGMA6 Register"
|
|
hexmask.long.word 0x18 0.--13. 1. " SIGMA6 ,Coefficient of degree 6 in the SIGMA Polynomial"
|
|
line.long 0x1C "PMERRLOC_SIGMA7,Error Location SIGMA7 Register"
|
|
hexmask.long.word 0x1C 0.--13. 1. " SIGMA7 ,Coefficient of degree 7 in the SIGMA Polynomial"
|
|
line.long 0x20 "PMERRLOC_SIGMA8,Error Location SIGMA8 Register"
|
|
hexmask.long.word 0x20 0.--13. 1. " SIGMA8 ,Coefficient of degree 8 in the SIGMA Polynomial"
|
|
line.long 0x24 "PMERRLOC_SIGMA9,Error Location SIGMA9 Register"
|
|
hexmask.long.word 0x24 0.--13. 1. " SIGMA9 ,Coefficient of degree 9 in the SIGMA Polynomial"
|
|
line.long 0x28 "PMERRLOC_SIGMA10,Error Location SIGMA10 Register"
|
|
hexmask.long.word 0x28 0.--13. 1. " SIGMA10 ,Coefficient of degree 10 in the SIGMA Polynomial"
|
|
line.long 0x2C "PMERRLOC_SIGMA11,Error Location SIGMA11 Register"
|
|
hexmask.long.word 0x2C 0.--13. 1. " SIGMA11 ,Coefficient of degree 11 in the SIGMA Polynomial"
|
|
line.long 0x30 "PMERRLOC_SIGMA12,Error Location SIGMA12 Register"
|
|
hexmask.long.word 0x30 0.--13. 1. " SIGMA12 ,Coefficient of degree 12 in the SIGMA Polynomial"
|
|
line.long 0x34 "PMERRLOC_SIGMA13,Error Location SIGMA13 Register"
|
|
hexmask.long.word 0x34 0.--13. 1. " SIGMA13 ,Coefficient of degree 13 in the SIGMA Polynomial"
|
|
line.long 0x38 "PMERRLOC_SIGMA14,Error Location SIGMA14 Register"
|
|
hexmask.long.word 0x38 0.--13. 1. " SIGMA14 ,Coefficient of degree 14 in the SIGMA Polynomial"
|
|
line.long 0x3C "PMERRLOC_SIGMA15,Error Location SIGMA15 Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. " SIGMA15 ,Coefficient of degree 15 in the SIGMA Polynomial"
|
|
line.long 0x40 "PMERRLOC_SIGMA16,Error Location SIGMA16 Register"
|
|
hexmask.long.word 0x40 0.--13. 1. " SIGMA16 ,Coefficient of degree 16 in the SIGMA Polynomial"
|
|
line.long 0x44 "PMERRLOC_SIGMA17,Error Location SIGMA17 Register"
|
|
hexmask.long.word 0x44 0.--13. 1. " SIGMA17 ,Coefficient of degree 17 in the SIGMA Polynomial"
|
|
line.long 0x48 "PMERRLOC_SIGMA18,Error Location SIGMA18 Register"
|
|
hexmask.long.word 0x48 0.--13. 1. " SIGMA18 ,Coefficient of degree 18 in the SIGMA Polynomial"
|
|
line.long 0x4C "PMERRLOC_SIGMA19,Error Location SIGMA19 Register"
|
|
hexmask.long.word 0x4C 0.--13. 1. " SIGMA19 ,Coefficient of degree 19 in the SIGMA Polynomial"
|
|
line.long 0x50 "PMERRLOC_SIGMA20,Error Location SIGMA20 Register"
|
|
hexmask.long.word 0x50 0.--13. 1. " SIGMA20 ,Coefficient of degree 20 in the SIGMA Polynomial"
|
|
line.long 0x54 "PMERRLOC_SIGMA21,Error Location SIGMA21 Register"
|
|
hexmask.long.word 0x54 0.--13. 1. " SIGMA21 ,Coefficient of degree 21 in the SIGMA Polynomial"
|
|
line.long 0x58 "PMERRLOC_SIGMA22,Error Location SIGMA22 Register"
|
|
hexmask.long.word 0x58 0.--13. 1. " SIGMA22 ,Coefficient of degree 22 in the SIGMA Polynomial"
|
|
line.long 0x5C "PMERRLOC_SIGMA23,Error Location SIGMA23 Register"
|
|
hexmask.long.word 0x5C 0.--13. 1. " SIGMA23 ,Coefficient of degree 23 in the SIGMA Polynomial"
|
|
line.long 0x60 "PMERRLOC_SIGMA24,Error Location SIGMA24 Register"
|
|
hexmask.long.word 0x60 0.--13. 1. " SIGMA24 ,Coefficient of degree 24 in the SIGMA Polynomial"
|
|
rgroup.long 0x8C++0x5F
|
|
line.long 0x0 "PMERRLOC_EL0,PMECC Error Location 0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. " ERRLOC0 ,Error Position within the set"
|
|
line.long 0x4 "PMERRLOC_EL1,PMECC Error Location 1 Register"
|
|
hexmask.long.word 0x4 0.--13. 1. " ERRLOC1 ,Error Position within the set"
|
|
line.long 0x8 "PMERRLOC_EL2,PMECC Error Location 2 Register"
|
|
hexmask.long.word 0x8 0.--13. 1. " ERRLOC2 ,Error Position within the set"
|
|
line.long 0xC "PMERRLOC_EL3,PMECC Error Location 3 Register"
|
|
hexmask.long.word 0xC 0.--13. 1. " ERRLOC3 ,Error Position within the set"
|
|
line.long 0x10 "PMERRLOC_EL4,PMECC Error Location 4 Register"
|
|
hexmask.long.word 0x10 0.--13. 1. " ERRLOC4 ,Error Position within the set"
|
|
line.long 0x14 "PMERRLOC_EL5,PMECC Error Location 5 Register"
|
|
hexmask.long.word 0x14 0.--13. 1. " ERRLOC5 ,Error Position within the set"
|
|
line.long 0x18 "PMERRLOC_EL6,PMECC Error Location 6 Register"
|
|
hexmask.long.word 0x18 0.--13. 1. " ERRLOC6 ,Error Position within the set"
|
|
line.long 0x1C "PMERRLOC_EL7,PMECC Error Location 7 Register"
|
|
hexmask.long.word 0x1C 0.--13. 1. " ERRLOC7 ,Error Position within the set"
|
|
line.long 0x20 "PMERRLOC_EL8,PMECC Error Location 8 Register"
|
|
hexmask.long.word 0x20 0.--13. 1. " ERRLOC8 ,Error Position within the set"
|
|
line.long 0x24 "PMERRLOC_EL9,PMECC Error Location 9 Register"
|
|
hexmask.long.word 0x24 0.--13. 1. " ERRLOC9 ,Error Position within the set"
|
|
line.long 0x28 "PMERRLOC_EL10,PMECC Error Location 10 Register"
|
|
hexmask.long.word 0x28 0.--13. 1. " ERRLOC10 ,Error Position within the set"
|
|
line.long 0x2C "PMERRLOC_EL11,PMECC Error Location 11 Register"
|
|
hexmask.long.word 0x2C 0.--13. 1. " ERRLOC11 ,Error Position within the set"
|
|
line.long 0x30 "PMERRLOC_EL12,PMECC Error Location 12 Register"
|
|
hexmask.long.word 0x30 0.--13. 1. " ERRLOC12 ,Error Position within the set"
|
|
line.long 0x34 "PMERRLOC_EL13,PMECC Error Location 13 Register"
|
|
hexmask.long.word 0x34 0.--13. 1. " ERRLOC13 ,Error Position within the set"
|
|
line.long 0x38 "PMERRLOC_EL14,PMECC Error Location 14 Register"
|
|
hexmask.long.word 0x38 0.--13. 1. " ERRLOC14 ,Error Position within the set"
|
|
line.long 0x3C "PMERRLOC_EL15,PMECC Error Location 15 Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. " ERRLOC15 ,Error Position within the set"
|
|
line.long 0x40 "PMERRLOC_EL16,PMECC Error Location 16 Register"
|
|
hexmask.long.word 0x40 0.--13. 1. " ERRLOC16 ,Error Position within the set"
|
|
line.long 0x44 "PMERRLOC_EL17,PMECC Error Location 17 Register"
|
|
hexmask.long.word 0x44 0.--13. 1. " ERRLOC17 ,Error Position within the set"
|
|
line.long 0x48 "PMERRLOC_EL18,PMECC Error Location 18 Register"
|
|
hexmask.long.word 0x48 0.--13. 1. " ERRLOC18 ,Error Position within the set"
|
|
line.long 0x4C "PMERRLOC_EL19,PMECC Error Location 19 Register"
|
|
hexmask.long.word 0x4C 0.--13. 1. " ERRLOC19 ,Error Position within the set"
|
|
line.long 0x50 "PMERRLOC_EL20,PMECC Error Location 20 Register"
|
|
hexmask.long.word 0x50 0.--13. 1. " ERRLOC20 ,Error Position within the set"
|
|
line.long 0x54 "PMERRLOC_EL21,PMECC Error Location 21 Register"
|
|
hexmask.long.word 0x54 0.--13. 1. " ERRLOC21 ,Error Position within the set"
|
|
line.long 0x58 "PMERRLOC_EL22,PMECC Error Location 22 Register"
|
|
hexmask.long.word 0x58 0.--13. 1. " ERRLOC22 ,Error Position within the set"
|
|
line.long 0x5C "PMERRLOC_EL23,PMECC Error Location 23 Register"
|
|
hexmask.long.word 0x5C 0.--13. 1. " ERRLOC23 ,Error Position within the set"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.open "SMC (Static Memory Controller)"
|
|
sif (cpu()=="AT91SAM9G45")
|
|
base ad:0xffffe800
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
base ad:0xffffe800
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffe800+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffe800+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xffffea00
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffea00+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffea00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffea00+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffea00+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffea00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffea00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xffffec00
|
|
width 0xC
|
|
tree "CS0"
|
|
group.long 0x0++0xB
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x0+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x0+0xC))&0x3000)==0x2000)))
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x0+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x10++0xB
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x10+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x10+0xC))&0x3000)==0x2000)))
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x10+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x20+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x20+0xC))&0x3000)==0x2000)))
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x20+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x30+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x30+0xC))&0x3000)==0x2000)))
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x30+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x40+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x40+0xC))&0x3000)==0x2000)))
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x40+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0x50++0xB
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x50+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x50+0xC))&0x3000)==0x2000)))
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x50+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x60+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x60+0xC))&0x3000)==0x2000)))
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x60+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
if ((((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x1000000)&&((((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif (((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x1000000)
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
elif ((((d.l(ad:0xffffec00+0x70+0xc))&0x1000000)==0x0000000)&&((((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x1000)||(((d.l(ad:0xffffec00+0x70+0xC))&0x3000)==0x2000)))
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0xc)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Delay I/O Registers"
|
|
group.long 0xc0++0x1f
|
|
line.long 0x0 "SMC_DELAY1,SMC Delay on I/O"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "SMC_DELAY2,SMC Delay on I/O"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "SMC_DELAY3,SMC Delay on I/O"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "SMC_DELAY4,SMC Delay on I/O"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SMC_DELAY5,SMC Delay on I/O"
|
|
bitfld.long 0x10 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SMC_DELAY6,SMC Delay on I/O"
|
|
bitfld.long 0x14 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SMC_DELAY7,SMC Delay on I/O"
|
|
bitfld.long 0x18 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "SMC_DELAY8,SMC Delay on I/O"
|
|
bitfld.long 0x1C 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "Write Protect Registers"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree.open "DDRSDRC (DDR/SDR SDRAM Controller)"
|
|
tree "DDRSDRC0"
|
|
base ad:0xffffe600
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DDRSDRC_MR,DDRSDRC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,DDRSDRC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "DDRSDRC_RTR,DDRSDRC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,DDRSDRC Refresh Timer Count"
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DIC/DS ,Output Driver Impedance Control" "Normal,Weak"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,Reserved,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==0x3)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x10)==0x10)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "Reserved,9 bits,10 bits,11 bits"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x3)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 24. " TWTR ,Internal Write to Read Delay" "1,2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDRSDRC_T1PR,Timing 1 Parameter Register"
|
|
bitfld.long 0x00 24.--27. " TXP ,Exit Power-down Delay to First Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXSRD ,Exit Self Refresh Delay to Read Command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXSNR ,Exit Self Refresh Delay to Non-read Command"
|
|
bitfld.long 0x00 0.--4. " TRFC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6&&(d.l(ad:0xffffe600+0x08)&0x100000)==0x100000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==0x6&&(d.l(ad:0xffffe600+0x08)&0x100000)==0x0)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==0x6)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " APDE ,Active Power Down Exit Time" "Fast Exit,Slow Exit"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9M11")
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
elif ((d.l(ad:0xffffe600+0x20)&0x7)==(0x1||0x3))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--10. " DS ,Drive Strength" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--9. " TCR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
endif
|
|
if ((d.l(ad:0xffffe600+0x20)&0x7)==(0x0||0x1))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "Reserved,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "32-bit,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DDRSDRC_DLL,DDRSDRC DLL Information Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MDVAL ,DLL Master Delay Value"
|
|
bitfld.long 0x00 2. " MDOVF ,DLL Master Delay Overflow Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDDEC ,DLL Master Delay Decrement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDINC ,DLL Master Delay Increment" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NO_OPTI ,No Optimization" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G15"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G35")
|
|
group.long 0x34++0xf
|
|
line.long 0x0 "DDRSDRC_DELAY1,DELAY I/O Register"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDRSDRC_DELAY2,DELAY I/O Register"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DDRSDRC_DELAY3,DELAY I/O Register"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DDRSDRC_DELAY4,DELAY I/O Register"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DDRSDRC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "DDRSDRC_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "DDRSDRC1"
|
|
base ad:0xffffe400
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DDRSDRC_MR,DDRSDRC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,DDRSDRC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "DDRSDRC_RTR,DDRSDRC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,DDRSDRC Refresh Timer Count"
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DIC/DS ,Output Driver Impedance Control" "Normal,Weak"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,Reserved,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==0x3)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x10)==0x10)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "Reserved,9 bits,10 bits,11 bits"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x3)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 24. " TWTR ,Internal Write to Read Delay" "1,2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDRSDRC_T1PR,Timing 1 Parameter Register"
|
|
bitfld.long 0x00 24.--27. " TXP ,Exit Power-down Delay to First Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXSRD ,Exit Self Refresh Delay to Read Command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXSNR ,Exit Self Refresh Delay to Non-read Command"
|
|
bitfld.long 0x00 0.--4. " TRFC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6&&(d.l(ad:0xffffe400+0x08)&0x100000)==0x100000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==0x6&&(d.l(ad:0xffffe400+0x08)&0x100000)==0x0)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==0x6)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " APDE ,Active Power Down Exit Time" "Fast Exit,Slow Exit"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9M11")
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
elif ((d.l(ad:0xffffe400+0x20)&0x7)==(0x1||0x3))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--10. " DS ,Drive Strength" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--9. " TCR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
endif
|
|
if ((d.l(ad:0xffffe400+0x20)&0x7)==(0x0||0x1))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "Reserved,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "32-bit,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DDRSDRC_DLL,DDRSDRC DLL Information Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MDVAL ,DLL Master Delay Value"
|
|
bitfld.long 0x00 2. " MDOVF ,DLL Master Delay Overflow Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDDEC ,DLL Master Delay Decrement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDINC ,DLL Master Delay Increment" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NO_OPTI ,No Optimization" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G15"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G35")
|
|
group.long 0x34++0xf
|
|
line.long 0x0 "DDRSDRC_DELAY1,DELAY I/O Register"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDRSDRC_DELAY2,DELAY I/O Register"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DDRSDRC_DELAY3,DELAY I/O Register"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DDRSDRC_DELAY4,DELAY I/O Register"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DDRSDRC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "DDRSDRC_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
tree "DDRSDRC (DDR SDR SDRAM Controller)"
|
|
base ad:0xffffe800
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DDRSDRC_MR,DDRSDRC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,DDRSDRC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "DDRSDRC_RTR,DDRSDRC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,DDRSDRC Refresh Timer Count"
|
|
if ((d.l(ad:0xffffe800+0x20)&0x7)==0x6)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DIC/DS ,Output Driver Impedance Control" "Normal,Weak"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,Reserved,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe800+0x20)&0x7)==0x3)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DLL ,Reset DLL" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "9 bits,10 bits,11 bits,12 bits"
|
|
elif ((d.l(ad:0xffffe800+0x20)&0x10)==0x10)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "Reserved,9 bits,10 bits,11 bits"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "DDRSDRC_CR,DDRSDRC Configuration Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,8"
|
|
textline " "
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 22. " DECOD ,Type of Decoding" "Sequential,Interleaved"
|
|
bitfld.long 0x0 20. " NB ,Number of Banks" "4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 18. " ACTBST ,ACTIVE Bank X to Burst Stop Read Access Bank Y" "Not allowed,Allowed"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 16. " EBISHARE ,External Bus Interface is Shared" "Not shared,Shared"
|
|
else
|
|
bitfld.long 0x0 16. " DQMS ,Mask Data is Shared" "Not shared,Shared"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 12.--14. " OCD ,Off-chip Driver" "Exit/maintain setting,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Default"
|
|
bitfld.long 0x0 9. " DIS_DLL ,Disable DLL" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 4.--6. " CAS ,CAS Latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x0 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,14 bits"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
endif
|
|
if ((d.l(ad:0xffffe800+0x20)&0x7)==0x3)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 24. " TWTR ,Internal Write to Read Delay" "1,2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "DDRSDRC_T0PR,Timing 0 Parameter Register"
|
|
bitfld.long 0x00 28.--31. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " REDUCE_WRRD ,Reduce Write to Read Delay" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 24.--26. " TWTR ,Internal Write to Read Delay" "Reserved,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TRRD ,Active bankA to Active bankB" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TWR ,Write Recovery Delay" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DDRSDRC_T1PR,Timing 1 Parameter Register"
|
|
bitfld.long 0x00 24.--27. " TXP ,Exit Power-down Delay to First Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TXSRD ,Exit Self Refresh Delay to Read Command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXSNR ,Exit Self Refresh Delay to Non-read Command"
|
|
bitfld.long 0x00 0.--4. " TRFC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((d.l(ad:0xffffe800+0x20)&0x7)==0x6&&(d.l(ad:0xffffe800+0x08)&0x100000)==0x100000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((d.l(ad:0xffffe800+0x20)&0x7)==0x6&&(d.l(ad:0xffffe800+0x08)&0x100000)==0x0)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 16.--19. " TFAW ,Four Active window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TRPA ,Row Precharge All Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TXARDS ,Exit Active Power Down Delay to Read Command in Mode Slow Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TXARD ,Exit Active Power Down Delay to Read Command in Mode Fast Exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRSDRC_T2PR,Timing 2 Parameter Register"
|
|
bitfld.long 0x00 12.--14. " TRTP ,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((d.l(ad:0xffffe800+0x20)&0x7)==0x6)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " APDE ,Active Power Down Exit Time" "Fast Exit,Slow Exit"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9M11")
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
elif ((d.l(ad:0xffffe800+0x20)&0x7)==(0x1||0x3))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--10. " DS ,Drive Strength" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 8.--9. " TCR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "DDRSDRC_LPR,DDRSDRC Low Power Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
bitfld.long 0x00 20.--21. " UPD_MR ,Update Load Mode Register and Extended Mode Register" "Disabled,Shared,Not shared,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 2. " CLK_FR ,Clock Frozen Command" "Not frozen,Frozen"
|
|
endif
|
|
if ((d.l(ad:0xffffe800+0x20)&0x7)==(0x0||0x1))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "Reserved,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DDRSDRC_MD,DDRSDRC Memory Device Register"
|
|
bitfld.long 0x0 4. " DBW ,Data Bus Width" "32-bit,16-bit"
|
|
bitfld.long 0x0 0.--2. " MD ,Memory Device" "SDR,Low-power SDR,Reserved,Low-power DDR1,Reserved,Reserved,DDR2,?..."
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DDRSDRC_DLL,DDRSDRC DLL Information Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MDVAL ,DLL Master Delay Value"
|
|
bitfld.long 0x00 2. " MDOVF ,DLL Master Delay Overflow Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDDEC ,DLL Master Delay Decrement" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MDINC ,DLL Master Delay Increment" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRSDRC_HS,High Speed Register"
|
|
bitfld.long 0x00 2. " DIS_ANTICIP_READ ,Anticip read access disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NO_OPTI ,No Optimization" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G15"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G35")
|
|
group.long 0x34++0xf
|
|
line.long 0x0 "DDRSDRC_DELAY1,DELAY I/O Register"
|
|
bitfld.long 0x0 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "DDRSDRC_DELAY2,DELAY I/O Register"
|
|
bitfld.long 0x4 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "DDRSDRC_DELAY3,DELAY I/O Register"
|
|
bitfld.long 0x8 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "DDRSDRC_DELAY4,DELAY I/O Register"
|
|
bitfld.long 0xC 28.--31. " DELAY8 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY7 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY6 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY5 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY4 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY3 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY2 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY1 ,Number of elements in the delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DDRSDRC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "DDRSDRC_WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "SDRAMC (SDRAM Controller)"
|
|
base ad:0xffffea00
|
|
width 12.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,All banks precharge,Load mode register,Auto-refresh,Extended load mode register,Deep power-down,?..."
|
|
line.long 0x4 "SDRAMC_TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count"
|
|
line.long 0x8 "SDRAMC_CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x8 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 24.--27. " TRAS ,Active to Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 20.--23. " TRCD ,Row to Column Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 16.--19. " TRP ,Row Precharge Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " TRC ,Row Cycle Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x8 8.--11. " TWR ,Write Recovery Delay" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 7. " DBW ,Data Bus Width" "32,16"
|
|
bitfld.long 0x8 5.--6. " CAS ,CAS Latency" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 4. " NB ,Number of Banks" "2 banks,4 banks"
|
|
bitfld.long 0x8 2.--3. " NR ,Number of Row Bits" "11 bits,12 bits,13 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " NC ,Column Bits Number" "8 bits,9 bits,10 bits,11 bits"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRAMC_LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Immediately,64 cycles,128 cycles,?..."
|
|
bitfld.long 0x00 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCSR ,Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power Configuration" "No low power,Self-refresh,Power-down,Deep power-down"
|
|
group.long 0x1c++0x3
|
|
line.long 0x0 "SDRAMC_IMR,SDRAMC Interrupt Mask Register"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " RES_set/clr ,Refresh Error Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SDRAMC_ISR,SDRAMC Interrupt Status Register"
|
|
bitfld.long 0x00 0. " Res ,Refresh Error Status" "No error,Error"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SDRAMC_MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x0 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power,?..."
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree "DMAC (DMA Controller)"
|
|
tree "DMA 0"
|
|
base ad:0xFFFFEC00
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8. " DICEN ,Descriptor Integrity Check" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
bitfld.long 0x08 15. " DSREQ7 ,Request a destination single transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " SSREQ7 ,Request a source single transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSREQ6 ,Request a destination single transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " SSREQ6 ,Request a source single transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
bitfld.long 0x0C 15. " DCREQ7 ,Request a destination chunk transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " SCREQ7 ,Request a source chunk transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DCREQ6 ,Request a destination chunk transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " SCREQ6 ,Request a source chunk transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
bitfld.long 0x10 15. " DLAST7 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 14. " SLAST7 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DLAST6 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 12. " SLAST6 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " DICERR7_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DICERR6_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " DICERR5_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " DICERR4_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " DICERR3_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " DICERR2_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " DICERR1_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DICERR0_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " ERR7_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " ERR6_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CBTC7_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CBTC6_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " BTC7_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " BTC6_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 31. " DICERR7 ,Channel 7 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 30. " DICERR6 ,Channel 6 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DICERR5 ,Channel 5 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 28. " DICERR4 ,Channel 4 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DICERR3 ,Channel 3 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 26. " DICERR2 ,Channel 2 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DICERR1 ,Channel 1 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 24. " DICERR0 ,Channel 0 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 23. " ERR7 ,Channel 7 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 ,Channel 6 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 ,Channel 5 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 ,Channel 4 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 ,Channel 3 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 ,Channel 2 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 ,Channel 1 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 ,Channel 0 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " ERR7 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CBTC7 ,Channel 7 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 14. " CBTC6 ,Channel 6 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 ,Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BTC7 ,Channel 7 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 6. " BTC6 ,Channel 6 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTC5 ,Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 ,Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
bitfld.long 0x00 31. " KEEP7 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 30. " KEEP6 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
bitfld.long 0x00 31. " STAL7 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 30. " STAL6 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMPT7 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 22. " EMPT6 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " SUSP7_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " SUSP6_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENA7_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x1f
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR0 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR0_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP0,DMAC Channel 0 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP0,DMAC Channel 0 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x1f
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR1 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR1_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP1,DMAC Channel 1 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP1,DMAC Channel 1 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x1f
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR2 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR2_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP2,DMAC Channel 2 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP2,DMAC Channel 2 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x1f
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR3 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR3_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP3,DMAC Channel 3 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP3,DMAC Channel 3 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x1f
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR4 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR4_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP4,DMAC Channel 4 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP4,DMAC Channel 4 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x1f
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR5 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR5_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP5,DMAC Channel 5 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP5,DMAC Channel 5 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x12C++0x1f
|
|
line.long 0x00 "DMAC_SADDR6,DMAC Channel 6 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR6, DMAC Channel 6 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR6,DMAC Channel 6 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR6 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR6_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA6,DMAC Channel 6 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB6,DMAC Channel 6 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[6] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG6,DMAC Channel 6 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 6 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 6 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 6 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP6,DMAC Channel 6 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP6,DMAC Channel 6 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x154++0x1f
|
|
line.long 0x00 "DMAC_SADDR7,DMAC Channel 7 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR7, DMAC Channel 7 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR7,DMAC Channel 7 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR7 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR7_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA7,DMAC Channel 7 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB7,DMAC Channel 7 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[7] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG7,DMAC Channel 7 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 7 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 7 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 7 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP7,DMAC Channel 7 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP7,DMAC Channel 7 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
textline ""
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DMAC_WPMR,DMAC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "DMAC_WPSR,DMAC Write Protect Status Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DMA 1"
|
|
base ad:0xFFFFEE00
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8. " DICEN ,Descriptor Integrity Check" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
bitfld.long 0x08 15. " DSREQ7 ,Request a destination single transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " SSREQ7 ,Request a source single transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSREQ6 ,Request a destination single transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " SSREQ6 ,Request a source single transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
bitfld.long 0x0C 15. " DCREQ7 ,Request a destination chunk transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " SCREQ7 ,Request a source chunk transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DCREQ6 ,Request a destination chunk transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " SCREQ6 ,Request a source chunk transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
bitfld.long 0x10 15. " DLAST7 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 14. " SLAST7 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DLAST6 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 12. " SLAST6 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " DICERR7_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DICERR6_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " DICERR5_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " DICERR4_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " DICERR3_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " DICERR2_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " DICERR1_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DICERR0_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " ERR7_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " ERR6_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CBTC7_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CBTC6_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " BTC7_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " BTC6_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 31. " DICERR7 ,Channel 7 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 30. " DICERR6 ,Channel 6 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DICERR5 ,Channel 5 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 28. " DICERR4 ,Channel 4 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DICERR3 ,Channel 3 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 26. " DICERR2 ,Channel 2 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DICERR1 ,Channel 1 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 24. " DICERR0 ,Channel 0 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 23. " ERR7 ,Channel 7 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 ,Channel 6 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 ,Channel 5 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 ,Channel 4 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 ,Channel 3 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 ,Channel 2 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 ,Channel 1 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 ,Channel 0 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " ERR7 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CBTC7 ,Channel 7 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 14. " CBTC6 ,Channel 6 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 ,Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BTC7 ,Channel 7 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 6. " BTC6 ,Channel 6 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTC5 ,Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 ,Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
bitfld.long 0x00 31. " KEEP7 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 30. " KEEP6 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
bitfld.long 0x00 31. " STAL7 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 30. " STAL6 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMPT7 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 22. " EMPT6 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " SUSP7_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " SUSP6_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENA7_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x1f
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR0 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR0_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP0,DMAC Channel 0 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP0,DMAC Channel 0 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x1f
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR1 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR1_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP1,DMAC Channel 1 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP1,DMAC Channel 1 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x1f
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR2 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR2_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP2,DMAC Channel 2 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP2,DMAC Channel 2 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x1f
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR3 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR3_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP3,DMAC Channel 3 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP3,DMAC Channel 3 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x1f
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR4 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR4_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP4,DMAC Channel 4 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP4,DMAC Channel 4 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x1f
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR5 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR5_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP5,DMAC Channel 5 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP5,DMAC Channel 5 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x12C++0x1f
|
|
line.long 0x00 "DMAC_SADDR6,DMAC Channel 6 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR6, DMAC Channel 6 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR6,DMAC Channel 6 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR6 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR6_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA6,DMAC Channel 6 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB6,DMAC Channel 6 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[6] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG6,DMAC Channel 6 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 6 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 6 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 6 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP6,DMAC Channel 6 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP6,DMAC Channel 6 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x154++0x1f
|
|
line.long 0x00 "DMAC_SADDR7,DMAC Channel 7 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR7, DMAC Channel 7 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR7,DMAC Channel 7 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR7 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR7_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA7,DMAC Channel 7 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB7,DMAC Channel 7 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[7] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG7,DMAC Channel 7 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 7 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 7 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 7 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP7,DMAC Channel 7 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP7,DMAC Channel 7 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
textline ""
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DMAC_WPMR,DMAC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "DMAC_WPSR,DMAC Write Protect Status Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "UHPHS OHCI (USB High Speed Host Port)"
|
|
base ad:0x00600000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00600000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00600000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00600000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00600000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "UHPHS EHCI (USB High Speed Host Port)"
|
|
base ad:0x00700000
|
|
width 12.
|
|
rgroup.word 0x00++0x01 "Host Controller Capability Registers"
|
|
line.word 0x00 "HCIVERSION,Version Of The EHCI Standard Register"
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "CAPLENGTH,Size Of The Entire Capability Register Area"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "HCSPARAMS,Host Controller Structure Parameters Register"
|
|
bitfld.long 0x00 20.--23. " DPN ,Debug Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " P_INDI ,Port Indicator" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRR ,Port Routing Rule" "N_PCC,HCSP-PORTROUTE"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,N_PORTS" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HCCPARAMS,Parameters Relating Host Controller Capabilities Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "Not cached,Reserved,2 microframes,Reserved,Reserved,Reserved,Reserved,Reserved,Entire frame,?..."
|
|
bitfld.long 0x04 2. " ASPC ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PFLF ,Programmable Frame List Flag" "Fixed 1024,Changed 512-256"
|
|
bitfld.long 0x04 0. " 64AC ,64-Bit Addressing Capability" "32-bit,64-bit"
|
|
width 16.
|
|
if (((data.long(ad:0x00700000+0x04))&0x80)==0x80)
|
|
;HCSPARAMS->PRR==1
|
|
rgroup.long 0x0c++0x07
|
|
line.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign Register"
|
|
line.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign Register"
|
|
else
|
|
hgroup.long 0x0c++0x07
|
|
hide.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign"
|
|
hide.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x01B "Host Controller Operational Registers"
|
|
line.long 0x00 "USBCMD,USBCMD Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASPMC ,RO Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024,512,256,?..."
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
line.long 0x04 "USBSTS,Status Information Register"
|
|
bitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " R ,Reclamation" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HCH ,HC Halted" "Run/Stop==1,Run/Stop==0"
|
|
bitfld.long 0x04 5. " IAA ,Interrupt Async Advance" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " HSE ,Host System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLR ,Frame List Rollover" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PCD ,Port Change Detect" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " UEI ,USB Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "USBINTR,On/off Of Hardware Interrupts Register"
|
|
bitfld.long 0x08 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PCDE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " UEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " UIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FRINDEX, Current Frame Number Register"
|
|
hexmask.long.word 0x0C 0.--13. 1. " FI ,Frame Index"
|
|
width 18.
|
|
line.long 0x10 "CTRLDSSEGMENT,CTRLDSSEGMENT Register"
|
|
line.long 0x14 "PERIODICLISTBASE,Periodic Framelist Base Address Register"
|
|
hexmask.long 0x14 12.--31. 0x1000 " BA ,Base Address"
|
|
line.long 0x18 "ASYNCLISTADDR,Queue Heads Pointer"
|
|
hexmask.long 0x18 5.--31. 0x20 " LPL ,Link Pointer Low"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CONFIGFLAG,Ownership Specification Register"
|
|
bitfld.long 0x00 0. " CF ,Config Flag" "Each port to cHC,All ports to eHC"
|
|
if ((((data.long(ad:0x00700000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00700000+0x54))&0x5)==0x1))
|
|
;HCSPARAMS->P_INDICATOR==1 && this->PED==0 && this->CCS==1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((data.long(ad:0x00700000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00700000+0x54))&0x5)!=0x1))
|
|
;HCSPARAMS->P_INDICATOR==1 && this->PED!=0 && this->CCS!=1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((data.long(ad:0x00700000+0x04))&0x80000)==0x00)&&(((data.long(ad:0x00700000+0x54))&0x5)==0x1))
|
|
;HCSPARAMS->P_INDICATOR==0 && this->PED==0 && this->CCS==1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
else
|
|
;HCSPARAMS->P_INDICATOR==0 && this->PED!=0 && this->CCS!=1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UDPHS (USB High Speed Device Port)"
|
|
base ad:0xF803C000
|
|
width 15.
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|
group.long 0x00++0x03
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|
line.long 0x00 "UDPHS_CTRL,UDPHS Control Register"
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|
bitfld.long 0x00 11. " PULLD_DIS , Pull-Down Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " REWAKEUP , Send Remote Wake Up" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 9. " DETACH , Detach Command" "Attached,Detached"
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|
bitfld.long 0x00 8. " EN_UDPHS , UDPHS Enable" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 7. " FADDR_EN , Function Address Enable" "Disabled,Enabled"
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hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR , UDPHS Address"
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rgroup.long 0x04++0x03
|
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line.long 0x00 "UDPHS_FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x00 31. " FNUM_ERR , Frame Number CRC Error " "No error,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRAME_NUMBER , Frame Number as defined in the Packet Field Formats"
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|
textline " "
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|
bitfld.long 0x00 0.--2. " MICRO_FRAME_NUM , Microframe Number" "0,1,2,3,4,5,6,7"
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group.long 0x10++0x03
|
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line.long 0x00 "UDPHS_IEN,UDPHS Interrupt Enable Register"
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bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt Enable" "Disabled,Enabled"
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textline " "
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|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SOF , SOF Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro-SOF Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
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line.long 0x00 "UDPHS_INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPEED , Speed Status" "Full,High"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "UDPHS_CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "UDPHS_EPTRST,UDPHS Endpoints Reset Register"
|
|
bitfld.long 0x04 6. " EPT_6 , Endpoint 6 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " EPT_5 , Endpoint 5 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EPT_4 , Endpoint 4 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 3. " EPT_3 , Endpoint 3 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EPT_2 , Endpoint 2 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 1. " EPT_1 , Endpoint 1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EPT_0 , Endpoint 0 Reset" "No effect,Reset"
|
|
group.long 0xe0++0x03
|
|
line.long 0x00 "UDPHS_TST,UDPHS Test Register"
|
|
bitfld.long 0x00 5. " OPMODE2 , OpMode2" "No effect,OpMode"
|
|
bitfld.long 0x00 4. " TST_PKT , Test Packet Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TST_K , Test K Mode" "No effect,Test"
|
|
bitfld.long 0x00 2. " TST_J , Test J Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SPEED_CFG , Speed Configuration" "Normal Mode,Reserved,High Speed,Full Speed"
|
|
width 18.
|
|
rgroup.long 0xf0++0xb
|
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line.long 0x00 "UDPHS_IPNAME1,UDPHS Name1 Register"
|
|
line.long 0x04 "UDPHS_IPNAME2,UDPHS Name2 Register"
|
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line.long 0x08 "UDPHS_IPFEATURES,UDPHS Features Register"
|
|
bitfld.long 0x08 31. " ISO_EPT_15 ,Endpoint15 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 30. " ISO_EPT_14 ,Endpoint14 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ISO_EPT_13 ,Endpoint13 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 28. " ISO_EPT_12 ,Endpoint12 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ISO_EPT_11 ,Endpoint11 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 26. " ISO_EPT_10 ,Endpoint10 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ISO_EPT_9 ,Endpoint9 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 24. " ISO_EPT_8 ,Endpoint8 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ISO_EPT_7 ,Endpoint7 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
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bitfld.long 0x08 22. " ISO_EPT_6 ,Endpoint6 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ISO_EPT_5 ,Endpoint5 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 20. " ISO_EPT_4 ,Endpoint4 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
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bitfld.long 0x08 19. " ISO_EPT_3 ,Endpoint3 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
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bitfld.long 0x08 18. " ISO_EPT_2 ,Endpoint2 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
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bitfld.long 0x08 17. " ISO_EPT_1 ,Endpoint1 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 16. " DATAB16_8 ,UTMI DataBus16_8" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 15. " BW_DPRAM ,DPRAM Byte Write Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 12.--14. " FIFO_MAX_SIZE ,DPRAM Size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DMA_FIFO_DEPTH ,DMA FIFO Depth in Words" "16 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words"
|
|
bitfld.long 0x08 7. " DMA_B_SIZ ,DMA Buffer Size" "16 bits,24 bits"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " DMA_CHANNEL_NBR ,Number of DMA Channels" "Reserved,1,2,3,4,5,6,7"
|
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bitfld.long 0x08 0.--3. " EPT_NBR_MAX ,Max Number of Endpoints" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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width 19.
|
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tree "Endpoint 0"
|
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if ((((d.l(ad:0xF803C000+0x100))&0x30)==0x0))
|
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group.long 0x100++0x03
|
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line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
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bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x100))&0x30)==0x10))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x100))&0x30)==0x20)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x100))&0x30)==0x10)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA0,UDPHS Endpoint Set Status Register 0"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA0,UDPHS Endpoint Clear Status Register 0"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x100))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x100))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x100))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x100))&0x8)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x100))&0x30)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x100))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x100))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
if ((((d.l(ad:0xF803C000+0x120))&0x30)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x120))&0x30)==0x10))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x120))&0x30)==0x20)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x120))&0x30)==0x10)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x134++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA1,UDPHS Endpoint Set Status Register 1"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA1,UDPHS Endpoint Clear Status Register 1"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x120))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x120))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x120))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x120))&0x8)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x120))&0x30)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x120))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x120))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
if ((((d.l(ad:0xF803C000+0x140))&0x30)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x140))&0x30)==0x10))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x140))&0x30)==0x20)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x140))&0x30)==0x10)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x154++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA2,UDPHS Endpoint Set Status Register 2"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA2,UDPHS Endpoint Clear Status Register 2"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x140))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x140))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x140))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x140))&0x8)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x140))&0x30)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x140))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x140))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
if ((((d.l(ad:0xF803C000+0x160))&0x30)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x160))&0x30)==0x10))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x160))&0x30)==0x20)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x160))&0x30)==0x10)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x174++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA3,UDPHS Endpoint Set Status Register 3"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA3,UDPHS Endpoint Clear Status Register 3"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x160))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x160))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x160))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x160))&0x8)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x160))&0x30)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x160))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x160))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
if ((((d.l(ad:0xF803C000+0x180))&0x30)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x180))&0x30)==0x10))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x180))&0x30)==0x20)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x180))&0x30)==0x10)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x194++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA4,UDPHS Endpoint Set Status Register 4"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA4,UDPHS Endpoint Clear Status Register 4"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x180))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x180))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x180))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x180))&0x8)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x180))&0x30)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x180))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x180))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
if ((((d.l(ad:0xF803C000+0x1A0))&0x30)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x1A0))&0x30)==0x10))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x1A0))&0x30)==0x20)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x1A0))&0x30)==0x10)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1B4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA5,UDPHS Endpoint Set Status Register 5"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA5,UDPHS Endpoint Clear Status Register 5"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x1A0))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x1A0))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1A0))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x1A0))&0x8)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1A0))&0x30)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1A0))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x1A0))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
if ((((d.l(ad:0xF803C000+0x1C0))&0x30)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xF803C000+0x1C0))&0x30)==0x10))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xF803C000+0x1C0))&0x30)==0x20)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xF803C000+0x1C0))&0x30)==0x10)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1D4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA6,UDPHS Endpoint Set Status Register 6"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA6,UDPHS Endpoint Clear Status Register 6"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xF803C000+0x1C0))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x1C0))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1C0))&0x30)==0x10)&&(((d.l(ad:0xF803C000+0x1C0))&0x8)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1C0))&0x30)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xF803C000+0x1C0))&0x30)==(0x20||0x30))&&(((d.l(ad:0xF803C000+0x1C0))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "DMA channel 1"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC1,UDPHS DMA Next Descriptor Address Register 1"
|
|
line.long 0x04 "UDPHS_DMAADDRESS1,UDPHS DMA Channel Address Register 1"
|
|
if ((d.l(ad:0xF803C000+0x100)&0x8)==0x0)
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x320+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS1,UDPHS DMA Channel Status Register 1"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC2,UDPHS DMA Next Descriptor Address Register 2"
|
|
line.long 0x04 "UDPHS_DMAADDRESS2,UDPHS DMA Channel Address Register 2"
|
|
if ((d.l(ad:0xF803C000+0x120)&0x8)==0x0)
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x330+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS2,UDPHS DMA Channel Status Register 2"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC3,UDPHS DMA Next Descriptor Address Register 3"
|
|
line.long 0x04 "UDPHS_DMAADDRESS3,UDPHS DMA Channel Address Register 3"
|
|
if ((d.l(ad:0xF803C000+0x140)&0x8)==0x0)
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x340+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS3,UDPHS DMA Channel Status Register 3"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC4,UDPHS DMA Next Descriptor Address Register 4"
|
|
line.long 0x04 "UDPHS_DMAADDRESS4,UDPHS DMA Channel Address Register 4"
|
|
if ((d.l(ad:0xF803C000+0x160)&0x8)==0x0)
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x350+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS4,UDPHS DMA Channel Status Register 4"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC5,UDPHS DMA Next Descriptor Address Register 5"
|
|
line.long 0x04 "UDPHS_DMAADDRESS5,UDPHS DMA Channel Address Register 5"
|
|
if ((d.l(ad:0xF803C000+0x180)&0x8)==0x0)
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x360+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS5,UDPHS DMA Channel Status Register 5"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 6"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC6,UDPHS DMA Next Descriptor Address Register 6"
|
|
line.long 0x04 "UDPHS_DMAADDRESS6,UDPHS DMA Channel Address Register 6"
|
|
if ((d.l(ad:0xF803C000+0x1A0)&0x8)==0x0)
|
|
group.long (0x370+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL6, UDPHS DMA Channel Control Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x370+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL6, UDPHS DMA Channel Control Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x370+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS6,UDPHS DMA Channel Status Register 6"
|
|
in
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "HSMCI (High Speed MultiMedia Card Interface)"
|
|
tree "HSMCI 0"
|
|
base ad:0xF0008000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (0xF0008000+0x200)--(0xF0008000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "HSMCI 1"
|
|
base ad:0xF000C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (0xF000C000+0x200)--(0xF000C000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45")
|
|
; no base address for this peripheral
|
|
; tree "ECC (Error Corrected Code)"
|
|
; base ad:0x
|
|
; %include at91cap9/ecc.ph
|
|
; tree.end
|
|
elif (cpu()=="AT91SAM9G46")
|
|
tree "ECC (Error Corrected Code)"
|
|
base ad:0xffffe200
|
|
width 0x9
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 1. " SRST ,Soft Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 4.--5. " TYPECORRECT , Type of Correction" "1 bit for a page,1 bit for 256 bytes,1 bit for 512 bytes,?..."
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "ECC_SR1,ECC Status Register 1"
|
|
bitfld.long 0x00 30. " MULERR7 ,Multiple Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR7 ,ECC Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 28. " RECERR7 ,Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MULERR6 ,Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 25. " ECCERR6 ,ECC Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR6 ,Recoverable Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MULERR5 ,Multiple Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR5 ,ECC Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 20. " RECERR5 ,Recoverable Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MULERR4 ,Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 17. " ECCERR4 ,ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR4 ,Recoverable Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR3 ,Multiple Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR3 ,ECC Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
bitfld.long 0x00 12. " RECERR3 ,Recoverable Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MULERR2 ,Multiple Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
bitfld.long 0x00 9. " ECCERR2 ,ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR2 ,Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR1 ,Multiple Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR1 ,ECC Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes" "No error,Error"
|
|
bitfld.long 0x00 4. " RECERR1 ,Recoverable Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MULERR0 ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR0 ,ECC Error" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR0 ,Recoverable Error" "No error,Error"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "ECC_SR2,ECC Status Register 2"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ECC_SR2,ECC Status Register 2"
|
|
endif
|
|
bitfld.long 0x00 30. " MULERR15 ,Multiple Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR15 ,ECC Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
bitfld.long 0x00 28. " RECERR15 ,Recoverable Error in the page between the 3840th and the 4095th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MULERR14 ,Multiple Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
bitfld.long 0x00 25. " ECCERR14 ,ECC Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR14 ,Recoverable Error in the page between the 3584th and the 3839th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MULERR13 ,Multiple Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR13 ,ECC Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
bitfld.long 0x00 20. " RECERR13 ,Recoverable Error in the page between the 3328th and the 3583rd bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MULERR12 ,Multiple Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
bitfld.long 0x00 17. " ECCERR12 ,ECC Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR12 ,Recoverable Error in the page between the 3072nd and the 3327th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR11 ,Multiple Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR11 ,ECC Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
bitfld.long 0x00 12. " RECERR11 ,Recoverable Error in the page between the 2816th and the 3071st bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MULERR10 ,Multiple Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
bitfld.long 0x00 9. " ECCERR10 ,ECC Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR10 ,Recoverable Error in the page between the 2560th and the 2815th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR9 ,Multiple Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR9 ,ECC Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
bitfld.long 0x00 4. " RECERR9 ,Recoverable Error in the page between the 2304th and the 2559th bytes" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MULERR8 ,Multiple Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR8 ,ECC Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR8 ,Recoverable Error in the page between the 2048th and the 2303rd bytes" "No error,Error"
|
|
if (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x10)
|
|
rgroup.long 0x0c++0x7 "Registers for 1 ECC per 256 bytes for a page"
|
|
line.long 0x0 "ECC_PR0 ,ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--22. 1. " NPARITY0 ,Parity 0 "
|
|
hexmask.long.byte 0x0 3.--10. 8. " WORDADDR0 ,Corrupted Word Address in the page between the 0 byte and the 255th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR0 ,Corrupted Bit Address in the page between the 0 byte and the 255th bytes"
|
|
line.long 0x4 "ECC_PR1 ,ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--22. 1. " NPARITY1 ,Parity 1 "
|
|
hexmask.long.byte 0x4 3.--10. 8. " WORDADDR1 ,Corrupted Word Address in the page between the 256 byte and the 511th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR1 ,Corrupted Bit Address in the page between the 256 byte and the 511th bytes"
|
|
rgroup.long 0x18++0x37
|
|
line.long 0x0 "ECC_PR2 ,ECC Parity Register 2 "
|
|
hexmask.long.word 0x0 12.--22. 1. " NPARITY2 ,Parity 2 "
|
|
hexmask.long.byte 0x0 3.--10. 8. " WORDADDR2 ,Corrupted Word Address in the page between the 512 byte and the 767th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR2 ,Corrupted Bit Address in the page between the 512 byte and the 767th bytes"
|
|
line.long 0x4 "ECC_PR3 ,ECC Parity Register 3 "
|
|
hexmask.long.word 0x4 12.--22. 1. " NPARITY3 ,Parity 3 "
|
|
hexmask.long.byte 0x4 3.--10. 8. " WORDADDR3 ,Corrupted Word Address in the page between the 768 byte and the 1023th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR3 ,Corrupted Bit Address in the page between the 768 byte and the 1023th bytes"
|
|
line.long 0x8 "ECC_PR4 ,ECC Parity Register 4 "
|
|
hexmask.long.word 0x8 12.--22. 1. " NPARITY4 ,Parity 4 "
|
|
hexmask.long.byte 0x8 3.--10. 8. " WORDADDR4 ,Corrupted Word Address in the page between the 1024 byte and the 1279th bytes"
|
|
hexmask.long.byte 0x8 0.--2. 1. " BITADDR4 ,Corrupted Bit Address in the page between the 1024 byte and the 1279th bytes"
|
|
line.long 0xC "ECC_PR5 ,ECC Parity Register 5 "
|
|
hexmask.long.word 0xC 12.--22. 1. " NPARITY5 ,Parity 5 "
|
|
hexmask.long.byte 0xC 3.--10. 8. " WORDADDR5 ,Corrupted Word Address in the page between the 1280 byte and the 1535th bytes"
|
|
hexmask.long.byte 0xC 0.--2. 1. " BITADDR5 ,Corrupted Bit Address in the page between the 1280 byte and the 1535th bytes"
|
|
line.long 0x10 "ECC_PR6 ,ECC Parity Register 6 "
|
|
hexmask.long.word 0x10 12.--22. 1. " NPARITY6 ,Parity 6 "
|
|
hexmask.long.byte 0x10 3.--10. 8. " WORDADDR6 ,Corrupted Word Address in the page between the 1536 byte and the 1791th bytes"
|
|
hexmask.long.byte 0x10 0.--2. 1. " BITADDR6 ,Corrupted Bit Address in the page between the 1536 byte and the 1791th bytes"
|
|
line.long 0x14 "ECC_PR7 ,ECC Parity Register 7 "
|
|
hexmask.long.word 0x14 12.--22. 1. " NPARITY7 ,Parity 7 "
|
|
hexmask.long.byte 0x14 3.--10. 8. " WORDADDR7 ,Corrupted Word Address in the page between the 1792 byte and the 2047th bytes"
|
|
hexmask.long.byte 0x14 0.--2. 1. " BITADDR7 ,Corrupted Bit Address in the page between the 1792 byte and the 2047th bytes"
|
|
line.long 0x18 "ECC_PR8 ,ECC Parity Register 8 "
|
|
hexmask.long.word 0x18 12.--22. 1. " NPARITY8 ,Parity 8 "
|
|
hexmask.long.byte 0x18 3.--10. 8. " WORDADDR8 ,Corrupted Word Address in the page between the 2048 byte and the 2303th bytes"
|
|
hexmask.long.byte 0x18 0.--2. 1. " BITADDR8 ,Corrupted Bit Address in the page between the 2048 byte and the 2303th bytes"
|
|
line.long 0x1C "ECC_PR9 ,ECC Parity Register 9 "
|
|
hexmask.long.word 0x1C 12.--22. 1. " NPARITY9 ,Parity 9 "
|
|
hexmask.long.byte 0x1C 3.--10. 8. " WORDADDR9 ,Corrupted Word Address in the page between the 2304 byte and the 2559th bytes"
|
|
hexmask.long.byte 0x1C 0.--2. 1. " BITADDR9 ,Corrupted Bit Address in the page between the 2304 byte and the 2559th bytes"
|
|
line.long 0x20 "ECC_PR10,ECC Parity Register 10"
|
|
hexmask.long.word 0x20 12.--22. 1. " NPARITY10 ,Parity 10"
|
|
hexmask.long.byte 0x20 3.--10. 8. " WORDADDR10 ,Corrupted Word Address in the page between the 2560 byte and the 2815th bytes"
|
|
hexmask.long.byte 0x20 0.--2. 1. " BITADDR10 ,Corrupted Bit Address in the page between the 2560 byte and the 2815th bytes"
|
|
line.long 0x24 "ECC_PR11,ECC Parity Register 11"
|
|
hexmask.long.word 0x24 12.--22. 1. " NPARITY11 ,Parity 11"
|
|
hexmask.long.byte 0x24 3.--10. 8. " WORDADDR11 ,Corrupted Word Address in the page between the 2816 byte and the 3071th bytes"
|
|
hexmask.long.byte 0x24 0.--2. 1. " BITADDR11 ,Corrupted Bit Address in the page between the 2816 byte and the 3071th bytes"
|
|
line.long 0x28 "ECC_PR12,ECC Parity Register 12"
|
|
hexmask.long.word 0x28 12.--22. 1. " NPARITY12 ,Parity 12"
|
|
hexmask.long.byte 0x28 3.--10. 8. " WORDADDR12 ,Corrupted Word Address in the page between the 3072 byte and the 3327th bytes"
|
|
hexmask.long.byte 0x28 0.--2. 1. " BITADDR12 ,Corrupted Bit Address in the page between the 3072 byte and the 3327th bytes"
|
|
line.long 0x2C "ECC_PR13,ECC Parity Register 13"
|
|
hexmask.long.word 0x2C 12.--22. 1. " NPARITY13 ,Parity 13"
|
|
hexmask.long.byte 0x2C 3.--10. 8. " WORDADDR13 ,Corrupted Word Address in the page between the 3328 byte and the 3583th bytes"
|
|
hexmask.long.byte 0x2C 0.--2. 1. " BITADDR13 ,Corrupted Bit Address in the page between the 3328 byte and the 3583th bytes"
|
|
line.long 0x30 "ECC_PR14,ECC Parity Register 14"
|
|
hexmask.long.word 0x30 12.--22. 1. " NPARITY14 ,Parity 14"
|
|
hexmask.long.byte 0x30 3.--10. 8. " WORDADDR14 ,Corrupted Word Address in the page between the 3584 byte and the 3839th bytes"
|
|
hexmask.long.byte 0x30 0.--2. 1. " BITADDR14 ,Corrupted Bit Address in the page between the 3584 byte and the 3839th bytes"
|
|
line.long 0x34 "ECC_PR15,ECC Parity Register 15"
|
|
hexmask.long.word 0x34 12.--22. 1. " NPARITY15 ,Parity 15"
|
|
hexmask.long.byte 0x34 3.--10. 8. " WORDADDR15 ,Corrupted Word Address in the page between the 3840 byte and the 4095th bytes"
|
|
hexmask.long.byte 0x34 0.--2. 1. " BITADDR15 ,Corrupted Bit Address in the page between the 3840 byte and the 4095th bytes"
|
|
elif (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x20)
|
|
rgroup.long 0x0c++0x7 "Registers for 1 ECC per 512 bytes for a page"
|
|
line.long 0x0 "ECC_PR0 ,ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--23. 1. " NPARITY0 ,Parity 0 "
|
|
hexmask.long.word 0x0 3.--11. 8. " WORDADDR0 ,Corrupted Word Address in the page between the 0 byte and the 511th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR0 ,Corrupted Bit Address in the page between the 0 byte and the 511th bytes"
|
|
line.long 0x4 "ECC_PR1 ,ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--23. 1. " NPARITY1 ,Parity 1 "
|
|
hexmask.long.word 0x4 3.--11. 8. " WORDADDR1 ,Corrupted Word Address in the page between the 512 byte and the 1023th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR1 ,Corrupted Bit Address in the page between the 512 byte and the 1023th bytes"
|
|
rgroup.long 0x18++0x17
|
|
line.long 0x0 "ECC_PR2 ,ECC Parity Register 2 "
|
|
hexmask.long.word 0x0 12.--23. 1. " NPARITY2 ,Parity 2 "
|
|
hexmask.long.word 0x0 3.--11. 8. " WORDADDR2 ,Corrupted Word Address in the page between the 1024 byte and the 1535th bytes"
|
|
hexmask.long.byte 0x0 0.--2. 1. " BITADDR2 ,Corrupted Bit Address in the page between the 1024 byte and the 1535th bytes"
|
|
line.long 0x4 "ECC_PR3 ,ECC Parity Register 3 "
|
|
hexmask.long.word 0x4 12.--23. 1. " NPARITY3 ,Parity 3 "
|
|
hexmask.long.word 0x4 3.--11. 8. " WORDADDR3 ,Corrupted Word Address in the page between the 1536 byte and the 2047th bytes"
|
|
hexmask.long.byte 0x4 0.--2. 1. " BITADDR3 ,Corrupted Bit Address in the page between the 1536 byte and the 2047th bytes"
|
|
line.long 0x8 "ECC_PR4 ,ECC Parity Register 4 "
|
|
hexmask.long.word 0x8 12.--23. 1. " NPARITY4 ,Parity 4 "
|
|
hexmask.long.word 0x8 3.--11. 8. " WORDADDR4 ,Corrupted Word Address in the page between the 2048 byte and the 2559th bytes"
|
|
hexmask.long.byte 0x8 0.--2. 1. " BITADDR4 ,Corrupted Bit Address in the page between the 2048 byte and the 2559th bytes"
|
|
line.long 0xC "ECC_PR5 ,ECC Parity Register 5 "
|
|
hexmask.long.word 0xC 12.--23. 1. " NPARITY5 ,Parity 5 "
|
|
hexmask.long.word 0xC 3.--11. 8. " WORDADDR5 ,Corrupted Word Address in the page between the 2560 byte and the 3071th bytes"
|
|
hexmask.long.byte 0xC 0.--2. 1. " BITADDR5 ,Corrupted Bit Address in the page between the 2560 byte and the 3071th bytes"
|
|
line.long 0x10 "ECC_PR6 ,ECC Parity Register 6 "
|
|
hexmask.long.word 0x10 12.--23. 1. " NPARITY6 ,Parity 6 "
|
|
hexmask.long.word 0x10 3.--11. 8. " WORDADDR6 ,Corrupted Word Address in the page between the 3072 byte and the 3583th bytes"
|
|
hexmask.long.byte 0x10 0.--2. 1. " BITADDR6 ,Corrupted Bit Address in the page between the 3072 byte and the 3583th bytes"
|
|
line.long 0x14 "ECC_PR7 ,ECC Parity Register 7 "
|
|
hexmask.long.word 0x14 12.--23. 1. " NPARITY7 ,Parity 7 "
|
|
hexmask.long.word 0x14 3.--11. 8. " WORDADDR7 ,Corrupted Word Address in the page between the 3584 byte and the 4095th bytes"
|
|
hexmask.long.byte 0x14 0.--2. 1. " BITADDR7 ,Corrupted Bit Address in the page between the 3584 byte and the 4095th bytes"
|
|
elif (((d.l(ad:(0xffffe200+0x4)))&0x30)==0x0)
|
|
rgroup.long 0x0C++0x07 "Registers for 1 ECC for a page"
|
|
line.long 0x00 "ECC_PR0,ECC Parity Register 0"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x00 4.--15. 10. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x04 "ECC_PR1,ECC Parity Register 1 "
|
|
hexmask.long.word 0x04 0.--15. 1. " NPARITY ,N PARITY Value"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G20")
|
|
tree "ECC (Error Corrected Code)"
|
|
base ad:0xffffe800
|
|
width 0x9
|
|
wgroup.long 0x00++3
|
|
line.long 0x00 "ECC_CR,ECC Control Register"
|
|
bitfld.long 0x00 0. " RST ,RESET Parity" "No effect,Reset"
|
|
group.long 0x04++3
|
|
line.long 0x00 "ECC_MR,ECC Mode Register"
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page Size" "528 words,1056 words,2112 words,4224 words"
|
|
rgroup.long 0x08++0xb
|
|
line.long 0x00 "ECC_SR,ECC Status Register"
|
|
bitfld.long 0x00 2. " MULERR ,Multiple Error" "No error,Error"
|
|
bitfld.long 0x00 1. " ECCERR ,ECC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RECERR ,Recoverable Error" "No error,Error"
|
|
line.long 0x04 "ECC_PR,ECC Parity Register"
|
|
hexmask.long.byte 0x04 0.--3. 1. " BITADDR ,Corrupted bit offset where an error occurred"
|
|
hexmask.long.word 0x04 4.--15. 1. " WORDADDR ,Word address where an error occurred"
|
|
line.long 0x08 "ECC_NPR,ECC NParity Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " NPARITY ,NPARITY Value"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree "Clock Generator"
|
|
base ad:0xfffffd50
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCKCR,Slow Clock Configuration Register"
|
|
bitfld.long 0x00 3. " OSCSEL ,Slow Clock Selector" "Internal RC,32768Hz oscillator"
|
|
bitfld.long 0x00 2. " OSC32BYP ,32768Hz Oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OSC32EN ,32768Hz Oscillator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCEN ,Internal RC" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xfffffc00
|
|
sif (cpu()=="AT91SAM9G10")
|
|
width 0x12
|
|
sif (cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK ,Processor Clock Disable" "No effect,Disable"
|
|
endif
|
|
group.long 0x08++03
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " HCK1_set/clr ,HClock Output 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " HCK0_set/clr ,HClock Output 0 Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PCK3_set/clr ,Programmable Clock 3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Status" "Disabled,Enabled"
|
|
elif (cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " PCK_set/clr ,Processor Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Disable Register "
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Disable" "No effect,Disabled"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
bitfld.long 0x0 0. " PCK ,Processor Clock Status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PID31_set/clr ,Peripheral Clock 31 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " PID30_set/clr ,Peripheral Clock 30 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " PID29_set/clr ,Peripheral Clock 29 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " PID28_set/clr ,Peripheral Clock 28 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PID27_set/clr ,Peripheral Clock 27 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PID26_set/clr ,Peripheral Clock 26 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " PID25_set/clr ,Peripheral Clock 25 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " PID24_set/clr ,Peripheral Clock 24 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " PID23_set/clr ,Peripheral Clock 23 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " PID22_set/clr ,Peripheral Clock 22 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " PID21_set/clr ,Peripheral Clock 21 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " PID20_set/clr ,Peripheral Clock 20 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PID19_set/clr ,Peripheral Clock 19 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PID18_set/clr ,Peripheral Clock 18 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " PID17_set/clr ,Peripheral Clock 17 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " PID16_set/clr ,Peripheral Clock 16 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PID15_set/clr ,Peripheral Clock 15 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PID14_set/clr ,Peripheral Clock 14 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PID13_set/clr ,Peripheral Clock 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PID12_set/clr ,Peripheral Clock 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PID11_set/clr ,Peripheral Clock 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PID10_set/clr ,Peripheral Clock 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PID9_set/clr ,Peripheral Clock 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PID8_set/clr ,Peripheral Clock 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PID7_set/clr ,Peripheral Clock 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " PID6_set/clr ,Peripheral Clock 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PID5_set/clr ,Peripheral Clock 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PID4_set/clr ,Peripheral Clock 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PID3_set/clr ,Peripheral Clock 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PID2_set/clr ,Peripheral Clock 2 Status" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x00 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0xB
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-200 MHz,Reserved,190-220 MHz,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-300 MHz,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "80-200 MHz,Reserved,190-240 MHz,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
line.long 0x4 "CKGR_PLLBR,PMC Clock Generator PLL B Register"
|
|
bitfld.long 0x4 28.--29. " USBDIV ,Divider for USB Clock" "PLL B,PLL B/2,PLL B/4,?..."
|
|
hexmask.long.word 0x4 16.--26. 1. " MULB ,PLL Multiplier"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "Reserved,70-130 MHz,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "80-300 MHz,?..."
|
|
else
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "80-200 MHz,Reserved,190-240 MHz,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " PLLBCOUNT ,PLL B Counter"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " DIVB ,Divider B"
|
|
line.long 0x8 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x8 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,?..."
|
|
bitfld.long 0x8 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9261"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x00 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
line.long 0x04 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x04 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x04 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
setclrfld.long 0x00 11. -0xc 11. -0x8 11. " PCKRDY3_set/clr ,Programmable Clock Ready 3 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0xc 2. -0x8 2. " LOCKB_set/clr ,PLL B Lock Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Enabled,Disabled"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
sif (cpu()!="AT91SAM9260"&&cpu()!="AT91SAM9XE128"&&cpu()!="AT91SAM9XE256"&&cpu()!="AT91SAM9XE512")
|
|
bitfld.long 0x00 11. " PCKRDY3 ,Programmable Clock Ready 3 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " PCKRDY2 ,Programmable Clock Ready 2 Status" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 7. " OSC_SEL , Slow Clock Oscillator Selection" "Internal,External"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " LOCKB ,PLL B Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
endif
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9G10")
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,Charge Pump Current Register"
|
|
bitfld.long 0x00 16. " ICPPLLB ,Charge pump current" "Reserved,1"
|
|
bitfld.long 0x00 0. " ICPPLLA ,Charge pump current" "Reserved,1"
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45")
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9M11")
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PCK7_set/clr ,Programmable Clock 7 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PCK6_set/clr ,Programmable Clock 6 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PCK5_set/clr ,Programmable Clock 5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PCK4_set/clr ,Programmable Clock 4 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PCK5_set/clr ,Programmable Clock 5 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK4_set/clr ,Programmable Clock 4 Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
sif (cpu()!="AT91SAM9M11")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PCK7_set/clr ,Programmable Clock 7 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMDCK_set/clr ,SMD Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " LCDCK_set/clr ,LCD Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " DDRCK_set/clr ,DDR Clock Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Status" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Disable" "No effect,Disable"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TRNG_set/clr ,True Random Number Generator (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " CAN1_set/clr ,CAN Controller 1 (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " AES_set/clr ,Advanced Encryption Standard (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " CAN0_set/clr ,CAN Controller 0 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " SSC_set/clr ,Synchronous Serial Controller (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " SHA_set/clr ,Secure Hash Algorithm (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35")
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " HSMCI1_set/clr ,High Speed Multimedia Card Interface 1(Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " EMAC1_set/clr ,Ethernet MAC1 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " HSMCI1_set/clr ,High Speed Multimedia Card Interface 1(Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LCDC_set/clr ,LCD Controller (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " EMAC0_set/clr ,Ethernet MAC0 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35")
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " EMAC_set/clr ,Ethernet MAC (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " UDP_set/clr ,USB Device (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHP_set/clr ,USB Host (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMAC1_set/clr ,DMA Controller 1 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC_set/clr ,DMA Controller (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC0_set/clr ,DMA Controller 0 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " ADC_set/clr ,ADC Controller (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TC0_TC1_set/clr ,Timer Counter (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " UART1_set/clr ,UART 1 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " UART0_set/clr ,UART0 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI1_set/clr ,Serial Peripheral Interface 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " SPI0_set/clr ,Serial Peripheral Interface 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " HSMCI_set/clr ,High Speed Multimedia Card Interface (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " HSMCI0_set/clr ,High Speed Multimedia Card Interface 0 (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TWI2_set/clr ,Two-Wire Interface 2 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
sif (cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " USART3_set/clr ,USART3 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " USART2_set/clr ,USART2 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " USART1_set/clr ,USART1 (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " USART0_set/clr ,USART0 (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " FUSE_set/clr ,FUSE Controller (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SMD_set/clr ,SMD Soft Modem (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOC_PIOD_set/clr ,Parallel I/O Controller C and D (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA_PIOB_set/clr ,Parallel I/O Controller A and B (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9M10")
|
|
textline " "
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " VDEC_set/clr ,Video Decoder (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_set/clr ,High Speed Multimedia Card Interface 1 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_set/clr ,High Speed Multimedia Card Interface 1 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " AES_TDES_SHA_set/clr ,Advanced Encryption Standard & Triple Data Encryption Standard & Secure Hash Algorithm (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " UDPHS_set/clr ,USB High Speed Device Port (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_set/clr ,Image Sensor Interface (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " EMAC_set/clr ,Ethernet MAC (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " AC97_set/clr ,AC97 Controller (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDC_set/clr ,LCD Controller (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMA_set/clr ,DMA Controller (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TSADCC_set/clr ,Touch Screen ADC Controller (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PWMC_set/clr ,Pulse Width Modulation Controller (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TC0-5_set/clr ,Timer Counter 0/1/2/3/4/5 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SSC1_set/clr ,Synchronous Serial Controller 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SSC0_set/clr ,Synchronous Serial Controller 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_set/clr ,Serial Peripheral Interface (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI0_set/clr ,Serial Peripheral Interface (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " MCI0_set/clr ,High Speed Multimedia Card Interface 0 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " US3_set/clr ,USART 3 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " US2_set/clr ,USART 2 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " US1_set/clr ,USART 1 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " US0_set/clr ,USART 0 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " TRNG_set/clr ,True Random Number Generator (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PIOD/PIOE_set/clr ,Parallel I/O Controller D/E (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9N12")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "On-Chip RC,Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x04 20. " RCMEAS ,RC Measure" "No effect,Restarded"
|
|
bitfld.long 0x04 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
else
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 28.--31. " BIASCOUNT , UTMI BIAS Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24. " BIASEN , UTMI BIAS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT , UTMI PLL Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " UPLLEN , UTMI PLL Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,Main Oscillator Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
bitfld.long 0x04 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MOSCSEL ,Main Oscillator Selection" "On-Chip RC,Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x04 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
else
|
|
hexmask.long.byte 0x04 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x04 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()!="AT91SAM9N12")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
endif
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
bitfld.long 0x00 29. " ONE ,One" "0,1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
hexmask.long.byte 0x00 16.--23. 1. " MULA ,PLLA Multiplier"
|
|
else
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range (CPLLA = 0/CPLLA = 1)" "745-800MHz/545-600MHz,695-750 MHz/495-550MHz,645-700 MHz/445-500 MHz,595-650 MHz/400-450 MHz"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULB ,PLL B Multiplier"
|
|
bitfld.long 0x00 14.--15. " OUTB ,PLL B Clock Frequency Range (CPLLA = 0/CPLLA = 1)" "745-800MHz/545-600MHz,695-750 MHz/495-550MHz,645-700 MHz/445-500 MHz,595-650 MHz/400-450 MHz"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLBCOUNT ,PLL B Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVB ,Divider B"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB OHCI Clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0. " USBS ,USB OHCI Input clock selection" "PLLA,UPLL"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,Processor Clock Division" "Clock,Clock/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,Clock/3"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 4.--6. " PRES ,Master/Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
bitfld.long 0x00 4.--6. " PRES ,Master/Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
else
|
|
bitfld.long 0x00 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 0.--1. " CSS ,Master/Processor Clock Source Selection" "Slow,Main,PLLA,UPLL"
|
|
elif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 0.--1. " CSS ,Master/Processor Clock Source Selection" "Slow,Main,PLLACK/PLLADIV2,PLLBCK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PMC_SMD,PMC SMD Clock Register"
|
|
bitfld.long 0x00 8.--12. " SMDDIV ,Divider for SMD Clock" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SMDS ,SMD input clock selection" "PLLA,UPLL"
|
|
endif
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Source Selection" "Slow,Main,PLLACK/PLLADIV2,PLLBCK,Master,?..."
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Source Selection" "Slow,Main,PLLACK/PLLADIV2,UPLL,Master,?..."
|
|
else
|
|
bitfld.long 0x0 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x0 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
endif
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Source Selection" "Slow,Main,PLLACK/PLLADIV2,PLLBCK,Master,?..."
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Source Selection" "Slow,Main,PLLACK/PLLADIV2,UPLL,Master,?..."
|
|
else
|
|
bitfld.long 0x4 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x4 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
wgroup.long 0x60++0x07
|
|
line.long 0x00 "PMC_IER,PMC Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " LOCKU ,UTMI PLL Lock Interrupt Enable" "Disable,Enable"
|
|
line.long 0x04 "PMC_IDR,PMC Interrupt Disable Register"
|
|
bitfld.long 0x04 6. " LOCKU ,UTMI PLL Lock Interrupt Disable" "Disable,Enable"
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 18. -0xc 18. -0x8 18. " CFDEV_set/clr ,Clock Failure Detector Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0xc 17. -0x8 17. " MOSCRCS_set/clr ,Main On-Chip RC Status Interrupt Mask" "Disabled,Enabled"
|
|
textline ""
|
|
setclrfld.long 0x00 16. -0xc 16. -0x8 16. " MOSCSELS_set/clr ,Main Oscillator Selection Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9M11")
|
|
setclrfld.long 0x00 11. -0xc 11. -0x8 11. " PCK5 ,Programmable Clock Output 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCK4 ,Programmable Clock Output 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
textline ""
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X35"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9N12")
|
|
setclrfld.long 0x00 6. -0xc 6. -0x8 6. " LOCKU_set/clr ,UTMI PLL Lock Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 2. -0xc 2. -0x8 2. " LOCKB_set/clr ,PLL B Lock Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCXTS_set/clr ,Main Crystal Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
sif (cpu()!="AT91SAM9M11")
|
|
bitfld.long 0x00 11. " PCK5 ,Programmable Clock Output 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PCK4 ,Programmable Clock Output 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOCKU ,UTMI PLL Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
endif
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,PLL Charge Pump Current Register"
|
|
bitfld.long 0x00 0. " ICPLLA ,Charge Pump Current" "Low,High"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12")
|
|
group.long 0xe4++0x03
|
|
line.long 0x00 "PMC_WPMR,PMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x03
|
|
hide.long 0x00 "PMC_WPSR,PMC Write Protect Status Register"
|
|
in
|
|
endif
|
|
sif (cpu()=="AT91SAM9N12")
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor value" "MCK,MCK/2,MCK/4,MCK/8"
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" "Reserved,Reserved,PIOA_PIOB,PIOC_PIOD,FUSE,USART0,USART1,USART2,USART3,TWI0,TWI1,Reserved,HSMCI,SPI0,SPI1,UART0,UART1,TC0_TC1,PWM,ADC,DMAC,Reserved,UHP,UDP,Reserved,LCDC,Reserved,SHA,SSC,AES,TRNG,AIC,?..."
|
|
elif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 28. " EN ,Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor value" "MCK,MCK/2,MCK/4,MCK/8"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read,Write"
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" "Reserved,Reserved,PIOA_PIOB,PIOC_PIOD,SMD,USART0,USART1,USART2,USART3,TWI0,TWI1,TWI2,HSMCI0,SPI0,SPI1,UART0,UART1,TC0_TC1,PWM,ADC,DMAC0,DMAC1,UHPHS,UDPHS,EMAC0,Reserved,HSMCI1,EMAC1,SSC,CAN0,CAN1,AIC,?..."
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " DDRCK_set/clr ,DDR Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Status" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "PMC_SCDR,PMC System Clock Disable Register"
|
|
bitfld.long 0x00 0. " PCK , Processor Clock Disable" "No effect,Disable"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AIC_IRQ_set/clr ,Advanced Interrupt Controller (IRQ1) (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " MCI1_set/clr ,High Speed Multimedia Card Interface 1 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " UDPHS_set/clr ,USB High Speed Device Port (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ISI_set/clr ,Image Sensor Interface (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " EMAC_set/clr ,Ethernet MAC (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " AC97_set/clr ,AC97 Controller (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " LCDC_set/clr ,LCD Controller (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " UHPHS_set/clr ,USB Host High Speed (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " DMA_set/clr ,DMA Controller (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " TSADCC_set/clr ,Touch Screen ADC Controller (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PWMC_set/clr ,Pulse Width Modulation Controller (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TC0-5_set/clr ,Timer Counter 0/1/2/3/4/5 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " SSC1_set/clr ,Synchronous Serial Controller 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " SSC0_set/clr ,Synchronous Serial Controller 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " SPI1_set/clr ,Serial Peripheral Interface (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " SPI0_set/clr ,Serial Peripheral Interface (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " MCI0_set/clr ,High Speed Multimedia Card Interface 0 (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " US3_set/clr ,USART 3 (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " US2_set/clr ,USART 2 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " US1_set/clr ,USART 1 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " US0_set/clr ,USART 0 (Peripheral ID 7) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " RNG_set/clr ,True Random Number Generator (Peripheral ID 6) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PIOD/PIOE_set/clr ,Parallel I/O Controller D/E (Peripheral ID 5) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 4) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 3) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 2) Clock Status" "Disabled,Enabled"
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 28.--31. " BIASCOUNT , UTMI BIAS Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24. " BIASEN , UTMI BIAS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT , UTMI PLL Start-up Time" "0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120"
|
|
bitfld.long 0x00 16. " UPLLEN , UTMI PLL Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,Main Oscillator Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x04 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range (CPLLA = 0/CPLLA = 1)" "745-800MHz/545-600MHz,695-750 MHz/495-550MHz,645-700 MHz/445-500 MHz,595-650 MHz/400-450 MHz"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB OHCI Clock" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0. " USBS ,USB OHCI Input clock selection" "PLLA,UPLL"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 12. " PLLADIV2 ,Processor Clock Division" "Clock,Clock/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,Clock/3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x0 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 8. " SLCKMCK ,Slow Clock or Master Clock Selection" "Slow,Master"
|
|
bitfld.long 0x4 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLLACK/PLLADIV2,UPLLCK"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0xc 6. -0x8 6. " LOCKU_set/clr ,UTMI PLL Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LOCKU ,UTMI PLL Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "PMC_PLLICPR,PLL Charge Pump Current Register"
|
|
bitfld.long 0x00 0. " ICPLLA ,Charge Pump Current" "Low,High"
|
|
width 0xb
|
|
else
|
|
width 0x11
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PCK3_Clear/Set ,Programmable Clock 3 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK2_Clear/Set ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_Clear/Set ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_Clear/Set ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_Clear/Set ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " UHP_Clear/Set ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " PCK_Clear/Set ,Processor Clock Status" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " PID31_Clear/Set ,Peripheral Clock 31 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " PID30_Clear/Set ,Peripheral Clock 30 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " PID29_Clear/Set ,Peripheral Clock 29 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " PID28_Clear/Set ,Peripheral Clock 28 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " PID27_Clear/Set ,Peripheral Clock 27 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " PID26_Clear/Set ,Peripheral Clock 26 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " PID25_Clear/Set ,Peripheral Clock 25 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " PID24_Clear/Set ,Peripheral Clock 24 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " PID23_Clear/Set ,Peripheral Clock 23 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " PID22_Clear/Set ,Peripheral Clock 22 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " PID21_Clear/Set ,Peripheral Clock 21 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " PID20_Clear/Set ,Peripheral Clock 20 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PID19_Clear/Set ,Peripheral Clock 19 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " PID18_Clear/Set ,Peripheral Clock 18 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " PID17_Clear/Set ,Peripheral Clock 17 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " PID16_Clear/Set ,Peripheral Clock 16 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PID15_Clear/Set ,Peripheral Clock 15 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PID14_Clear/Set ,Peripheral Clock 14 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PID13_Clear/Set ,Peripheral Clock 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PID12_Clear/Set ,Peripheral Clock 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PID11_Clear/Set ,Peripheral Clock 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PID10_Clear/Set ,Peripheral Clock 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PID9_Clear/Set ,Peripheral Clock 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PID8_Clear/Set ,Peripheral Clock 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PID7_Clear/Set ,Peripheral Clock 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " PID6_Clear/Set ,Peripheral Clock 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " PID5_Clear/Set ,Peripheral Clock 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " PID4_Clear/Set ,Peripheral Clock 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " PID3_Clear/Set ,Peripheral Clock 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " PID2_Clear/Set ,Peripheral Clock 2 Status" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OSCOUNT ,Main Oscillator Start-up Time"
|
|
bitfld.long 0x00 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0xB
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
hexmask.long.word 0x00 16.--23. 1. " MULA ,PLL A Multiplier"
|
|
bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range (ICPLLA=0 / ICPLLA=1)" "745-800 MHz / 545-600 MHz,695-750 MHz / 495-550 MHz,645-700 MHz / 445-500 MHz,595-650 MHz / 400-450 MHz"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
line.long 0x4 "CKGR_PLLBR,PMC Clock Generator PLL B Register"
|
|
bitfld.long 0x4 28.--29. " USBDIV ,Divider for USB Clock" "PLL B,PLL B/2,PLL B/4,?..."
|
|
hexmask.long.word 0x4 16.--21. 1. " MULB ,PLL Multiplier"
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " OUTB ,PLL B Clock Frequency Range" "30-100 MHz,?..."
|
|
hexmask.long.byte 0x4 8.--13. 1. " PLLBCOUNT ,PLL B Counter"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. " DIVB ,Divider B"
|
|
line.long 0x8 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x8 12. " PDIV ,Processor Clock Division" "Clock,Clock/2"
|
|
textline " "
|
|
bitfld.long 0x8 8.--9. " MDIV ,Master Clock Division" "Clock,Clock/2,Clock/4,Clock/6"
|
|
bitfld.long 0x8 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
group.long 0x40++0x07
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL A,PLL B"
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR_Set/Clr,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 11. -0xc 11. -0x8 11. " PCKRDY3 ,Programmable Clock Ready 3 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2 ,Programmable Clock Ready 2 Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1 ,Programmable Clock Ready 1 Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0 ,Programmable Clock Ready 0 Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY ,Master Clock Ready Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0xc 2. -0x8 2. " LOCKB ,PLL B Lock Interrupt Mask" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA ,PLL A Lock Interrupt Mask" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCS ,Main Oscillator Status Interrupt Mask" "Enabled,Disabled"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "PMC_SR,PMC Status Register"
|
|
bitfld.long 0x00 9. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCKRDY ,Master Clock Status" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " LOCKB ,PLL B Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCKA ,PLL A Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0xfffff000
|
|
width 11.
|
|
tree "Source Mode Registers"
|
|
group.long 0x00++0x7f
|
|
line.long 0x0 "AIC_SMR0,AIC Source Mode Register 0"
|
|
bitfld.long 0x0 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G46")
|
|
bitfld.long 0x0 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
endif
|
|
line.long 0x4 "AIC_SMR1,AIC Source Mode Register 1"
|
|
bitfld.long 0x4 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x8 "AIC_SMR2,AIC Source Mode Register 2"
|
|
bitfld.long 0x8 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x8 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0xC "AIC_SMR3,AIC Source Mode Register 3"
|
|
bitfld.long 0xC 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0xC 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x10 "AIC_SMR4,AIC Source Mode Register 4"
|
|
bitfld.long 0x10 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x10 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x14 "AIC_SMR5,AIC Source Mode Register 5"
|
|
bitfld.long 0x14 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x14 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x18 "AIC_SMR6,AIC Source Mode Register 6"
|
|
bitfld.long 0x18 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x18 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x1C "AIC_SMR7,AIC Source Mode Register 7"
|
|
bitfld.long 0x1C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x1C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x20 "AIC_SMR8,AIC Source Mode Register 8"
|
|
bitfld.long 0x20 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x20 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x24 "AIC_SMR9,AIC Source Mode Register 9"
|
|
bitfld.long 0x24 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x24 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x28 "AIC_SMR10,AIC Source Mode Register 10"
|
|
bitfld.long 0x28 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x28 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x2C "AIC_SMR11,AIC Source Mode Register 11"
|
|
bitfld.long 0x2C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x2C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x30 "AIC_SMR12,AIC Source Mode Register 12"
|
|
bitfld.long 0x30 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x30 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x34 "AIC_SMR13,AIC Source Mode Register 13"
|
|
bitfld.long 0x34 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x34 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x38 "AIC_SMR14,AIC Source Mode Register 14"
|
|
bitfld.long 0x38 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x38 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x3C "AIC_SMR15,AIC Source Mode Register 15"
|
|
bitfld.long 0x3C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x3C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x40 "AIC_SMR16,AIC Source Mode Register 16"
|
|
bitfld.long 0x40 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x40 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x44 "AIC_SMR17,AIC Source Mode Register 17"
|
|
bitfld.long 0x44 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x44 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x48 "AIC_SMR18,AIC Source Mode Register 18"
|
|
bitfld.long 0x48 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x48 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x4C "AIC_SMR19,AIC Source Mode Register 19"
|
|
bitfld.long 0x4C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x4C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x50 "AIC_SMR20,AIC Source Mode Register 20"
|
|
bitfld.long 0x50 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x50 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x54 "AIC_SMR21,AIC Source Mode Register 21"
|
|
bitfld.long 0x54 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x54 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x58 "AIC_SMR22,AIC Source Mode Register 22"
|
|
bitfld.long 0x58 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x58 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x5C "AIC_SMR23,AIC Source Mode Register 23"
|
|
bitfld.long 0x5C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x5C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x60 "AIC_SMR24,AIC Source Mode Register 24"
|
|
bitfld.long 0x60 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x60 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x64 "AIC_SMR25,AIC Source Mode Register 25"
|
|
bitfld.long 0x64 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x64 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x68 "AIC_SMR26,AIC Source Mode Register 26"
|
|
bitfld.long 0x68 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x68 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x6C "AIC_SMR27,AIC Source Mode Register 27"
|
|
bitfld.long 0x6C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x6C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x70 "AIC_SMR28,AIC Source Mode Register 28"
|
|
bitfld.long 0x70 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x70 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x74 "AIC_SMR29,AIC Source Mode Register 29"
|
|
bitfld.long 0x74 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x74 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x78 "AIC_SMR30,AIC Source Mode Register 30"
|
|
bitfld.long 0x78 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x78 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
line.long 0x7C "AIC_SMR31,AIC Source Mode Register 31"
|
|
bitfld.long 0x7C 5.--6. " SRCTYPE ,Interrupt Source Type (Internal/External)" "High/low,Positive/negative,High/high,Positive/positive"
|
|
bitfld.long 0x7C 0.--2. " PRIOR ,Priority Level" "Lowest,1,2,3,4,5,6,Highest"
|
|
tree.end
|
|
tree "Source Vector Registers"
|
|
group.long 0x80++0x7f
|
|
textline ""
|
|
line.long 0x0 "AIC_SVR0 ,AIC Source Vector Register 0 "
|
|
textline ""
|
|
line.long 0x4 "AIC_SVR1 ,AIC Source Vector Register 1 "
|
|
textline ""
|
|
line.long 0x8 "AIC_SVR2 ,AIC Source Vector Register 2 "
|
|
textline ""
|
|
line.long 0xC "AIC_SVR3 ,AIC Source Vector Register 3 "
|
|
textline ""
|
|
line.long 0x10 "AIC_SVR4 ,AIC Source Vector Register 4 "
|
|
textline ""
|
|
line.long 0x14 "AIC_SVR5 ,AIC Source Vector Register 5 "
|
|
textline ""
|
|
line.long 0x18 "AIC_SVR6 ,AIC Source Vector Register 6 "
|
|
textline ""
|
|
line.long 0x1C "AIC_SVR7 ,AIC Source Vector Register 7 "
|
|
textline ""
|
|
line.long 0x20 "AIC_SVR8 ,AIC Source Vector Register 8 "
|
|
textline ""
|
|
line.long 0x24 "AIC_SVR9 ,AIC Source Vector Register 9 "
|
|
textline ""
|
|
line.long 0x28 "AIC_SVR10,AIC Source Vector Register 10"
|
|
textline ""
|
|
line.long 0x2C "AIC_SVR11,AIC Source Vector Register 11"
|
|
textline ""
|
|
line.long 0x30 "AIC_SVR12,AIC Source Vector Register 12"
|
|
textline ""
|
|
line.long 0x34 "AIC_SVR13,AIC Source Vector Register 13"
|
|
textline ""
|
|
line.long 0x38 "AIC_SVR14,AIC Source Vector Register 14"
|
|
textline ""
|
|
line.long 0x3C "AIC_SVR15,AIC Source Vector Register 15"
|
|
textline ""
|
|
line.long 0x40 "AIC_SVR16,AIC Source Vector Register 16"
|
|
textline ""
|
|
line.long 0x44 "AIC_SVR17,AIC Source Vector Register 17"
|
|
textline ""
|
|
line.long 0x48 "AIC_SVR18,AIC Source Vector Register 18"
|
|
textline ""
|
|
line.long 0x4C "AIC_SVR19,AIC Source Vector Register 19"
|
|
textline ""
|
|
line.long 0x50 "AIC_SVR20,AIC Source Vector Register 20"
|
|
textline ""
|
|
line.long 0x54 "AIC_SVR21,AIC Source Vector Register 21"
|
|
textline ""
|
|
line.long 0x58 "AIC_SVR22,AIC Source Vector Register 22"
|
|
textline ""
|
|
line.long 0x5C "AIC_SVR23,AIC Source Vector Register 23"
|
|
textline ""
|
|
line.long 0x60 "AIC_SVR24,AIC Source Vector Register 24"
|
|
textline ""
|
|
line.long 0x64 "AIC_SVR25,AIC Source Vector Register 25"
|
|
textline ""
|
|
line.long 0x68 "AIC_SVR26,AIC Source Vector Register 26"
|
|
textline ""
|
|
line.long 0x6C "AIC_SVR27,AIC Source Vector Register 27"
|
|
textline ""
|
|
line.long 0x70 "AIC_SVR28,AIC Source Vector Register 28"
|
|
textline ""
|
|
line.long 0x74 "AIC_SVR29,AIC Source Vector Register 29"
|
|
textline ""
|
|
line.long 0x78 "AIC_SVR30,AIC Source Vector Register 30"
|
|
textline ""
|
|
line.long 0x7C "AIC_SVR31,AIC Source Vector Register 31"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "AIC_IVR,AIC Interrupt Vector Register"
|
|
line.long 0x04 "AIC_FVR,AIC FIQ Vector Register"
|
|
line.long 0x08 "AIC_ISR,AIC Interrupt Status Register"
|
|
bitfld.long 0x08 0.--4. " IRQID ,Current Interrupt Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x07
|
|
line.long 0x0 "AIC_IPR,AIC Interrupt Pending Register"
|
|
setclrfld.long 0x0 31. 0x20 31. 0x1C 31. " PID31_set/clr ,Interrupt 31 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 30. 0x20 30. 0x1C 30. " PID30_set/clr ,Interrupt 30 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x20 29. 0x1C 29. " PID29_set/clr ,Interrupt 29 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 28. 0x20 28. 0x1C 28. " PID28_set/clr ,Interrupt 28 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x20 27. 0x1C 27. " PID27_set/clr ,Interrupt 27 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 26. 0x20 26. 0x1C 26. " PID26_set/clr ,Interrupt 26 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x20 25. 0x1C 25. " PID25_set/clr ,Interrupt 25 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 24. 0x20 24. 0x1C 24. " PID24_set/clr ,Interrupt 24 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x20 23. 0x1C 23. " PID23_set/clr ,Interrupt 23 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 22. 0x20 22. 0x1C 22. " PID22_set/clr ,Interrupt 22 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x20 21. 0x1C 21. " PID21_set/clr ,Interrupt 21 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 20. 0x20 20. 0x1C 20. " PID20_set/clr ,Interrupt 20 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x20 19. 0x1C 19. " PID19_set/clr ,Interrupt 19 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 18. 0x20 18. 0x1C 18. " PID18_set/clr ,Interrupt 18 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x20 17. 0x1C 17. " PID17_set/clr ,Interrupt 17 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 16. 0x20 16. 0x1C 16. " PID16_set/clr ,Interrupt 16 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x20 15. 0x1C 15. " PID15_set/clr ,Interrupt 15 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 14. 0x20 14. 0x1C 14. " PID14_set/clr ,Interrupt 14 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x20 13. 0x1C 13. " PID13_set/clr ,Interrupt 13 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 12. 0x20 12. 0x1C 12. " PID12_set/clr ,Interrupt 12 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x20 11. 0x1C 11. " PID11_set/clr ,Interrupt 11 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 10. 0x20 10. 0x1C 10. " PID10_set/clr ,Interrupt 10 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x20 9. 0x1C 9. " PID9_set/clr ,Interrupt 9 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 8. 0x20 8. 0x1C 8. " PID8_set/clr ,Interrupt 8 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x20 7. 0x1C 7. " PID7_set/clr ,Interrupt 7 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 6. 0x20 6. 0x1C 6. " PID6_set/clr ,Interrupt 6 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x20 5. 0x1C 5. " PID5_set/clr ,Interrupt 5 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 4. 0x20 4. 0x1C 4. " PID4_set/clr ,Interrupt 4 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x20 3. 0x1C 3. " PID3_set/clr ,Interrupt 3 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 2. 0x20 2. 0x1C 2. " PID2_set/clr ,Interrupt 2 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x20 1. 0x1C 1. " SYS_set/clr ,SYS Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0 0. 0x20 0. 0x1C 0. " FIQ_set/clr ,FIQ Interrupt Pending" "Not pending,Pending"
|
|
line.long 0x4 "AIC_IMR,AIC Interrupt Mask Register"
|
|
setclrfld.long 0x4 31. 0x14 31. 0x18 31. " PID31_set/clr ,Interrupt 31 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x14 30. 0x18 30. " PID30_set/clr ,Interrupt 30 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x14 29. 0x18 29. " PID29_set/clr ,Interrupt 29 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x14 28. 0x18 28. " PID28_set/clr ,Interrupt 28 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x14 27. 0x18 27. " PID27_set/clr ,Interrupt 27 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x14 26. 0x18 26. " PID26_set/clr ,Interrupt 26 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x14 25. 0x18 25. " PID25_set/clr ,Interrupt 25 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x14 24. 0x18 24. " PID24_set/clr ,Interrupt 24 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x14 23. 0x18 23. " PID23_set/clr ,Interrupt 23 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x14 22. 0x18 22. " PID22_set/clr ,Interrupt 22 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x14 21. 0x18 21. " PID21_set/clr ,Interrupt 21 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x14 20. 0x18 20. " PID20_set/clr ,Interrupt 20 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x14 19. 0x18 19. " PID19_set/clr ,Interrupt 19 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x14 18. 0x18 18. " PID18_set/clr ,Interrupt 18 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x14 17. 0x18 17. " PID17_set/clr ,Interrupt 17 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x14 16. 0x18 16. " PID16_set/clr ,Interrupt 16 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x14 15. 0x18 15. " PID15_set/clr ,Interrupt 15 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x14 14. 0x18 14. " PID14_set/clr ,Interrupt 14 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x14 13. 0x18 13. " PID13_set/clr ,Interrupt 13 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x14 12. 0x18 12. " PID12_set/clr ,Interrupt 12 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x14 11. 0x18 11. " PID11_set/clr ,Interrupt 11 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x14 10. 0x18 10. " PID10_set/clr ,Interrupt 10 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x14 9. 0x18 9. " PID9_set/clr ,Interrupt 9 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x14 8. 0x18 8. " PID8_set/clr ,Interrupt 8 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x14 7. 0x18 7. " PID7_set/clr ,Interrupt 7 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x14 6. 0x18 6. " PID6_set/clr ,Interrupt 6 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x14 5. 0x18 5. " PID5_set/clr ,Interrupt 5 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x14 4. 0x18 4. " PID4_set/clr ,Interrupt 4 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x14 3. 0x18 3. " PID3_set/clr ,Interrupt 3 Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x14 2. 0x18 2. " PID2_set/clr ,Interrupt 2 Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x14 1. 0x18 1. " SYS_set/clr ,SYS Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x4 0. 0x14 0. 0x18 0. " FIQ_set/clr ,FIQ Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "AIC_CISR,AIC Core Interrupt Status Register"
|
|
bitfld.long 0x0 1. " NIRQ ,NIRQ Status" "Deactivated,Activated"
|
|
bitfld.long 0x0 0. " NFIQ ,NFIQ Status" "Deactivated,Activated"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x0 "AIC_EOICR,AIC End of Interrupt Command Register"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "AIC_SPU,AIC Spurious Interrupt Vector Register"
|
|
line.long 0x04 "AIC_DEBUG,AIC Debug Control Register"
|
|
bitfld.long 0x04 1. " GMSK ,General Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " PROT ,Protection Mode" "Disabled,Enabled"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "AIC_FFSR,Fast Forcing Status Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " PID31_set/clr ,Interrupt 31 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " PID30_set/clr ,Interrupt 30 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " PID29_set/clr ,Interrupt 29 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " PID28_set/clr ,Interrupt 28 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " PID27_set/clr ,Interrupt 27 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " PID26_set/clr ,Interrupt 26 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " PID25_set/clr ,Interrupt 25 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " PID24_set/clr ,Interrupt 24 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " PID23_set/clr ,Interrupt 23 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " PID22_set/clr ,Interrupt 22 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " PID21_set/clr ,Interrupt 21 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " PID20_set/clr ,Interrupt 20 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " PID19_set/clr ,Interrupt 19 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " PID18_set/clr ,Interrupt 18 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " PID17_set/clr ,Interrupt 17 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " PID16_set/clr ,Interrupt 16 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " PID15_set/clr ,Interrupt 15 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " PID14_set/clr ,Interrupt 14 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " PID13_set/clr ,Interrupt 13 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " PID12_set/clr ,Interrupt 12 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " PID11_set/clr ,Interrupt 11 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " PID10_set/clr ,Interrupt 10 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " PID9_set/clr ,Interrupt 9 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " PID8_set/clr ,Interrupt 8 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " PID7_set/clr ,Interrupt 7 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " PID6_set/clr ,Interrupt 6 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " PID5_set/clr ,Interrupt 5 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " PID4_set/clr ,Interrupt 4 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " PID3_set/clr ,Interrupt 3 Fast Forcing Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " PID2_set/clr ,Interrupt 2 Fast Forcing Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " SYS_set/clr ,SYS Interrupt Fast Forcing Status" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9N12"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35")
|
|
group.long 0x1e4++0x3
|
|
line.long 0x00 "AIC_WPMR,AIC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "AIC_WPSR,AIC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DBGU (Debug Unit)"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xffffee00
|
|
else
|
|
base ad:0xfffff200
|
|
endif
|
|
tree "PDC_DBGU"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xffffee00
|
|
else
|
|
base ad:0xfffff200
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "DBGU_RPR,Debug Unit Receive Pointer Register"
|
|
line.long 0x04 "DBGU_RCR,Debug Unit Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "DBGU_TPR,Debug Unit Transmit Pointer Register"
|
|
line.long 0x0c "DBGU_TCR,Debug Unit Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "DBGU_RNPR,Debug Unit Receive Next Pointer Register"
|
|
line.long 0x14 "DBGU_RNCR,Debug Unit Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "DBGU_TNPR,Debug Unit Transmit Next Pointer Register"
|
|
line.long 0x1c "DBGU_TNCR,Debug Unit Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "DBGU_PTCR,Debug Unit PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DBGU_PTSR,Debug Unit PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output Controller)"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree "PIOA"
|
|
base ad:0xfffff200
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DMARQ1,ISI_D11"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TIOB0,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TIOA0,ISI_D9"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI0_NPCS3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "PCK1,ISI_MCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "SCK0,ISI_VSYNC"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "CTS0,ISI_HSYNC"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RTS0,ISI_PCK"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "RXD0,ISI_D7"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TXD0,ISI_D6"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "MCI1_D3,ISI_D5"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "MCI1_D2,ISI_D4"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "MCI1_D1,ISI_D3"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "MCI1_D0,ISI_D2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "MCI1_CD,ISI_D1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "MCI1_CK,ISI_D0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "DMARQ3,PCK2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TCLK2,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "CANRX,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "CANTX,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "DMARQ0,PWM3"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "IRQ0,PWM1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "AC97RX,?..."
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "AC97TX,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "AC97CK,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "AC97FS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_D3,SPI0_NPCS0"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_D2,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_D1,SPI0_NPCS1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_CK,SPI0_SPCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CD,SPI0_MOSI"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_D0,SPI0_MISO"
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "TPK15,A24"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TPK14,A23"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TPK13,SPI0_NPCS3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "TPK12,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "TPK11,SPI0_NPCS1"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "TPK10,SPI1_NPCS3"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "TPK9,SPI1_NPCS2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "TPK8,SPI1_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TPK7,RTS0"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TPK6,RF1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TPK5,RK1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TPK4,RD1"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TPK3,TD1"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "TPK2,TK1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "TPK1,TF1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "TPK0,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "TPS2,RTS2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TPS1,SCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "TPS0,CTS1"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TCLK,RTS1"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TSYNC,SCK1"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "DTXD,PCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "DRXD,PCK2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TWCK,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TWD,PCK0"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "SPI0_NPCS3,MCDA3"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "SPI0_NPCS2,MCDA2"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "SPI0_NPCS1,MCDA1"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,MCCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,MCCDA"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,MCDA0"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "MCI1_CK,PCK0"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "MCI1_DA7,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "MCI1_DA6,ECRS"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "MCI1_DA5,ERXCK"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "MCI1_DA4,ETXER"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "MCI1_DA3,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "MCI1_DA2,PWM3"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "MCI1_DA1,CTS3"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "MCI1_DA0,RTS3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "MCI1_CDA,SCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TWCK0,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TWD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "EMDIO,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "EMDC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "ETXCK,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "ERXER,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "ERXDV,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "ETXEN,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "ERX1,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "ERX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "ETX1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "ETX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "MCI0_DA7,ERX3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "MCI0_DA6,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "MCI0_DA5,ETX3"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "MCI0_DA4,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_DA3,TIOB4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_DA2,TIOA4"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_DA1,TCKL4"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_DA0,TIOB3"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CDA,TIOA3"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_CK,TCLK3"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ADTRIG,EF100"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "EMDIO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "EMDC,PWM3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ETXEN,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ERXER,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ERX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ERX0,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ETX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ETX0,PCK3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ERXDV,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ETXCK/EREFCK,TIOA2"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "PWM1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "PWM0,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "SPI1_NPCS3,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS2,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_NPCS1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_NPCS0,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "SPI1_MOSI,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "RF1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RK1,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RD1,LCDCC"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TD1,PWM2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TK1,TIOB1"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TF1,TIOA1"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RF0,TWCK"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "RK0,TWD"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RD0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "TK0,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TF0,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "SPI1_MOSI,PCK2"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "SPI1_MISO,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "SPI1_SPCK,IRQ2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI1_NPCS0,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "SPI1_NPCS1,LCDD22"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "RF0,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "RK0,LCDD20"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RD0,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TD0,LCDD18"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TK0,LCDD17"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TF0,LCDD16"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD15,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD14,LCDD22"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD13,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD12,LCDD20"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD11,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD10,LCDD15"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD9,LCDD14"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD8,LCDD13"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD7,LCDD12"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD6,LCDD11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD5,LCDD10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD4,LCDD7"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD3,LCDD6"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD2,LCDD5"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD1,LCDD4"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD0,LCDD3"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDCC,LCDD2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ISI_MCK,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "ISI_HSYNC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "ISI_VSYNC,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ISI_PCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ISI_D7,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ISI_D6,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ISI_D5,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ISI_D4,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ISI_D3,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ISI_D2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ISI_D1,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "ISI_D0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TXD0,SPI0_NPCS2"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "RXD0,SPI0_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS0,RTS0"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_SPCK,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_MOSI,CTS0"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "DTXD,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TWCK1,ISI_D11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "TWD1,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD3,ISI_D9"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "RXD2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TXD2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RXD1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "TXD1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DTXD,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "PCK0,PWM2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "PWM0,TCLK1"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "LCDD23,ERXCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "LCDD22,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "LCDD21,ECRS"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "LCDD20,ETXER"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "LCDD19,ERX3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "LCDD18,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "LCDD17,ETX3"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD16,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD15,LCDD23"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD14,LCDD22"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD13,LCDD21"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD12,LCDD20"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD11,LCDD19"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD10,LCDD15"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD9,LCDD14"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD8,LCDD13"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD7,LCDD12"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD6,LCDD11"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD5,LCDD10"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD4,LCDD7"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD3,LCDD6"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD2,LCDD5"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD1,LCDD4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDD0,LCDD3"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,PWM1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,RF2"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,RK2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,RD2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,TD2"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,TK2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,TF2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,TIOA2"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,TIOB1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,TIOA1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,TIOB0"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,TIOA0"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,TCLK1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "RXD2,SPI1_NPCS3"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TXD2,SPI1_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "RXD1,NCS7"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TXD1,NCS6"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "CTS0,FIQ"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RTS0,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD0,PCK3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD0,PCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "CFCE2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "NCS5/CFCS1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "NCS4/CFCS0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A25/CFRNW,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "NWAIT,IRQ0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "NANDWE,NCS7"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "NANDOE,NCS6"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "NWAIT,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "NCS3/NANDCS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "NCS2,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A25/CFRNW,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "NCS5/CFCS1,CTS2"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "NCS4/CFCS0,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "CFCE2,RTS2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A24,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A22/NANDCLE,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A21/NANDALE,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A20,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A19,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "DQM3,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "DQM2,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
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|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
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|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
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|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
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|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xfffff800
|
|
width 11.
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|
group.long 0x8++0x3
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|
line.long 0x0 "PIOD_PSR,PIOD Controller PIO Status Register"
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|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
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|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
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|
textline " "
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|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
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|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
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|
textline " "
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|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
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|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
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|
textline " "
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|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
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|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
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|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
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|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOD_OSR,PIOD Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
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|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
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|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
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|
textline " "
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|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
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|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
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|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
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|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
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|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOD_IFSR,PIOD Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOD_ODSR,PIOD Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOD_PDSR,PIOD Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOD_IMR,PIOD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOD_ISR,PIOD Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOD_MDSR,PIOD Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOD_PUSR,PIOD Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "NCS3/NANDCS,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A25/CFRNW,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A24,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "NCS2,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "CFCE2,SCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "CFCE1,SCK2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "NCS5/CFCS1,CTS1"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "NCS4/CFCS0,RTS1"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "NWAIT,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "DMARQ2,RTS2"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "FIQ,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RXD2,SPI1_NPCS3"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TXD2,SPI1_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "RXD1,SPI0_NPCS3"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TXD1,SPI0_NPCS2"
|
|
elif (cpu()=="AT91SAM9G10")
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "TIOB1,PWM1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TIOB0,SCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TCLK1,SCK1"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "TSADTRG,SPI1_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "PCK1,SPI0_NPCS3"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "PCK0,PWM2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "SPI0_NPCS2,PWM1"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "SPI0_NPCS1,PWM0"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TCLK0,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TIOA2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TIOA1,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TIOA0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "SPI1_NPCS3,FIQ"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "SPI1_NPCS2,IRQ"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "CTS1,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "RTS1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "RF1,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TF1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "RK1,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TK1,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "RD1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "TD1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "AC97CK,TCLK5"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "AC97FS,TIOB5"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "AC97TX,TIOA5"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "AC97RX,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RF0,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "RK0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RD0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "TF0,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TK0,PWM3"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOD_ABSR,PIOD Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOD_OWSR,PIOD Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOE"
|
|
base ad:0xfffffa00
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOE_PSR,PIOE Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOE_OSR,PIOE Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOE_IFSR,PIOE Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOE_ODSR,PIOE Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOE_PDSR,PIOE Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOE_IMR,PIOE Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOE_ISR,PIOE Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOE_MDSR,PIOE Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOE_PUSR,PIOE Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
elif (cpu()=="AT91SAM9G10")
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOE_ABSR,PIOE Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "PWM2,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "LCDD23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "LCDD22,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "LCDD21,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "LCDD20,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "LCDD19,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "LCDD18,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "LCDD17,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "LCDD16,LCDD22"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "LCDD15,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "LCDD14,LCDD20"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD13,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD12,LCDD18"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD11,LCDD15"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD10,LCDD14"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD9,LCDD13"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD8,LCDD12"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD7,LCDD11"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD6,LCDD10"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD5,LCDD7"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD4,LCDD6"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD3,LCDD5"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD2,LCDD4"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD1,LCDD3"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD0,LCDD2"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDDEN,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDDOTCK,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDHSYNC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDVSYNC,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDCC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDMOD,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDPWR,PCK0"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOE_ABSR,PIOE Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOE_OWSR,PIOE Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "PIOA"
|
|
base ad:0xfffff400
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOA_PSR,PIOA Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOA_OSR,PIOA Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOA_IFSR,PIOA Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOA_ODSR,PIOA Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOA_PDSR,PIOA Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOA_IMR,PIOA Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOA_ISR,PIOA Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOA_MDSR,PIOA Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOA_PUSR,PIOA Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DMARQ1,ISI_D11"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TIOB0,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TIOA0,ISI_D9"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI0_NPCS3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "PCK1,ISI_MCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "SCK0,ISI_VSYNC"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "CTS0,ISI_HSYNC"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RTS0,ISI_PCK"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "RXD0,ISI_D7"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TXD0,ISI_D6"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "MCI1_D3,ISI_D5"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "MCI1_D2,ISI_D4"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "MCI1_D1,ISI_D3"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "MCI1_D0,ISI_D2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "MCI1_CD,ISI_D1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "MCI1_CK,ISI_D0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "DMARQ3,PCK2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TCLK2,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "CANRX,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "CANTX,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "DMARQ0,PWM3"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "IRQ0,PWM1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "AC97RX,?..."
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "AC97TX,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "AC97CK,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "AC97FS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_D3,SPI0_NPCS0"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_D2,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_D1,SPI0_NPCS1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_CK,SPI0_SPCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CD,SPI0_MOSI"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_D0,SPI0_MISO"
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "TPK15,A24"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "TPK14,A23"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "TPK13,SPI0_NPCS3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "TPK12,SPI0_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "TPK11,SPI0_NPCS1"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "TPK10,SPI1_NPCS3"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "TPK9,SPI1_NPCS2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "TPK8,SPI1_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TPK7,RTS0"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TPK6,RF1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TPK5,RK1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TPK4,RD1"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TPK3,TD1"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "TPK2,TK1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "TPK1,TF1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "TPK0,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "TPS2,RTS2"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TPS1,SCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "TPS0,CTS1"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TCLK,RTS1"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TSYNC,SCK1"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "DTXD,PCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "DRXD,PCK2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TWCK,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TWD,PCK0"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "SPI0_NPCS3,MCDA3"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "SPI0_NPCS2,MCDA2"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "SPI0_NPCS1,MCDA1"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,MCCK"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,MCCDA"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,MCDA0"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "MCI1_CK,PCK0"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "MCI1_DA7,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "MCI1_DA6,ECRS"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "MCI1_DA5,ERXCK"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "MCI1_DA4,ETXER"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "MCI1_DA3,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "MCI1_DA2,PWM3"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "MCI1_DA1,CTS3"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "MCI1_DA0,RTS3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "MCI1_CDA,SCK3"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TWCK0,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "TWD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "EMDIO,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "EMDC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "ETXCK,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "ERXER,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "ERXDV,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "ETXEN,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "ERX1,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "ERX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "ETX1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "ETX0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "MCI0_DA7,ERX3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "MCI0_DA6,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "MCI0_DA5,ETX3"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "MCI0_DA4,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "MCI0_DA3,TIOB4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "MCI0_DA2,TIOA4"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "MCI0_DA1,TCKL4"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "MCI0_DA0,TIOB3"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "MCI0_CDA,TIOA3"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "MCI0_CK,TCLK3"
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOA_ABSR,PIOA Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOA_OWSR,PIOA Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xfffff600
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOB_PSR,PIOB Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOB_OSR,PIOB Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOB_IFSR,PIOB Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOB_ODSR,PIOB Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOB_PDSR,PIOB Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOB_IMR,PIOB Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOB_ISR,PIOB Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOB_MDSR,PIOB Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOB_PUSR,PIOB Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ADTRIG,EF100"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "EMDIO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "EMDC,PWM3"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ETXEN,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ERXER,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ERX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ERX0,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ETX1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ETX0,PCK3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ERXDV,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ETXCK/EREFCK,TIOA2"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "PWM1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "PWM0,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "SPI1_NPCS3,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS2,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_NPCS1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_NPCS0,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "SPI1_MOSI,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "RF1,?..."
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RK1,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RD1,LCDCC"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TD1,PWM2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "TK1,TIOB1"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TF1,TIOA1"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RF0,TWCK"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "RK0,TWD"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "RD0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "TD0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "TK0,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "TF0,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "SPI1_MOSI,PCK2"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "SPI1_MISO,IRQ1"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "SPI1_SPCK,IRQ2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "SPI1_NPCS0,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "SPI1_NPCS1,LCDD22"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "RF0,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "RK0,LCDD20"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "RD0,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "TD0,LCDD18"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "TK0,LCDD17"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "TF0,LCDD16"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD15,LCDD23"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD14,LCDD22"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD13,LCDD21"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD12,LCDD20"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD11,LCDD19"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD10,LCDD15"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD9,LCDD14"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD8,LCDD13"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD7,LCDD12"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD6,LCDD11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD5,LCDD10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD4,LCDD7"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD3,LCDD6"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD2,LCDD5"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD1,LCDD4"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD0,LCDD3"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDCC,LCDD2"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,PCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "ISI_MCK,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "ISI_HSYNC,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "ISI_VSYNC,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "ISI_PCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "ISI_D7,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "ISI_D6,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "ISI_D5,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "ISI_D4,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "ISI_D3,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "ISI_D2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "ISI_D1,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "ISI_D0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "TXD0,SPI0_NPCS2"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "RXD0,SPI0_NPCS1"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "SPI1_NPCS0,RTS0"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "SPI1_SPCK,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "SPI1_MOSI,CTS0"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "SPI1_MISO,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "DTXD,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "TWCK1,ISI_D11"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "TWD1,ISI_D10"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD3,ISI_D9"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD3,ISI_D8"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "RXD2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "TXD2,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "RXD1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "TXD1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "SPI0_NPCS0,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "SPI0_SPCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "SPI0_MOSI,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "SPI0_MISO,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOB_ABSR,PIOB Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOB_OWSR,PIOB Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xfffff800
|
|
width 11.
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PIOC_PSR,PIOC Controller PIO Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,PIO Status 31" "Peripheral,PIO"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,PIO Status 30" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,PIO Status 29" "Peripheral,PIO"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,PIO Status 28" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,PIO Status 27" "Peripheral,PIO"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,PIO Status 26" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,PIO Status 25" "Peripheral,PIO"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,PIO Status 24" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,PIO Status 23" "Peripheral,PIO"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,PIO Status 22" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,PIO Status 21" "Peripheral,PIO"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,PIO Status 20" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,PIO Status 19" "Peripheral,PIO"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,PIO Status 18" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,PIO Status 17" "Peripheral,PIO"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,PIO Status 16" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,PIO Status 15" "Peripheral,PIO"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,PIO Status 14" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,PIO Status 13" "Peripheral,PIO"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,PIO Status 12" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,PIO Status 11" "Peripheral,PIO"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,PIO Status 10" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,PIO Status 9" "Peripheral,PIO"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,PIO Status 8" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,PIO Status 7" "Peripheral,PIO"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,PIO Status 6" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,PIO Status 5" "Peripheral,PIO"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,PIO Status 4" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,PIO Status 3" "Peripheral,PIO"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,PIO Status 2" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,PIO Status 1" "Peripheral,PIO"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,PIO Status 0" "Peripheral,PIO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIOC_OSR,PIOC Controller Output Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Status 31" "Input,Output"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Status 30" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Status 29" "Input,Output"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Status 28" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Status 27" "Input,Output"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Status 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Status 25" "Input,Output"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Status 24" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Status 23" "Input,Output"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Status 22" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Status 21" "Input,Output"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Status 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Status 19" "Input,Output"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Status 18" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Status 17" "Input,Output"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Status 16" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Status 15" "Input,Output"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Status 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Status 13" "Input,Output"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Status 12" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Status 11" "Input,Output"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Status 10" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Status 9" "Input,Output"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Status 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Status 7" "Input,Output"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Status 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Status 5" "Input,Output"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Status 4" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Status 3" "Input,Output"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Status 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Status 1" "Input,Output"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Status 0" "Input,Output"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PIOC_IFSR,PIOC Controller Input Filter Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PIOC_ODSR,PIOC Controller Output Data Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PIOC_PDSR,PIOC Controller Pin Data Status Register"
|
|
bitfld.long 0x0 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x0 30. " P30 ,Output Data Status 30" "Low,High"
|
|
bitfld.long 0x0 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x0 28. " P28 ,Output Data Status 28" "Low,High"
|
|
bitfld.long 0x0 27. " P27 ,Output Data Status 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " P26 ,Output Data Status 26" "Low,High"
|
|
bitfld.long 0x0 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x0 24. " P24 ,Output Data Status 24" "Low,High"
|
|
bitfld.long 0x0 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x0 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x0 20. " P20 ,Output Data Status 20" "Low,High"
|
|
bitfld.long 0x0 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x0 18. " P18 ,Output Data Status 18" "Low,High"
|
|
bitfld.long 0x0 17. " P17 ,Output Data Status 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " P16 ,Output Data Status 16" "Low,High"
|
|
bitfld.long 0x0 15. " P15 ,Output Data Status 15" "Low,High"
|
|
bitfld.long 0x0 14. " P14 ,Output Data Status 14" "Low,High"
|
|
bitfld.long 0x0 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x0 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x0 10. " P10 ,Output Data Status 10" "Low,High"
|
|
bitfld.long 0x0 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x0 8. " P8 ,Output Data Status 8" "Low,High"
|
|
bitfld.long 0x0 7. " P7 ,Output Data Status 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " P6 ,Output Data Status 6" "Low,High"
|
|
bitfld.long 0x0 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x0 4. " P4 ,Output Data Status 4" "Low,High"
|
|
bitfld.long 0x0 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x0 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x0 0. " P0 ,Output Data Status 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIOC_IMR,PIOC Controller Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x0 "PIOC_ISR,PIOC Controller Interrupt Status Register"
|
|
in
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIOC_MDSR,PIOC Multi-driver Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PIOC_PUSR,PIOC Pull Up Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Pull Up Status 31" "Enabled,Disabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Pull Up Status 30" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Pull Up Status 29" "Enabled,Disabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Pull Up Status 28" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Pull Up Status 27" "Enabled,Disabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Pull Up Status 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Pull Up Status 25" "Enabled,Disabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Pull Up Status 24" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Pull Up Status 23" "Enabled,Disabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Pull Up Status 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Pull Up Status 21" "Enabled,Disabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Pull Up Status 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Pull Up Status 19" "Enabled,Disabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Pull Up Status 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Pull Up Status 17" "Enabled,Disabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Pull Up Status 16" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Pull Up Status 15" "Enabled,Disabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Pull Up Status 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Pull Up Status 13" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Pull Up Status 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Pull Up Status 11" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Pull Up Status 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Pull Up Status 9" "Enabled,Disabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Pull Up Status 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Pull Up Status 7" "Enabled,Disabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Pull Up Status 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Pull Up Status 5" "Enabled,Disabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Pull Up Status 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Pull Up Status 3" "Enabled,Disabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Pull Up Status 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Pull Up Status 1" "Enabled,Disabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Pull Up Status 0" "Enabled,Disabled"
|
|
sif (cpuis("AT91CAP9*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "DTXD,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "DRXD,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "PCK0,PWM2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "PWM0,TCLK1"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "LCDD23,ERXCK"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "LCDD22,ECOL"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "LCDD21,ECRS"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "LCDD20,ETXER"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "LCDD19,ERX3"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "LCDD18,ERX2"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "LCDD17,ETX3"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "LCDD16,ETX2"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "LCDD15,LCDD23"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "LCDD14,LCDD22"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "LCDD13,LCDD21"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "LCDD12,LCDD20"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "LCDD11,LCDD19"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "LCDD10,LCDD15"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "LCDD9,LCDD14"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "LCDD8,LCDD13"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "LCDD7,LCDD12"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "LCDD6,LCDD11"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "LCDD5,LCDD10"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "LCDD4,LCDD7"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "LCDD3,LCDD6"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "LCDD2,LCDD5"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "LCDD1,LCDD4"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "LCDD0,LCDD3"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "LCDDEN,PWM1"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "LCDDOTCK,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "LCDHSYNC,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "LCDVSYNC,?..."
|
|
elif (cpu()=="AT91SAM9G10")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,PCK1"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,RF2"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,RK2"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,RD2"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,TD2"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,TK2"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,TF2"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,TIOB2"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,TIOA2"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,TIOB1"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,TIOA1"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,TIOB0"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,TIOA0"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,TCLK1"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,TCLK0"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "RXD2,SPI1_NPCS3"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "TXD2,SPI1_NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "RXD1,NCS7"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "TXD1,NCS6"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "CTS0,FIQ"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "RTS0,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "RXD0,PCK3"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "TXD0,PCK2"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "CFCE2,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "NCS5/CFCS1,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "NCS4/CFCS0,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A25/CFRNW,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "NWAIT,IRQ0"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "NANDWE,NCS7"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "NANDOE,NCS6"
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "D31,?..."
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "D30,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "D29,?..."
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "D28,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "D27,?..."
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "D26,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "D25,?..."
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "D24,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "D23,?..."
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "D22,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "D21,?..."
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "D20,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "D19,?..."
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "D18,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "D17,?..."
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "D16,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "NWAIT,?..."
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "NCS3/NANDCS,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "NCS2,?..."
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A25/CFRNW,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "NCS5/CFCS1,CTS2"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "NCS4/CFCS0,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "CFCE2,RTS2"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "CFCE1,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A24,?..."
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A23,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A22/NANDCLE,?..."
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A21/NANDALE,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A20,?..."
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A19,?..."
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "DQM3,?..."
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "DQM2,?..."
|
|
else
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PIOC_ABSR,PIOC Peripheral A B Status Register"
|
|
setclrfld.long 0x0 31. -0x4 31. -0x8 31. " P31_set/clr ,Peripheral A B Status 31" "A,B"
|
|
setclrfld.long 0x0 30. -0x4 30. -0x8 30. " P30_set/clr ,Peripheral A B Status 30" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x4 29. -0x8 29. " P29_set/clr ,Peripheral A B Status 29" "A,B"
|
|
setclrfld.long 0x0 28. -0x4 28. -0x8 28. " P28_set/clr ,Peripheral A B Status 28" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x4 27. -0x8 27. " P27_set/clr ,Peripheral A B Status 27" "A,B"
|
|
setclrfld.long 0x0 26. -0x4 26. -0x8 26. " P26_set/clr ,Peripheral A B Status 26" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x4 25. -0x8 25. " P25_set/clr ,Peripheral A B Status 25" "A,B"
|
|
setclrfld.long 0x0 24. -0x4 24. -0x8 24. " P24_set/clr ,Peripheral A B Status 24" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x4 23. -0x8 23. " P23_set/clr ,Peripheral A B Status 23" "A,B"
|
|
setclrfld.long 0x0 22. -0x4 22. -0x8 22. " P22_set/clr ,Peripheral A B Status 22" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x4 21. -0x8 21. " P21_set/clr ,Peripheral A B Status 21" "A,B"
|
|
setclrfld.long 0x0 20. -0x4 20. -0x8 20. " P20_set/clr ,Peripheral A B Status 20" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x4 19. -0x8 19. " P19_set/clr ,Peripheral A B Status 19" "A,B"
|
|
setclrfld.long 0x0 18. -0x4 18. -0x8 18. " P18_set/clr ,Peripheral A B Status 18" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x4 17. -0x8 17. " P17_set/clr ,Peripheral A B Status 17" "A,B"
|
|
setclrfld.long 0x0 16. -0x4 16. -0x8 16. " P16_set/clr ,Peripheral A B Status 16" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x4 15. -0x8 15. " P15_set/clr ,Peripheral A B Status 15" "A,B"
|
|
setclrfld.long 0x0 14. -0x4 14. -0x8 14. " P14_set/clr ,Peripheral A B Status 14" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x4 13. -0x8 13. " P13_set/clr ,Peripheral A B Status 13" "A,B"
|
|
setclrfld.long 0x0 12. -0x4 12. -0x8 12. " P12_set/clr ,Peripheral A B Status 12" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x4 11. -0x8 11. " P11_set/clr ,Peripheral A B Status 11" "A,B"
|
|
setclrfld.long 0x0 10. -0x4 10. -0x8 10. " P10_set/clr ,Peripheral A B Status 10" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x4 9. -0x8 9. " P9_set/clr ,Peripheral A B Status 9" "A,B"
|
|
setclrfld.long 0x0 8. -0x4 8. -0x8 8. " P8_set/clr ,Peripheral A B Status 8" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x4 7. -0x8 7. " P7_set/clr ,Peripheral A B Status 7" "A,B"
|
|
setclrfld.long 0x0 6. -0x4 6. -0x8 6. " P6_set/clr ,Peripheral A B Status 6" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x4 5. -0x8 5. " P5_set/clr ,Peripheral A B Status 5" "A,B"
|
|
setclrfld.long 0x0 4. -0x4 4. -0x8 4. " P4_set/clr ,Peripheral A B Status 4" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x4 3. -0x8 3. " P3_set/clr ,Peripheral A B Status 3" "A,B"
|
|
setclrfld.long 0x0 2. -0x4 2. -0x8 2. " P2_set/clr ,Peripheral A B Status 2" "A,B"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x4 1. -0x8 1. " P1_set/clr ,Peripheral A B Status 1" "A,B"
|
|
setclrfld.long 0x0 0. -0x4 0. -0x8 0. " P0_set/clr ,Peripheral A B Status 0" "A,B"
|
|
endif
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PIOC_OWSR,PIOC Output Write Status Register"
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " P31_set/clr ,Output Write Status 31" "Not affected,Affected"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " P30_set/clr ,Output Write Status 30" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " P29_set/clr ,Output Write Status 29" "Not affected,Affected"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " P28_set/clr ,Output Write Status 28" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " P27_set/clr ,Output Write Status 27" "Not affected,Affected"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " P26_set/clr ,Output Write Status 26" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " P25_set/clr ,Output Write Status 25" "Not affected,Affected"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " P24_set/clr ,Output Write Status 24" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " P23_set/clr ,Output Write Status 23" "Not affected,Affected"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " P22_set/clr ,Output Write Status 22" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " P21_set/clr ,Output Write Status 21" "Not affected,Affected"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " P20_set/clr ,Output Write Status 20" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " P19_set/clr ,Output Write Status 19" "Not affected,Affected"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " P18_set/clr ,Output Write Status 18" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " P17_set/clr ,Output Write Status 17" "Not affected,Affected"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " P16_set/clr ,Output Write Status 16" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " P15_set/clr ,Output Write Status 15" "Not affected,Affected"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " P14_set/clr ,Output Write Status 14" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " P13_set/clr ,Output Write Status 13" "Not affected,Affected"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " P12_set/clr ,Output Write Status 12" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " P11_set/clr ,Output Write Status 11" "Not affected,Affected"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " P10_set/clr ,Output Write Status 10" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " P9_set/clr ,Output Write Status 9" "Not affected,Affected"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " P8_set/clr ,Output Write Status 8" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " P7_set/clr ,Output Write Status 7" "Not affected,Affected"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " P6_set/clr ,Output Write Status 6" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " P5_set/clr ,Output Write Status 5" "Not affected,Affected"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " P4_set/clr ,Output Write Status 4" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " P3_set/clr ,Output Write Status 3" "Not affected,Affected"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " P2_set/clr ,Output Write Status 2" "Not affected,Affected"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " P1_set/clr ,Output Write Status 1" "Not affected,Affected"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " P0_set/clr ,Output Write Status 0" "Not affected,Affected"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc0++0xf
|
|
line.long 0x0 "PIO_DELAY0,PIO I/O Delay Register 0"
|
|
bitfld.long 0x0 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "PIO_DELAY1,PIO I/O Delay Register 1"
|
|
bitfld.long 0x4 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "PIO_DELAY2,PIO I/O Delay Register 2"
|
|
bitfld.long 0x8 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "PIO_DELAY3,PIO I/O Delay Register 3"
|
|
bitfld.long 0xC 28.--31. " DELAY7 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 24.--27. " DELAY6 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 20.--23. " DELAY5 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 16.--19. " DELAY4 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " DELAY3 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " DELAY2 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 4.--7. " DELAY1 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 0.--3. " DELAY0 ,Number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffa4000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa4000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa4000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffa4000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa4000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa4000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xf0000000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0000000+0x4)))&0x1)==0x1)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0000000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:(0xf0000000+0x04)))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0000000+0x4)))&0x1)==0x1)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0000000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0000000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
if ((((data.long(ad:(0xf0000000+0x4)))&0x04)==0x00)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:(0xf0000000+0x4)))&0x04)==0x04)&&(((d.l(ad:(0xf0000000+0x4)))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " SPIWPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
else
|
|
base ad:0xfffc8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI0_CR,SPI0 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffc8000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffc8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_MR,SPI0 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffc8000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI0_RDR,SPI0 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffc8000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffc8000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffc8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI0_TDR,SPI0 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI0_SR,SPI0 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI0_IMR,SPI0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI0 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_SPI0"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffa4000
|
|
else
|
|
base ad:0xfffc8000
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI0_RPR,Serial Peripheral Interface 0 Receive Pointer Register"
|
|
line.long 0x04 "SPI0_RCR,Serial Peripheral Interface 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI0_TPR,Serial Peripheral Interface 0 Transmit Pointer Register"
|
|
line.long 0x0c "SPI0_TCR,Serial Peripheral Interface 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI0_RNPR,Serial Peripheral Interface 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI0_RNCR,Serial Peripheral Interface 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI0_TNPR,Serial Peripheral Interface 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI0_TNCR,Serial Peripheral Interface 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI0_PTCR,Serial Peripheral Interface 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI0_PTSR,Serial Peripheral Interface 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "SPI1"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffa8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffa8000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffa8000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffa8000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffa8000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffa8000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xf0004000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0004000+0x4)))&0x1)==0x1)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0004000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x00)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:(0xf0004000+0x04)))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0004000+0x4)))&0x1)==0x1)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0004000+0x4)))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:(0xf0004000+0x04)))&0x04)==0x04)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
if ((((data.long(ad:(0xf0004000+0x4)))&0x04)==0x00)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:(0xf0004000+0x4)))&0x04)==0x04)&&(((d.l(ad:(0xf0004000+0x4)))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " SPIWPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
else
|
|
base ad:0xfffcc000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI1_CR,SPI1 Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long(ad:0xfffcc000+0x04))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x1)==0x1))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif ((((data.long(ad:0xfffcc000+0x04))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_MR,SPI1 Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "No effect,Waiting"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Direct,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Select" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:(ad:0xfffcc000+0x4))&0x1)==0x1)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SPI1_RDR,SPI1 Receive Data Register"
|
|
in
|
|
endif
|
|
if ((((data.long(ad:0xfffcc000+0x4))&0x04)==0x00)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=0111,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,NPCS[3:0]=1011,NPCS[3:0]=1110,NPCS[3:0]=1101,NPCS[3:0]=1110,Forbidden"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif ((((data.long(ad:0xfffcc000+0x4))&0x04)==0x04)&&(((d.l(ad:0xfffcc000+0x4))&0x2)==0x2))
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Last"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "PCS0,PCS1,PCS2,PCS3,PCS4,PCS5,PCS6,PCS7,PCS8,PCS9,PCS10,PCS11,PCS12,PCS13,PCS14,PCS15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "SPI1_TDR,SPI1 Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI1_SR,SPI1 Status Register"
|
|
in
|
|
group.long 0x14++0xB
|
|
line.long 0x8 "SPI1_IMR,SPI1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x8 10. 0x0 10. 0x4 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 9. 0x0 9. 0x4 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 8. 0x0 8. 0x4 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9M11"&&cpu()!="AT91SAM9G45"&&cpu()!="AT91SAM9M10"&&cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9X25"&&cpu()!="AT91SAM9X35")
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " OVRES_set/clr ,Overrun Error Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " MODF_set/clr ,Mode Fault Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " TDRE_set/clr ,SPI1 Transmit Data Register Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " RDRF_set/clr ,Receive Data Register Full Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x30++0x0F
|
|
line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x4 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x8 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High"
|
|
line.long 0xC "SPI_CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0xC 2. " CSNAAT , Chip Select Not Active After Transfer" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR, SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY , Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN , Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "SPI_WPSR, SPI Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_SPI1"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffa8000
|
|
else
|
|
base ad:0xfffcc000
|
|
endif
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SPI1_RPR,Serial Peripheral Interface 1 Receive Pointer Register"
|
|
line.long 0x04 "SPI1_RCR,Serial Peripheral Interface 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI1_TPR,Serial Peripheral Interface 1 Transmit Pointer Register"
|
|
line.long 0x0c "SPI1_TCR,Serial Peripheral Interface 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI1_RNPR,Serial Peripheral Interface 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SPI1_RNCR,Serial Peripheral Interface 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI1_TNPR,Serial Peripheral Interface 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI1_TNCR,Serial Peripheral Interface 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI1_PTCR,Serial Peripheral Interface 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI1_PTSR,Serial Peripheral Interface 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC Channel 0"
|
|
base ad:0xF8008000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF8008000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
if (data.long(ad:0xF8008000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
base ad:0xF8008040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF8008040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
if (data.long(ad:0xF8008040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
base ad:0xF8008080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF8008080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
if (data.long(ad:0xF8008080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC0/TC1/TC2)"
|
|
base ad:0xF80080C0
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
base ad:0xF800C000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF800C000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
if (data.long(ad:0xF800C000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
base ad:0xF800C040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF800C040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
if (data.long(ad:0xF800C040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
base ad:0xF800C080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Triggere"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xF800C080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
if (data.long(ad:0xF800C080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x8 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC3/TC4/TC5)"
|
|
base ad:0xF800C0C0
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0xF8034000
|
|
width 0x9
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0xc++3
|
|
line.long 0x0 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM Output for Channel 3 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM Output for Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM Output for Channel 1 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM Output for Channel 0 Enable" "Disabled,Enabled"
|
|
group.long 0x18++3
|
|
line.long 0x0 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Enable Interrupt for PWM Channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Enable Interrupt for PWM Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Enable Interrupt for PWM Channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,Enable Interrupt for PWM Channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PWM_ISR,PWM Interrupt Status Register"
|
|
in
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree "Channel 0 Registers"
|
|
group.long (0x200+(0*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR0,PWM Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
rgroup.long (0x20C+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
wgroup.long (0x210+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel 0 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 1 Registers"
|
|
group.long (0x200+(1*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR1,PWM Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
rgroup.long (0x20C+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
wgroup.long (0x210+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel 1 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 2 Registers"
|
|
group.long (0x200+(2*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR2,PWM Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
rgroup.long (0x20C+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
wgroup.long (0x210+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel 2 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 3 Registers"
|
|
group.long (0x200+(3*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR3,PWM Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
rgroup.long (0x20C+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
wgroup.long (0x210+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel 3 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI 1"
|
|
base ad:0xfff84000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xfff84000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xfff84000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff84000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff84000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xfff84000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "TWI 2"
|
|
base ad:0xfff88000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xfff88000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xfff88000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff88000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfff88000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xfff88000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI 0"
|
|
base ad:0xF8010000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xF8010000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xF8010000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8010000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8010000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xF8010000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "TWI 1"
|
|
base ad:0xF8014000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xF8014000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xF8014000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8014000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8014000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xF8014000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "TWI 2"
|
|
base ad:0xF8018000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xF8018000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xF8018000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8018000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xF8018000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xF8018000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "TWI (Two-wire Interface)"
|
|
base ad:0xfffac000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif (cpu()=="AT91SAM9M11"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Send"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9N12")
|
|
if ((d.l(ad:0xfffac000+0x00)&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TWI_SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
if (((d.l(ad:0xfffac000+0x4))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfffac000+0x4))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l(ad:0xfffac000+0x4))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
if ((d.l(ad:0xfffac000+0x00)&0x4)==0x4)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
else
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Master or Slave Receive Holding Data"
|
|
else
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
width 18.
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TWI_WPROT_MODE, TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE , Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT , Write protection bit" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "TWI_WPROT_STATUS, TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPROTADDR , Write Protection Error Address"
|
|
bitfld.long 0x00 0. " WPROTERR , Write Protection Error" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G46")
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xfffcc000
|
|
width 0x10
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "TRNG_CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 100. " KEY ,Key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disables,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TRNG_IMR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "TRNG_ISR,TRNG Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "TRNG_ODATA ,TRNG Output Data Register"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.open "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
tree "USART0"
|
|
base ad:0xfffb0000
|
|
sif (cpu()=="AT91SAM9G10")
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb0000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US0_IER,USART0 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb0000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb0000
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45")
|
|
base ad:0xfff8c000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff8c000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Aborted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,Released"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,Forced"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,RTS=0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
if (((d.l(ad:(0xfff8c000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff8c000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff8c000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff8c000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff8c000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff8c000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff8c000+0x04))&0xE)==0xE)||((d.l(ad:(0xfff8c000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
if (((d.l(ad:(0xfff8c000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration or SPI Underrun Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US0_MAN,USART0xfff8c000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((0==3)&&((d.l(ad:0xfff8c000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((0==3)&&((d.l(ad:0xfff8c000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
base ad:0xfff8c000
|
|
width 0xa
|
|
if ((((d.l(ad:0xfff8c000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff8c000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xfff8c000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff8c000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff8c000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff8c000+0x4))&0xE)==0x4||((d.l(ad:0xfff8c000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xfff8c000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff8c000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff8c000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff8c000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff8c000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff8c000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff8c000+0x04))&0xE)==0xE)||((d.l((ad:0xfff8c000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US0_MAN,USARTad:0xfff8c000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xF801C000
|
|
width 0xa
|
|
if ((((d.l(ad:0xF801C000+0x4))&0xE)==0xE)&&((d.l(ad:0xF801C000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xF801C000+0x4))&0xE)==0xE)&&((d.l(ad:0xF801C000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF801C000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF801C000+0x4))&0xE)==0x4||((d.l(ad:0xF801C000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xF801C000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF801C000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF801C000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF801C000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF801C000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF801C000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF801C000+0x04))&0xE)==0xE)||((d.l((ad:0xF801C000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US0_MAN,USARTad:0xF801C000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb0000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffb0000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb0000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_USART0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART0_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "USART1"
|
|
base ad:0xfffb4000
|
|
sif (cpu()=="AT91SAM9G10")
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb4000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US1_IER,USART1 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb4000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb4000
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45")
|
|
base ad:0xfff90000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff90000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Aborted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,Released"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,Forced"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,RTS=0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
if (((d.l(ad:(0xfff90000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff90000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff90000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff90000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff90000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff90000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff90000+0x04))&0xE)==0xE)||((d.l(ad:(0xfff90000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
if (((d.l(ad:(0xfff90000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration or SPI Underrun Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US1_MAN,USART0xfff90000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((1==3)&&((d.l(ad:0xfff90000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((1==3)&&((d.l(ad:0xfff90000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
base ad:0xfff90000
|
|
width 0xa
|
|
if ((((d.l(ad:0xfff90000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff90000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xfff90000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff90000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff90000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff90000+0x4))&0xE)==0x4||((d.l(ad:0xfff90000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xfff90000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff90000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff90000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff90000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff90000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff90000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff90000+0x04))&0xE)==0xE)||((d.l((ad:0xfff90000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US1_MAN,USARTad:0xfff90000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xF8020000
|
|
width 0xa
|
|
if ((((d.l(ad:0xF8020000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8020000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xF8020000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8020000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8020000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8020000+0x4))&0xE)==0x4||((d.l(ad:0xF8020000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xF8020000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8020000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8020000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8020000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8020000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8020000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8020000+0x04))&0xE)==0xE)||((d.l((ad:0xF8020000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US1_MAN,USARTad:0xF8020000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb4000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffb4000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb4000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_USART1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART1_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "USART2"
|
|
base ad:0xfffb8000
|
|
sif (cpu()=="AT91SAM9G10")
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512")
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb8000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC , Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN , Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 22. " VAR_SYNC , Variable Synchronization of Command/Data Sync Start Frame Delimiter" "User defined,US_THR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9261")
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "US2_IER,USART2 Interrupt Enable Register"
|
|
bitfld.long 0x00 20. " MANE ,Manchester Error Interrupt Enable" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64")
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
sif (cpu()=="AT91SAM9260"||cpu()=="AT91SAM9263"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9G10")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift compensation" "Not recover,Recover"
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0to1,1to0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0=0-to-1,1=0-to-1"
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 x bit period,2 x bit period,3 x bit period,4 x bit period,5 x bit period,6 x bit period,7 x bit period,8 x bit period,9 x bit period,10 x bit period,11 x bit period,12 x bit period,13 x bit period,14 x bit period,15 x bit period"
|
|
endif
|
|
if (((data.long(ad:(0xfffb8000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb8000
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45")
|
|
base ad:0xfff94000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff94000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Aborted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,Released"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,Forced"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,RTS=0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
if (((d.l(ad:(0xfff94000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff94000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff94000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff94000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff94000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff94000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff94000+0x04))&0xE)==0xE)||((d.l(ad:(0xfff94000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
if (((d.l(ad:(0xfff94000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration or SPI Underrun Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US2_MAN,USART0xfff94000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((2==3)&&((d.l(ad:0xfff94000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((2==3)&&((d.l(ad:0xfff94000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
base ad:0xfff94000
|
|
width 0xa
|
|
if ((((d.l(ad:0xfff94000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff94000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xfff94000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff94000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff94000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff94000+0x4))&0xE)==0x4||((d.l(ad:0xfff94000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xfff94000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff94000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff94000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff94000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff94000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff94000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff94000+0x04))&0xE)==0xE)||((d.l((ad:0xfff94000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US2_MAN,USARTad:0xfff94000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xF8024000
|
|
width 0xa
|
|
if ((((d.l(ad:0xF8024000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8024000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xF8024000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8024000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8024000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8024000+0x4))&0xE)==0x4||((d.l(ad:0xF8024000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xF8024000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8024000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8024000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8024000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8024000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8024000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8024000+0x04))&0xE)==0xE)||((d.l((ad:0xF8024000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US2_MAN,USARTad:0xF8024000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffb8000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffb8000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffb8000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_USART2"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART2_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Pointer Register"
|
|
line.long 0x04 "USART2_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART2_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Pointer Register"
|
|
line.long 0x0c "USART2_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART2_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Pointer Register"
|
|
line.long 0x14 "USART2_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART2_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART2_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART2_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART2_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 2 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif ((cpu()=="AT91SAM9G20")||(cpu()=="AT91SAM9G25")||(cpu()=="AT91SAM9G45")||(cpu()=="AT91SAM9G46"))
|
|
tree "USART3"
|
|
sif (cpu()=="AT91SAM9G45")
|
|
base ad:0xfff98000
|
|
width 0xa
|
|
if ((d.l(ad:0xfff98000+0x04)&0xE)==0xE)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Aborted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,Released"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,Forced"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 19. " RTSDIS/RCS ,Request to Send Disable/Release SPI Chip Select" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN/FCS ,Request to Send Enable/Force SPI Chip Select" "No effect,RTS=0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
if (((d.l(ad:(0xfff98000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff98000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff98000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff98000+0x04))&0xE)!=0xE)&&((d.l(ad:(0xfff98000+0x04))&0xF)!=0xF)&&((d.l(ad:(0xfff98000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l(ad:(0xfff98000+0x04))&0xE)==0xE)||((d.l(ad:(0xfff98000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF/CPOL ,Bit Order or SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC/CPHA ,Synchronous Mode Select or SPI Clock Phase" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 Protocol T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
if (((d.l(ad:(0xfff98000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9M11")
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration or SPI Underrun Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M10")
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
sif (cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9G45")
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US0_MAN,USART0xfff98000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
if ((0==3)&&((d.l(ad:0xfff98000+0x04)&0xA)==0xA))
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC, Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
line.long 0x04 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
elif ((0==3)&&((d.l(ad:0xfff98000+0x04)&0xA)!=0xA))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Identifier Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. 1. " DLC , Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,Bits 5 and 6"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0-Enhanced,LIN 1.3-Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G46")
|
|
base ad:0xfff98000
|
|
width 0xa
|
|
if ((((d.l(ad:0xfff98000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff98000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xfff98000+0x4))&0xE)==0xE)&&((d.l(ad:0xfff98000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff98000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xfff98000+0x4))&0xE)==0x4||((d.l(ad:0xfff98000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xfff98000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff98000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff98000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff98000+0x04))&0xE)!=0xE)&&((d.l((ad:0xfff98000+0x04))&0xF)!=0xF)&&((d.l((ad:0xfff98000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xfff98000+0x04))&0xE)==0xE)||((d.l((ad:0xfff98000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US3_IMR,USART3 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US3_CSR,USART3 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US3_RHR,USART3 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US3_THR,USART3 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US3_BRGR,USART3 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US3_RTOR,USART3 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US3_TTGR,USART3 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US3_FIDI,USART3 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US3_NER,USART3 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US3_IF,USART3 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US3_MAN,USARTad:0xfff98000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Mode Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FDIS ,Frame Slot Mode Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Defined by DLC,Defined by 5 & 6 bits IDCHR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0 Enhanced,LIN 1.3 Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "Computed/Sent & Checked,Not Computed/Sent & Not checked"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "Computed/Sent & Checked,Not Computed/Sent & Not checked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
if (((d.l(ad:0xfff98000+0x4))&0xA)==0xA)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G25")
|
|
base ad:0xF8028000
|
|
width 0xa
|
|
if ((((d.l(ad:0xF8028000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8028000+0x4))&0xE00)!=0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((((d.l(ad:0xF8028000+0x4))&0xE)==0xE)&&((d.l(ad:0xF8028000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8028000+0x4))&0xE00)==0xE00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif (((d.l(ad:0xF8028000+0x4))&0xE)==0x4||((d.l(ad:0xF8028000+0x4))&0xE)==0x6)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US3_CR,USART3 Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Abort LIN Transmission" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Send LIN Wakeup Signal" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if (((d.l((ad:0xF8028000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8028000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8028000+0x04))&0x100)!=0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8028000+0x04))&0xE)!=0xE)&&((d.l((ad:0xF8028000+0x04))&0xF)!=0xF)&&((d.l((ad:0xF8028000+0x04))&0x100)==0x100))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
elif (((d.l((ad:0xF8028000+0x04))&0xE)==0xE)||((d.l((ad:0xF8028000+0x04))&0xF)==0xF))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US3_MR,USART3 Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CLKO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Reserved,Multidrop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase" "Data Changed,Data Captured"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Reserved,IS07816 T = 0,Reserved,IS07816 T = 1,Reserved,IrDA,Reserved,LIN Master,LIN Slave,Reserved,Reserved,SPI Master,SPI Slave"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US3_IMR,USART3 Interrupt Mask Register"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mas" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask Err" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK/LINBK_set/clr ,Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Iteration/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46")
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "US3_CSR,USART3 Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "US3_RHR,USART3 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US3_THR,USART3 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US3_BRGR,USART3 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US3_RTOR,USART3 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US3_TTGR,USART3 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US3_FIDI,USART3 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US3_NER,USART3 Number of Errors Register"
|
|
in
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US3_IF,USART3 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US3_MAN,USARTad:0xF8028000 Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART3 LIN Mode Register"
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
bitfld.long 0x00 6. " FDIS ,Frame Slot Mode Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Defined by DLC,Defined by 5 & 6 bits IDCHR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "LIN 2.0 Enhanced,LIN 1.3 Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "Computed/Sent & Checked,Not Computed/Sent & Not checked"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "Computed/Sent & Checked,Not Computed/Sent & Not checked"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
if (((d.l(ad:0xF8028000+0x4))&0xA)==0xA)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART3 LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
sif (cpu()!="AT91SAM9G46")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffd0000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd0000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US0_CSR,USART0 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US0_RHR,USART0 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US0_THR,USART0 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US0_RTOR,USART0 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US0_FIDI,USART0 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US0_NER,USART0 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffd0000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US0_IF,USART0 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd0000
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G25")
|
|
tree "PDC_USART3"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART3_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Pointer Register"
|
|
line.long 0x04 "USART3_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART3_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Pointer Register"
|
|
line.long 0x0c "USART3_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART3_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Pointer Register"
|
|
line.long 0x14 "USART3_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART3_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART3_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART3_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART3_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 3 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G20")
|
|
tree "USART4"
|
|
base ad:0xfffd4000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd4000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US1_CSR,USART1 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US1_RHR,USART1 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US1_THR,USART1 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US1_RTOR,USART1 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US1_FIDI,USART1 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US1_NER,USART1 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffd4000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US1_IF,USART1 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd4000
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART4"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART4_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Pointer Register"
|
|
line.long 0x04 "USART4_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART4_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Pointer Register"
|
|
line.long 0x0c "USART4_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART4_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Next Pointer Register"
|
|
line.long 0x14 "USART4_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART4_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART4_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART4_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART4_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 4 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART5"
|
|
base ad:0xfffd8000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US2_CR,USART2 Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,DTR=1"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,DTR=0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restarted"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Started"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Started"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
if (((d.l(ad:(0xfffd8000+0x4)))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,Reserved,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US2_MR,USART2 Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Number of Iterations" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "CHRL,9-bit"
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1 bit,1.5 bits,2 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,ISO7816 T = 0,Reserved,ISO7816 T = 1,Reserved,IrDA,?..."
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "US2_IMR,USART2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " CTSIC_Clear/Set ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " DCDIC_Clear/Set ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " DSRIC_Clear/Set ,Data Set Ready Input Change Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " RIIC_Clear/Set ,Ring Indicator Input Change Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " NACK_Clear/Set ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RXBUFF_Clear/Set ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " TXBUFE_Clear/Set ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ITERATION_Clear/Set ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_Clear/Set ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " TIMEOUT_Clear/Set ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_Clear/Set ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_Clear/Set ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_Clear/Set ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " ENDTX_Clear/Set ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " ENDRX_Clear/Set ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RXBRK_Clear/Set ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_Clear/Set ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_Clear/Set ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x7
|
|
hide.long 0x0 "US2_CSR,USART2 Channel Status Register"
|
|
in
|
|
hide.long 0x4 "US2_RHR,USART2 Receive Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US2_THR,USART2 Transmit Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0xb
|
|
line.long 0x00 "US2_BRGR,USART2 Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US2_RTOR,USART2 Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "US2_TTGR,USART2 Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US2_FIDI,USART2 FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US2_NER,USART2 Number of Errors Register"
|
|
in
|
|
if (((data.long(ad:(0xfffd8000+0x04)))&0xf)==0x8)
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "US2_IF,USART2 IrDA Filter Register"
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
base ad:0xfffd8000
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_USART5"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "USART5_RPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Pointer Register"
|
|
line.long 0x04 "USART5_RCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART5_TPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Pointer Register"
|
|
line.long 0x0c "USART5_TCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART5_RNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Next Pointer Register"
|
|
line.long 0x14 "USART5_RNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART5_TNPR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Next Pointer Register"
|
|
line.long 0x1c "USART5_TNCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART5_PTCR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART5_PTSR,Universal Synchronous/Asynchronous Receiver/Transmitter 5 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
tree.open "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART 0"
|
|
base ad:0xF8040000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART0_CR,USART0 Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART0_MR,USART0 Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "UART0_IMR,USART0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "UART0_SR,UART0 Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9N12")
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x00 "UART0_RHR,UART0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "UART0_RHR,UART0 Receive Holding Register"
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 15. " RXSYNH ,Received Sync" "Data,Command"
|
|
endif
|
|
hexmask.long.word 0x00 0.--8. 1. " RXCHR ,Received Character"
|
|
endif
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "UART0_THR,UART0 Transmit Holding Register"
|
|
sif (cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
endif
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "UART0_BRGR,UART0 Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0xF8044000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART1_CR,USART1 Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART1_MR,USART1 Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "UART1_IMR,USART1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "UART1_SR,UART1 Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9N12")
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x00 "UART1_RHR,UART1 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "UART1_RHR,UART1 Receive Holding Register"
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 15. " RXSYNH ,Received Sync" "Data,Command"
|
|
endif
|
|
hexmask.long.word 0x00 0.--8. 1. " RXCHR ,Received Character"
|
|
endif
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "UART1_THR,UART1 Transmit Holding Register"
|
|
sif (cpu()!="AT91SAM9N12"&&cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
endif
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "UART1_BRGR,UART1 Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "ADC (Analog-to-digital Converter)"
|
|
base ad:0xF804C000
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
sif (cpu()!="AT91SAM9G25")
|
|
bitfld.long 0x00 2. " TSCALIB ,Touchscreen Calibration" "No effect,Calibration"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,Use Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "SUT0,SUT8,SUT16,SUT24,SUT64,SUT80,SUT96,SUT112,SUT512,SUT576,SUT704,SUT768,SUT832,SUT896,SUT960,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FWUP ,Fast Wake Up" "Off,On"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
if ((d.l(ad:0xF804C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH8 ,User Sequence Number 8" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x00 24.--27. " USCH7 ,User Sequence Number 7" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " USCH6 ,User Sequence Number 6" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x00 16.--19. " USCH5 ,User Sequence Number 5" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " USCH4 ,User Sequence Number 4" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x00 8.--11. " USCH3 ,User Sequence Number 3" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " USCH2 ,User Sequence Number 2" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x00 0.--3. " USCH1 ,User Sequence Number 1" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
line.long 0x04 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
bitfld.long 0x04 28.--31. " USCH16 ,User Sequence Number 8" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x04 24.--27. " USCH15 ,User Sequence Number 7" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20.--23. " USCH14 ,User Sequence Number 6" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x04 16.--19. " USCH13 ,User Sequence Number 5" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " USCH12 ,User Sequence Number 4" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x04 8.--11. " USCH11 ,User Sequence Number 3" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " USCH10 ,User Sequence Number 2" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x04 0.--3. " USCH9 ,User Sequence Number 1" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
else
|
|
hgroup.long 0x08++0x07
|
|
hide.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
hide.long 0x04 "ADC_SEQR1,ADC Channel Sequence 2 Register"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CH11_set/clr ,Channel 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CH10_set/clr ,Channel 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CH9_set/clr ,Channel 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CH8_set/clr ,Channel 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "ADC_LCDR,ADC Last Converted Data Register"
|
|
bitfld.long 0x00 12.--15. " CHNB ,Channel Number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " LDATA ,Last Data Converted"
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
sif (cpu()!="AT91SAM9G25"||cpu()!="AT91SAM9X25")
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " NOPEN_set/clr ,No Pen Contact Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " PEN_set/clr ,Pen Contact Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE_set/clr ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE_set/clr ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9X25")
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " PRDY_set/clr ,Touchscreen Measure Pressure Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " YRDY_set/clr ,Touchscreen Measure YPOS Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " XRDY_set/clr ,Touchscreen Measure XPOS Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOC11_set/clr ,Conversion End Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " EOC10_set/clr ,Conversion End Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " EOC9_set/clr ,Conversion End Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " EOC8_set/clr ,Conversion End Interrupt Mask 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7_set/clr ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6_set/clr ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5_set/clr ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4_set/clr ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3_set/clr ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2_set/clr ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1_set/clr ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0_set/clr ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "ADC_ISR,ADC Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "ADC_OVER,ADC Overrun Status Register"
|
|
bitfld.long 0x00 11. " OVRE11 ,Overrun Error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " OVRE10 ,Overrun Error 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OVRE9 ,Overrun Error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " OVRE8 ,Overrun Error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OVRE7 ,Overrun Error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " OVRE6 ,Overrun Error 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRE5 ,Overrun Error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " OVRE4 ,Overrun Error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OVRE3 ,Overrun Error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " OVRE2 ,Overrun Error 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE1 ,Overrun Error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " OVRE0 ,Overrun Error 0" "No error,Error"
|
|
if ((d.l(ad:0xF804C000+0x40)&0x200)==0x200)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LDCR register" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 12.--13. " CMPFILTER , Compare Event Filtering" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Not compared,Compared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LDCR register" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 12.--13. " CMPFILTER , Compare Event Filtering" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Not compared,Compared"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWTHRES ,LOW Threshold"
|
|
group.long 0x50++0x2F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel Data Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel Data Register"
|
|
hexmask.long.word 0x8 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel Data Register"
|
|
hexmask.long.word 0xC 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel Data Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel Data Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel Data Register"
|
|
hexmask.long.word 0x18 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel Data Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel Data Register"
|
|
hexmask.long.word 0x20 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel Data Register"
|
|
hexmask.long.word 0x24 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x28 "ADC_CDR10,ADC Channel Data Register"
|
|
hexmask.long.word 0x28 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x2C "ADC_CDR11,ADC Channel Data Register"
|
|
hexmask.long.word 0x2C 0.--11. 1. " DATA ,Converted Data"
|
|
sif (cpu()!="AT91SAM9X25")
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 0.--1. " PENDETSENS ,Pen Detection Sensitivity" "0,1,2,3"
|
|
endif
|
|
sif (cpu()!="AT91SAM9G25")&&(cpu()!="AT91SAM9X25")
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC_TSMR,ADC Touchscreen Mode Register"
|
|
bitfld.long 0x00 28.--31. " PENDBC ,Pen Detect Debouncing Period" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16348,32768"
|
|
bitfld.long 0x00 24. " PENDET ,Pen Contact Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " NOTSDMA ,No TouchScreen DMA - XPOS YPOS Z1 Z2 are transmitted in ADC_LCDR" "Transmitted,Never transmitted"
|
|
bitfld.long 0x00 16.--19. " TSSCTIM ,Touchscreen Switches Closure Time" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TSFREQ ,Touchscreen Frequency" "Trigger Frequency/1,Trigger Frequency/2,Trigger Frequency/4,Trigger Frequency/8,Trigger Frequency/16,Trigger Frequency/32,Trigger Frequency/64,Trigger Frequency/128,Trigger Frequency/256,Trigger Frequency/512,Trigger Frequency/1024,Trigger Frequency/2048,Trigger Frequency/4096,Trigger Frequency/8192,Trigger Frequency/16348,Trigger Frequency/32768"
|
|
bitfld.long 0x00 4.--5. " TSAV ,Touchscreen Average" "NO_FILTER,AVG2CONV,AVG4CONV,AVG8CONV"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TSMODE ,Touchscreen Mode" "NONE,4_WIRE_NO_PM,4_WIRE,5_WIRE"
|
|
rgroup.long 0xB4++0x0B
|
|
line.long 0x00 "ADC_XPOSR,ADC Touchscreen X Position Register"
|
|
sif (cpu()=="AT91SAM9X35")
|
|
hexmask.long.word 0x00 16.--27. 1. " XSCALE ,Scale of XPOS"
|
|
hexmask.long.word 0x00 0.--11. 1. " XPOS ,X Position"
|
|
else
|
|
hexmask.long.word 0x00 16.--25. 1. " XSCALE ,Scale of XPOS"
|
|
hexmask.long.word 0x00 0.--9. 1. " XPOS ,X Position"
|
|
endif
|
|
line.long 0x04 "ADC_YPOSR,ADC Touchscreen Y Position Register"
|
|
sif (cpu()=="AT91SAM9X35")
|
|
hexmask.long.word 0x04 16.--27. 1. " YSCALE ,Scale of YPOS"
|
|
hexmask.long.word 0x04 0.--11. 1. " YPOS ,Y Position"
|
|
else
|
|
hexmask.long.word 0x04 16.--25. 1. " YSCALE ,Scale of YPOS"
|
|
hexmask.long.word 0x04 0.--9. 1. " YPOS ,Y Position"
|
|
endif
|
|
line.long 0x08 "ADC_PRESSR,ADC Touchscreen Pressure Register"
|
|
sif (cpu()=="AT91SAM9X35")
|
|
hexmask.long.word 0x08 16.--27. 1. " Z2 ,Data of Z2 Measurement"
|
|
hexmask.long.word 0x08 0.--11. 1. " Z1 ,Data of Z1 Measurement"
|
|
else
|
|
hexmask.long.word 0x08 16.--25. 1. " Z2 ,Data of Z2 Measurement"
|
|
hexmask.long.word 0x08 0.--9. 1. " Z1 ,Data of Z1 Measurement"
|
|
endif
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "ADC_TRGR,ADC Trigger Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRGPER ,Trigger Period"
|
|
sif (cpu()!="AT91SAM9G25"||cpu()!="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TRGMOD ,Trigger Mode" "NO_TRIGGER,EXT_TRIG_RISE,EXT_TRIG_FALL,EXT_TRIG_ANY,Reserved,PERIOD_TRIG,CONTINUOUS,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TRGMOD ,Trigger Mode" "NO_TRIGGER,EXT_TRIG_RISE,EXT_TRIG_FALL,EXT_TRIG_ANY,PEN_TRIG,PERIOD_TRIG,CONTINUOUS,?..."
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "ADC_WPMR,ADC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X35"||cpu()=="AT91SAM9X25")
|
|
hide.long 0x00 "ADC_WPSR,ADC Write Protect Status Register"
|
|
in
|
|
else
|
|
hide.long 0x00 "ADC_WPSR,ADC Write Protect Status Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.open "SSC (Synchronous Serial Controller)"
|
|
tree "SSC0"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfff9c000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
base ad:0xF0010000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffbc000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC0_CR,SSC0 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC0_CMR,SSC0 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC0_RCMR,SSC0 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC0_RFMR,SSC0 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC0_TCMR,SSC0 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC0_TFMR,SSC0 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC0_RHR,SSC0 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC0_THR,SSC0 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC0_RSHR,SSC0 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC0_TSHR,SSC0 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC0_RC0R,SSC0 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC0_RC1R,SSC0 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC0_SR,SSC0 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC0_IMR,SSC0 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
tree "PDC_SSC0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC0_RPR,Synchronous Serial Controller 0 Receive Pointer Register"
|
|
line.long 0x04 "SSC0_RCR,Synchronous Serial Controller 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC0_TPR,Synchronous Serial Controller 0 Transmit Pointer Register"
|
|
line.long 0x0c "SSC0_TCR,Synchronous Serial Controller 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC0_RNPR,Synchronous Serial Controller 0 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC0_RNCR,Synchronous Serial Controller 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC0_TNPR,Synchronous Serial Controller 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC0_TNCR,Synchronous Serial Controller 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC0_PTCR,Synchronous Serial Controller 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC0_PTSR,Synchronous Serial Controller 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "SSC1"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffa0000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC1_CR,SSC1 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC1_CMR,SSC1 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC1_RCMR,SSC1 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC1_RFMR,SSC1 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC1_TCMR,SSC1 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC1_TFMR,SSC1 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC1_THR,SSC1 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC1_TSHR,SSC1 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC1_RC0R,SSC1 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC1_RC1R,SSC1 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC1_SR,SSC1 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC1_IMR,SSC1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G10")
|
|
base ad:0xfffc0000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC1_CR,SSC1 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC1_CMR,SSC1 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC1_RCMR,SSC1 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC1_RFMR,SSC1 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC1_TCMR,SSC1 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC1_TFMR,SSC1 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC1_RHR,SSC1 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC1_THR,SSC1 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC1_RSHR,SSC1 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC1_TSHR,SSC1 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC1_RC0R,SSC1 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC1_RC1R,SSC1 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC1_SR,SSC1 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC1_IMR,SSC1 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree "PDC_SSC1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC1_RPR,Synchronous Serial Controller 1 Receive Pointer Register"
|
|
line.long 0x04 "SSC1_RCR,Synchronous Serial Controller 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC1_TPR,Synchronous Serial Controller 1 Transmit Pointer Register"
|
|
line.long 0x0c "SSC1_TCR,Synchronous Serial Controller 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC1_RNPR,Synchronous Serial Controller 1 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC1_RNCR,Synchronous Serial Controller 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC1_TNPR,Synchronous Serial Controller 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC1_TNCR,Synchronous Serial Controller 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC1_PTCR,Synchronous Serial Controller 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC1_PTSR,Synchronous Serial Controller 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G10")
|
|
tree "SSC2"
|
|
base ad:0xfffc4000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SSC2_CR,SSC2 Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXEN ,Transmit Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receive Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSC2_CMR,SSC2 Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock Divider"
|
|
group.long 0x10++0xf
|
|
line.long 0x00 "SSC2_RCMR,SSC2 Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive Start Delay"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STOP ,Receive Stop Selection" "After completion,After starting"
|
|
bitfld.long 0x00 8.--11. " START ,Receive Start Selection" "Continuous,Transmit start,Low level on RF,High level on RF,Falling edge on RF,Rising edge on RF,Any level change on RF,Any edge on RF,Compare 0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive Clock Gating Selection" "None,RF low,RF high,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive Clock Inversion" "Falling/rising,Rising/falling"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive Clock Selection" "Divided Clock,TK Clock signal,RK Pin,?..."
|
|
line.long 0x04 "SSC2_RFMR,SSC2 Receive Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive Frame Sync Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop Mode" "Normal,Loop"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
line.long 0x08 "SSC2_TCMR,SSC2 Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit Start Delay"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " START ,Transmit Start Selection" "Continuous,Receive start,Low level on TF,High level on TF,Falling edge on TF,Rising edge on TF,Any level change on TF,Any edge on TF,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit Clock Gating Selection" "None,TF low,TF high,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " CKI ,Transmit Clock Inversion" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit Clock Output Mode Selection" "None,Continuous,Transfers,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit Clock Selection" "Divided Clock,RK Clock signal,TK Pin,?..."
|
|
line.long 0x0c "SSC2_TFMR,SSC2 Transmit Frame Mode Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x0c 28.--31. " FSLEN_EXT , FSLEN Field Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 24. " FSEDGE ,Frame Sync Edge Detection" "Positive,Negative"
|
|
bitfld.long 0x0c 23. " FSDEN ,Frame Sync Data Enable" "TD default,SSC_TSHR shifted out"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " FSOS ,Transmit Frame Sync Output Selection" "None,Negative,Positive,Driven Low,Driven High,Toggling,?..."
|
|
bitfld.long 0x0c 16.--19. " FSLEN ,Transmit Frame Sync Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--11. " DATNB ,Data Number per Frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0c 7. " MSBF ,Most Significant Bit First" "LSB,MSB"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DATDEF ,Data Default Value" "Low,High"
|
|
bitfld.long 0x0c 0.--4. " DATLEN ,Data Length" "Forbidden,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits"
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SSC2_RHR,SSC2 Receive Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SSC2_RHR,SSC2 Receive Holding Register"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SSC2_THR,SSC2 Transmit Holding Register"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")||cpu()=="AT91SAM9M11"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SSC2_RSHR,SSC2 Receive Synchronization Holding Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SSC2_RSHR,SSC2 Receive Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSDAT ,Receive Synchronization Data"
|
|
endif
|
|
group.long 0x34++0xB
|
|
line.long 0x00 "SSC2_TSHR,SSC2 Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit Synchronization Data"
|
|
line.long 0x4 "SSC2_RC0R,SSC2 Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CP0 ,Receive Compare Data 0"
|
|
line.long 0x8 "SSC2_RC1R,SSC2 Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CP1 ,Receive Compare Data 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SSC2_SR,SSC2 Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "SSC2_IMR,SSC2 Interrupt Mask Register"
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " RXSYN_set/clr ,Rx Sync Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " TXSYN_set/clr ,Tx Sync Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " CP1_set/clr ,Compare 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " CP0_set/clr ,Compare 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Reception Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OVRUN_set/clr ,Receive Overrun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " ENDTX_set/clr ,End of Transmission Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " TXEMPTY_set/clr ,Transmit Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "SSC_WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SSC_WPSR,SSC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_SSC2"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SSC2_RPR,Synchronous Serial Controller 2 Receive Pointer Register"
|
|
line.long 0x04 "SSC2_RCR,Synchronous Serial Controller 2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SSC2_TPR,Synchronous Serial Controller 2 Transmit Pointer Register"
|
|
line.long 0x0c "SSC2_TCR,Synchronous Serial Controller 2 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SSC2_RNPR,Synchronous Serial Controller 2 Receive Next Pointer Register"
|
|
line.long 0x14 "SSC2_RNCR,Synchronous Serial Controller 2 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SSC2_TNPR,Synchronous Serial Controller 2 Transmit Next Pointer Register"
|
|
line.long 0x1c "SSC2_TNCR,Synchronous Serial Controller 2 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SSC2_PTCR,Synchronous Serial Controller 2 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SSC2_PTSR,Synchronous Serial Controller 2 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC Channel 0"
|
|
base ad:0xfff7c000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
base ad:0xfff7c040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
base ad:0xfff7c080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfff7c080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC0/TC1/TC2)"
|
|
base ad:0xfff7c000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
base ad:0xfffd4000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
base ad:0xfffd4040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
base ad:0xfffd4080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffd4080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffd4080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC3/TC4/TC5)"
|
|
base ad:0xfffd4000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC Channel 0"
|
|
base ad:0xfffa0000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
base ad:0xfffa0040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
base ad:0xfffa0080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffa0080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffa0080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC0/TC1/TC2)"
|
|
base ad:0xfffa0000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G20")
|
|
tree "TC Channel 3"
|
|
base ad:0xfffdc000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc000+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc000+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
base ad:0xfffdc040
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc040+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc040+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
base ad:0xfffdc080
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
if (data.long(ad:0xfffdc080+0x04)&0x8000)==0x0000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Capture Mode)"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Each"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register (Waveform Mode)"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Capture/Waveform Mode" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Cleared,Toggled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP without automatic,UPDOWN without automatic,UP with automatic,UPDOWN with automatic"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Each"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0 ANDed,XC1 ANDed,XC2 ANDed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (data.long(ad:0xfffdc080+0x04)&0x8000)==0x0000
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
sif (cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
else
|
|
line.long 0x8 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
endif
|
|
setclrfld.long 0x8 7. 0x0 7. 0x4 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x8 6. 0x0 6. 0x4 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 5. 0x0 5. 0x4 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x8 4. 0x0 4. 0x4 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 3. 0x0 3. 0x4 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x8 2. 0x0 2. 0x4 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x8 1. 0x0 1. 0x4 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x8 0. 0x0 0. 0x4 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Block Registers (TC3/TC4/TC5)"
|
|
base ad:0xfffdc000
|
|
width 8.
|
|
wgroup.long 0xc0++0x3
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G46")
|
|
tree.open "HSMCI (High Speed MultiMedia Card Interface)"
|
|
tree "HSMCI 0"
|
|
base ad:0xfff80000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (0xfff80000+0x200)--(0xfff80000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "HSMCI 1"
|
|
base ad:0xfffd0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (fffd0000+0x200)--(fffd0000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "MCI (MultiMedia Card Interface)"
|
|
tree "MCI 0"
|
|
sif (cpu()=="AT91SAM9G45")
|
|
base ad:0xfff80000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (0xfff80000+0x200)--(0xfff80000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
else
|
|
base ad:0xfffa8000
|
|
width 0xb
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "MCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " MCIDIS ,Multi-Media Interface Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enabled"
|
|
group.long 0x04++3
|
|
line.long 0x00 "MCI_MR,MCI Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PDCPADV ,PDC Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " PDCFBYTE ,PDC Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "MCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0 x Multiplier,1 x Multiplier,2 x Multiplier,3 x Multiplier,4 x Multiplier,5 x Multiplier,6 x Multiplier,7 x Multiplier,8 x Multiplier,9 x Multiplier,10 x Multiplier,11 x Multiplier,12 x Multiplier,13 x Multiplier,14 x Multiplier,15 x Multiplier"
|
|
line.long 0x04 "MCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 7. " SDCBUS ,SDCard Bus Width" "1-bit,4-bit"
|
|
sif (cpu()=="AT91SAM9G20")
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "MCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "MCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Started,Stopped,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,Reserved,Interrupt command,Interrupt response,?..."
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "MCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "MCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "MCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "MCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "MCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "MCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "MCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "MCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "MCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_Clear/Set ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_Clear/Set ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_Clear/Set ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_Clear/Set ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_Clear/Set ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_Clear/Set ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_Clear/Set ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_Clear/Set ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_Clear/Set ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_Clear/Set ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_Clear/Set ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9G20")
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " SDIOIRQB_Clear/Set ,SDIOIRQB Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_Clear/Set ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_Clear/Set ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_Clear/Set ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_Clear/Set ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_Clear/Set ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_Clear/Set ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_Clear/Set ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_Clear/Set ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_Clear/Set ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "PDC_MCI 0"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI0_RPR,MultiMedia Card Interface 0 Receive Pointer Register"
|
|
line.long 0x04 "MCI0_RCR,MultiMedia Card Interface 0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI0_TPR,MultiMedia Card Interface 0 Transmit Pointer Register"
|
|
line.long 0x0c "MCI0_TCR,MultiMedia Card Interface 0 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI0_RNPR,MultiMedia Card Interface 0 Receive Next Pointer Register"
|
|
line.long 0x14 "MCI0_RNCR,MultiMedia Card Interface 0 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI0_TNPR,MultiMedia Card Interface 0 Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI0_TNCR,MultiMedia Card Interface 0 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI0_PTCR,MultiMedia Card Interface 0 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI0_PTSR,MultiMedia Card Interface 0 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G45")
|
|
tree "MCI 1"
|
|
base ad:0xfffd0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Not odd,Odd"
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
line.long 0x04 "HSMCI_SDCR,HSMCI SDCard/SDIO Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard/SDIO Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard/SDIO Slot" "A,?..."
|
|
else
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,Reserved,4-bit,8-bit"
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "No acknowledge,Acknowledge"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,Reserved,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronized,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
sif (cpu()=="AT91SAM9N12")||(cpu()=="AT91SAM9M11"||cpu()=="AT9SAM9X25"||cpu()=="AT91SAM9X35")
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "HSMCI_RDR, MCI Receive Data Register"
|
|
in
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " MCI_SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4,8,16"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
line.long 0x04 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x04 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "One data written,Sufficient level"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9M11"||cpu()=="AT91SAM9X25"||cpu()=="AT91SAM9X35")
|
|
tree "HSMCI FIFO"
|
|
hgroup.long 0x200++0x3FF
|
|
hide.long 0x0 "FIFO0,HSMCI FIFO0 Memory Aperture"
|
|
in
|
|
hide.long 0x4 "FIFO1,HSMCI FIFO1 Memory Aperture"
|
|
in
|
|
hide.long 0x8 "FIFO2,HSMCI FIFO2 Memory Aperture"
|
|
in
|
|
hide.long 0xC "FIFO3,HSMCI FIFO3 Memory Aperture"
|
|
in
|
|
hide.long 0x10 "FIFO4,HSMCI FIFO4 Memory Aperture"
|
|
in
|
|
hide.long 0x14 "FIFO5,HSMCI FIFO5 Memory Aperture"
|
|
in
|
|
hide.long 0x18 "FIFO6,HSMCI FIFO6 Memory Aperture"
|
|
in
|
|
hide.long 0x1C "FIFO7,HSMCI FIFO7 Memory Aperture"
|
|
in
|
|
hide.long 0x20 "FIFO8,HSMCI FIFO8 Memory Aperture"
|
|
in
|
|
hide.long 0x24 "FIFO9,HSMCI FIFO9 Memory Aperture"
|
|
in
|
|
hide.long 0x28 "FIFO10,HSMCI FIFO10 Memory Aperture"
|
|
in
|
|
hide.long 0x2C "FIFO11,HSMCI FIFO11 Memory Aperture"
|
|
in
|
|
hide.long 0x30 "FIFO12,HSMCI FIFO12 Memory Aperture"
|
|
in
|
|
hide.long 0x34 "FIFO13,HSMCI FIFO13 Memory Aperture"
|
|
in
|
|
hide.long 0x38 "FIFO14,HSMCI FIFO14 Memory Aperture"
|
|
in
|
|
hide.long 0x3C "FIFO15,HSMCI FIFO15 Memory Aperture"
|
|
in
|
|
hide.long 0x40 "FIFO16,HSMCI FIFO16 Memory Aperture"
|
|
in
|
|
hide.long 0x44 "FIFO17,HSMCI FIFO17 Memory Aperture"
|
|
in
|
|
hide.long 0x48 "FIFO18,HSMCI FIFO18 Memory Aperture"
|
|
in
|
|
hide.long 0x4C "FIFO19,HSMCI FIFO19 Memory Aperture"
|
|
in
|
|
hide.long 0x50 "FIFO20,HSMCI FIFO20 Memory Aperture"
|
|
in
|
|
hide.long 0x54 "FIFO21,HSMCI FIFO21 Memory Aperture"
|
|
in
|
|
hide.long 0x58 "FIFO22,HSMCI FIFO22 Memory Aperture"
|
|
in
|
|
hide.long 0x5C "FIFO23,HSMCI FIFO23 Memory Aperture"
|
|
in
|
|
hide.long 0x60 "FIFO24,HSMCI FIFO24 Memory Aperture"
|
|
in
|
|
hide.long 0x64 "FIFO25,HSMCI FIFO25 Memory Aperture"
|
|
in
|
|
hide.long 0x68 "FIFO26,HSMCI FIFO26 Memory Aperture"
|
|
in
|
|
hide.long 0x6C "FIFO27,HSMCI FIFO27 Memory Aperture"
|
|
in
|
|
hide.long 0x70 "FIFO28,HSMCI FIFO28 Memory Aperture"
|
|
in
|
|
hide.long 0x74 "FIFO29,HSMCI FIFO29 Memory Aperture"
|
|
in
|
|
hide.long 0x78 "FIFO30,HSMCI FIFO30 Memory Aperture"
|
|
in
|
|
hide.long 0x7C "FIFO31,HSMCI FIFO31 Memory Aperture"
|
|
in
|
|
hide.long 0x80 "FIFO32,HSMCI FIFO32 Memory Aperture"
|
|
in
|
|
hide.long 0x84 "FIFO33,HSMCI FIFO33 Memory Aperture"
|
|
in
|
|
hide.long 0x88 "FIFO34,HSMCI FIFO34 Memory Aperture"
|
|
in
|
|
hide.long 0x8C "FIFO35,HSMCI FIFO35 Memory Aperture"
|
|
in
|
|
hide.long 0x90 "FIFO36,HSMCI FIFO36 Memory Aperture"
|
|
in
|
|
hide.long 0x94 "FIFO37,HSMCI FIFO37 Memory Aperture"
|
|
in
|
|
hide.long 0x98 "FIFO38,HSMCI FIFO38 Memory Aperture"
|
|
in
|
|
hide.long 0x9C "FIFO39,HSMCI FIFO39 Memory Aperture"
|
|
in
|
|
hide.long 0xA0 "FIFO40,HSMCI FIFO40 Memory Aperture"
|
|
in
|
|
hide.long 0xA4 "FIFO41,HSMCI FIFO41 Memory Aperture"
|
|
in
|
|
hide.long 0xA8 "FIFO42,HSMCI FIFO42 Memory Aperture"
|
|
in
|
|
hide.long 0xAC "FIFO43,HSMCI FIFO43 Memory Aperture"
|
|
in
|
|
hide.long 0xB0 "FIFO44,HSMCI FIFO44 Memory Aperture"
|
|
in
|
|
hide.long 0xB4 "FIFO45,HSMCI FIFO45 Memory Aperture"
|
|
in
|
|
hide.long 0xB8 "FIFO46,HSMCI FIFO46 Memory Aperture"
|
|
in
|
|
hide.long 0xBC "FIFO47,HSMCI FIFO47 Memory Aperture"
|
|
in
|
|
hide.long 0xC0 "FIFO48,HSMCI FIFO48 Memory Aperture"
|
|
in
|
|
hide.long 0xC4 "FIFO49,HSMCI FIFO49 Memory Aperture"
|
|
in
|
|
hide.long 0xC8 "FIFO50,HSMCI FIFO50 Memory Aperture"
|
|
in
|
|
hide.long 0xCC "FIFO51,HSMCI FIFO51 Memory Aperture"
|
|
in
|
|
hide.long 0xD0 "FIFO52,HSMCI FIFO52 Memory Aperture"
|
|
in
|
|
hide.long 0xD4 "FIFO53,HSMCI FIFO53 Memory Aperture"
|
|
in
|
|
hide.long 0xD8 "FIFO54,HSMCI FIFO54 Memory Aperture"
|
|
in
|
|
hide.long 0xDC "FIFO55,HSMCI FIFO55 Memory Aperture"
|
|
in
|
|
hide.long 0xE0 "FIFO56,HSMCI FIFO56 Memory Aperture"
|
|
in
|
|
hide.long 0xE4 "FIFO57,HSMCI FIFO57 Memory Aperture"
|
|
in
|
|
hide.long 0xE8 "FIFO58,HSMCI FIFO58 Memory Aperture"
|
|
in
|
|
hide.long 0xEC "FIFO59,HSMCI FIFO59 Memory Aperture"
|
|
in
|
|
hide.long 0xF0 "FIFO60,HSMCI FIFO60 Memory Aperture"
|
|
in
|
|
hide.long 0xF4 "FIFO61,HSMCI FIFO61 Memory Aperture"
|
|
in
|
|
hide.long 0xF8 "FIFO62,HSMCI FIFO62 Memory Aperture"
|
|
in
|
|
hide.long 0xFC "FIFO63,HSMCI FIFO63 Memory Aperture"
|
|
in
|
|
hide.long 0x100 "FIFO64,HSMCI FIFO64 Memory Aperture"
|
|
in
|
|
hide.long 0x104 "FIFO65,HSMCI FIFO65 Memory Aperture"
|
|
in
|
|
hide.long 0x108 "FIFO66,HSMCI FIFO66 Memory Aperture"
|
|
in
|
|
hide.long 0x10C "FIFO67,HSMCI FIFO67 Memory Aperture"
|
|
in
|
|
hide.long 0x110 "FIFO68,HSMCI FIFO68 Memory Aperture"
|
|
in
|
|
hide.long 0x114 "FIFO69,HSMCI FIFO69 Memory Aperture"
|
|
in
|
|
hide.long 0x118 "FIFO70,HSMCI FIFO70 Memory Aperture"
|
|
in
|
|
hide.long 0x11C "FIFO71,HSMCI FIFO71 Memory Aperture"
|
|
in
|
|
hide.long 0x120 "FIFO72,HSMCI FIFO72 Memory Aperture"
|
|
in
|
|
hide.long 0x124 "FIFO73,HSMCI FIFO73 Memory Aperture"
|
|
in
|
|
hide.long 0x128 "FIFO74,HSMCI FIFO74 Memory Aperture"
|
|
in
|
|
hide.long 0x12C "FIFO75,HSMCI FIFO75 Memory Aperture"
|
|
in
|
|
hide.long 0x130 "FIFO76,HSMCI FIFO76 Memory Aperture"
|
|
in
|
|
hide.long 0x134 "FIFO77,HSMCI FIFO77 Memory Aperture"
|
|
in
|
|
hide.long 0x138 "FIFO78,HSMCI FIFO78 Memory Aperture"
|
|
in
|
|
hide.long 0x13C "FIFO79,HSMCI FIFO79 Memory Aperture"
|
|
in
|
|
hide.long 0x140 "FIFO80,HSMCI FIFO80 Memory Aperture"
|
|
in
|
|
hide.long 0x144 "FIFO81,HSMCI FIFO81 Memory Aperture"
|
|
in
|
|
hide.long 0x148 "FIFO82,HSMCI FIFO82 Memory Aperture"
|
|
in
|
|
hide.long 0x14C "FIFO83,HSMCI FIFO83 Memory Aperture"
|
|
in
|
|
hide.long 0x150 "FIFO84,HSMCI FIFO84 Memory Aperture"
|
|
in
|
|
hide.long 0x154 "FIFO85,HSMCI FIFO85 Memory Aperture"
|
|
in
|
|
hide.long 0x158 "FIFO86,HSMCI FIFO86 Memory Aperture"
|
|
in
|
|
hide.long 0x15C "FIFO87,HSMCI FIFO87 Memory Aperture"
|
|
in
|
|
hide.long 0x160 "FIFO88,HSMCI FIFO88 Memory Aperture"
|
|
in
|
|
hide.long 0x164 "FIFO89,HSMCI FIFO89 Memory Aperture"
|
|
in
|
|
hide.long 0x168 "FIFO90,HSMCI FIFO90 Memory Aperture"
|
|
in
|
|
hide.long 0x16C "FIFO91,HSMCI FIFO91 Memory Aperture"
|
|
in
|
|
hide.long 0x170 "FIFO92,HSMCI FIFO92 Memory Aperture"
|
|
in
|
|
hide.long 0x174 "FIFO93,HSMCI FIFO93 Memory Aperture"
|
|
in
|
|
hide.long 0x178 "FIFO94,HSMCI FIFO94 Memory Aperture"
|
|
in
|
|
hide.long 0x17C "FIFO95,HSMCI FIFO95 Memory Aperture"
|
|
in
|
|
hide.long 0x180 "FIFO96,HSMCI FIFO96 Memory Aperture"
|
|
in
|
|
hide.long 0x184 "FIFO97,HSMCI FIFO97 Memory Aperture"
|
|
in
|
|
hide.long 0x188 "FIFO98,HSMCI FIFO98 Memory Aperture"
|
|
in
|
|
hide.long 0x18C "FIFO99,HSMCI FIFO99 Memory Aperture"
|
|
in
|
|
hide.long 0x190 "FIFO100,HSMCI FIFO100 Memory Aperture"
|
|
in
|
|
hide.long 0x194 "FIFO101,HSMCI FIFO101 Memory Aperture"
|
|
in
|
|
hide.long 0x198 "FIFO102,HSMCI FIFO102 Memory Aperture"
|
|
in
|
|
hide.long 0x19C "FIFO103,HSMCI FIFO103 Memory Aperture"
|
|
in
|
|
hide.long 0x1A0 "FIFO104,HSMCI FIFO104 Memory Aperture"
|
|
in
|
|
hide.long 0x1A4 "FIFO105,HSMCI FIFO105 Memory Aperture"
|
|
in
|
|
hide.long 0x1A8 "FIFO106,HSMCI FIFO106 Memory Aperture"
|
|
in
|
|
hide.long 0x1AC "FIFO107,HSMCI FIFO107 Memory Aperture"
|
|
in
|
|
hide.long 0x1B0 "FIFO108,HSMCI FIFO108 Memory Aperture"
|
|
in
|
|
hide.long 0x1B4 "FIFO109,HSMCI FIFO109 Memory Aperture"
|
|
in
|
|
hide.long 0x1B8 "FIFO110,HSMCI FIFO110 Memory Aperture"
|
|
in
|
|
hide.long 0x1BC "FIFO111,HSMCI FIFO111 Memory Aperture"
|
|
in
|
|
hide.long 0x1C0 "FIFO112,HSMCI FIFO112 Memory Aperture"
|
|
in
|
|
hide.long 0x1C4 "FIFO113,HSMCI FIFO113 Memory Aperture"
|
|
in
|
|
hide.long 0x1C8 "FIFO114,HSMCI FIFO114 Memory Aperture"
|
|
in
|
|
hide.long 0x1CC "FIFO115,HSMCI FIFO115 Memory Aperture"
|
|
in
|
|
hide.long 0x1D0 "FIFO116,HSMCI FIFO116 Memory Aperture"
|
|
in
|
|
hide.long 0x1D4 "FIFO117,HSMCI FIFO117 Memory Aperture"
|
|
in
|
|
hide.long 0x1D8 "FIFO118,HSMCI FIFO118 Memory Aperture"
|
|
in
|
|
hide.long 0x1DC "FIFO119,HSMCI FIFO119 Memory Aperture"
|
|
in
|
|
hide.long 0x1E0 "FIFO120,HSMCI FIFO120 Memory Aperture"
|
|
in
|
|
hide.long 0x1E4 "FIFO121,HSMCI FIFO121 Memory Aperture"
|
|
in
|
|
hide.long 0x1E8 "FIFO122,HSMCI FIFO122 Memory Aperture"
|
|
in
|
|
hide.long 0x1EC "FIFO123,HSMCI FIFO123 Memory Aperture"
|
|
in
|
|
hide.long 0x1F0 "FIFO124,HSMCI FIFO124 Memory Aperture"
|
|
in
|
|
hide.long 0x1F4 "FIFO125,HSMCI FIFO125 Memory Aperture"
|
|
in
|
|
hide.long 0x1F8 "FIFO126,HSMCI FIFO126 Memory Aperture"
|
|
in
|
|
hide.long 0x1FC "FIFO127,HSMCI FIFO127 Memory Aperture"
|
|
in
|
|
hide.long 0x200 "FIFO128,HSMCI FIFO128 Memory Aperture"
|
|
in
|
|
hide.long 0x204 "FIFO129,HSMCI FIFO129 Memory Aperture"
|
|
in
|
|
hide.long 0x208 "FIFO130,HSMCI FIFO130 Memory Aperture"
|
|
in
|
|
hide.long 0x20C "FIFO131,HSMCI FIFO131 Memory Aperture"
|
|
in
|
|
hide.long 0x210 "FIFO132,HSMCI FIFO132 Memory Aperture"
|
|
in
|
|
hide.long 0x214 "FIFO133,HSMCI FIFO133 Memory Aperture"
|
|
in
|
|
hide.long 0x218 "FIFO134,HSMCI FIFO134 Memory Aperture"
|
|
in
|
|
hide.long 0x21C "FIFO135,HSMCI FIFO135 Memory Aperture"
|
|
in
|
|
hide.long 0x220 "FIFO136,HSMCI FIFO136 Memory Aperture"
|
|
in
|
|
hide.long 0x224 "FIFO137,HSMCI FIFO137 Memory Aperture"
|
|
in
|
|
hide.long 0x228 "FIFO138,HSMCI FIFO138 Memory Aperture"
|
|
in
|
|
hide.long 0x22C "FIFO139,HSMCI FIFO139 Memory Aperture"
|
|
in
|
|
hide.long 0x230 "FIFO140,HSMCI FIFO140 Memory Aperture"
|
|
in
|
|
hide.long 0x234 "FIFO141,HSMCI FIFO141 Memory Aperture"
|
|
in
|
|
hide.long 0x238 "FIFO142,HSMCI FIFO142 Memory Aperture"
|
|
in
|
|
hide.long 0x23C "FIFO143,HSMCI FIFO143 Memory Aperture"
|
|
in
|
|
hide.long 0x240 "FIFO144,HSMCI FIFO144 Memory Aperture"
|
|
in
|
|
hide.long 0x244 "FIFO145,HSMCI FIFO145 Memory Aperture"
|
|
in
|
|
hide.long 0x248 "FIFO146,HSMCI FIFO146 Memory Aperture"
|
|
in
|
|
hide.long 0x24C "FIFO147,HSMCI FIFO147 Memory Aperture"
|
|
in
|
|
hide.long 0x250 "FIFO148,HSMCI FIFO148 Memory Aperture"
|
|
in
|
|
hide.long 0x254 "FIFO149,HSMCI FIFO149 Memory Aperture"
|
|
in
|
|
hide.long 0x258 "FIFO150,HSMCI FIFO150 Memory Aperture"
|
|
in
|
|
hide.long 0x25C "FIFO151,HSMCI FIFO151 Memory Aperture"
|
|
in
|
|
hide.long 0x260 "FIFO152,HSMCI FIFO152 Memory Aperture"
|
|
in
|
|
hide.long 0x264 "FIFO153,HSMCI FIFO153 Memory Aperture"
|
|
in
|
|
hide.long 0x268 "FIFO154,HSMCI FIFO154 Memory Aperture"
|
|
in
|
|
hide.long 0x26C "FIFO155,HSMCI FIFO155 Memory Aperture"
|
|
in
|
|
hide.long 0x270 "FIFO156,HSMCI FIFO156 Memory Aperture"
|
|
in
|
|
hide.long 0x274 "FIFO157,HSMCI FIFO157 Memory Aperture"
|
|
in
|
|
hide.long 0x278 "FIFO158,HSMCI FIFO158 Memory Aperture"
|
|
in
|
|
hide.long 0x27C "FIFO159,HSMCI FIFO159 Memory Aperture"
|
|
in
|
|
hide.long 0x280 "FIFO160,HSMCI FIFO160 Memory Aperture"
|
|
in
|
|
hide.long 0x284 "FIFO161,HSMCI FIFO161 Memory Aperture"
|
|
in
|
|
hide.long 0x288 "FIFO162,HSMCI FIFO162 Memory Aperture"
|
|
in
|
|
hide.long 0x28C "FIFO163,HSMCI FIFO163 Memory Aperture"
|
|
in
|
|
hide.long 0x290 "FIFO164,HSMCI FIFO164 Memory Aperture"
|
|
in
|
|
hide.long 0x294 "FIFO165,HSMCI FIFO165 Memory Aperture"
|
|
in
|
|
hide.long 0x298 "FIFO166,HSMCI FIFO166 Memory Aperture"
|
|
in
|
|
hide.long 0x29C "FIFO167,HSMCI FIFO167 Memory Aperture"
|
|
in
|
|
hide.long 0x2A0 "FIFO168,HSMCI FIFO168 Memory Aperture"
|
|
in
|
|
hide.long 0x2A4 "FIFO169,HSMCI FIFO169 Memory Aperture"
|
|
in
|
|
hide.long 0x2A8 "FIFO170,HSMCI FIFO170 Memory Aperture"
|
|
in
|
|
hide.long 0x2AC "FIFO171,HSMCI FIFO171 Memory Aperture"
|
|
in
|
|
hide.long 0x2B0 "FIFO172,HSMCI FIFO172 Memory Aperture"
|
|
in
|
|
hide.long 0x2B4 "FIFO173,HSMCI FIFO173 Memory Aperture"
|
|
in
|
|
hide.long 0x2B8 "FIFO174,HSMCI FIFO174 Memory Aperture"
|
|
in
|
|
hide.long 0x2BC "FIFO175,HSMCI FIFO175 Memory Aperture"
|
|
in
|
|
hide.long 0x2C0 "FIFO176,HSMCI FIFO176 Memory Aperture"
|
|
in
|
|
hide.long 0x2C4 "FIFO177,HSMCI FIFO177 Memory Aperture"
|
|
in
|
|
hide.long 0x2C8 "FIFO178,HSMCI FIFO178 Memory Aperture"
|
|
in
|
|
hide.long 0x2CC "FIFO179,HSMCI FIFO179 Memory Aperture"
|
|
in
|
|
hide.long 0x2D0 "FIFO180,HSMCI FIFO180 Memory Aperture"
|
|
in
|
|
hide.long 0x2D4 "FIFO181,HSMCI FIFO181 Memory Aperture"
|
|
in
|
|
hide.long 0x2D8 "FIFO182,HSMCI FIFO182 Memory Aperture"
|
|
in
|
|
hide.long 0x2DC "FIFO183,HSMCI FIFO183 Memory Aperture"
|
|
in
|
|
hide.long 0x2E0 "FIFO184,HSMCI FIFO184 Memory Aperture"
|
|
in
|
|
hide.long 0x2E4 "FIFO185,HSMCI FIFO185 Memory Aperture"
|
|
in
|
|
hide.long 0x2E8 "FIFO186,HSMCI FIFO186 Memory Aperture"
|
|
in
|
|
hide.long 0x2EC "FIFO187,HSMCI FIFO187 Memory Aperture"
|
|
in
|
|
hide.long 0x2F0 "FIFO188,HSMCI FIFO188 Memory Aperture"
|
|
in
|
|
hide.long 0x2F4 "FIFO189,HSMCI FIFO189 Memory Aperture"
|
|
in
|
|
hide.long 0x2F8 "FIFO190,HSMCI FIFO190 Memory Aperture"
|
|
in
|
|
hide.long 0x2FC "FIFO191,HSMCI FIFO191 Memory Aperture"
|
|
in
|
|
hide.long 0x300 "FIFO192,HSMCI FIFO192 Memory Aperture"
|
|
in
|
|
hide.long 0x304 "FIFO193,HSMCI FIFO193 Memory Aperture"
|
|
in
|
|
hide.long 0x308 "FIFO194,HSMCI FIFO194 Memory Aperture"
|
|
in
|
|
hide.long 0x30C "FIFO195,HSMCI FIFO195 Memory Aperture"
|
|
in
|
|
hide.long 0x310 "FIFO196,HSMCI FIFO196 Memory Aperture"
|
|
in
|
|
hide.long 0x314 "FIFO197,HSMCI FIFO197 Memory Aperture"
|
|
in
|
|
hide.long 0x318 "FIFO198,HSMCI FIFO198 Memory Aperture"
|
|
in
|
|
hide.long 0x31C "FIFO199,HSMCI FIFO199 Memory Aperture"
|
|
in
|
|
hide.long 0x320 "FIFO200,HSMCI FIFO200 Memory Aperture"
|
|
in
|
|
hide.long 0x324 "FIFO201,HSMCI FIFO201 Memory Aperture"
|
|
in
|
|
hide.long 0x328 "FIFO202,HSMCI FIFO202 Memory Aperture"
|
|
in
|
|
hide.long 0x32C "FIFO203,HSMCI FIFO203 Memory Aperture"
|
|
in
|
|
hide.long 0x330 "FIFO204,HSMCI FIFO204 Memory Aperture"
|
|
in
|
|
hide.long 0x334 "FIFO205,HSMCI FIFO205 Memory Aperture"
|
|
in
|
|
hide.long 0x338 "FIFO206,HSMCI FIFO206 Memory Aperture"
|
|
in
|
|
hide.long 0x33C "FIFO207,HSMCI FIFO207 Memory Aperture"
|
|
in
|
|
hide.long 0x340 "FIFO208,HSMCI FIFO208 Memory Aperture"
|
|
in
|
|
hide.long 0x344 "FIFO209,HSMCI FIFO209 Memory Aperture"
|
|
in
|
|
hide.long 0x348 "FIFO210,HSMCI FIFO210 Memory Aperture"
|
|
in
|
|
hide.long 0x34C "FIFO211,HSMCI FIFO211 Memory Aperture"
|
|
in
|
|
hide.long 0x350 "FIFO212,HSMCI FIFO212 Memory Aperture"
|
|
in
|
|
hide.long 0x354 "FIFO213,HSMCI FIFO213 Memory Aperture"
|
|
in
|
|
hide.long 0x358 "FIFO214,HSMCI FIFO214 Memory Aperture"
|
|
in
|
|
hide.long 0x35C "FIFO215,HSMCI FIFO215 Memory Aperture"
|
|
in
|
|
hide.long 0x360 "FIFO216,HSMCI FIFO216 Memory Aperture"
|
|
in
|
|
hide.long 0x364 "FIFO217,HSMCI FIFO217 Memory Aperture"
|
|
in
|
|
hide.long 0x368 "FIFO218,HSMCI FIFO218 Memory Aperture"
|
|
in
|
|
hide.long 0x36C "FIFO219,HSMCI FIFO219 Memory Aperture"
|
|
in
|
|
hide.long 0x370 "FIFO220,HSMCI FIFO220 Memory Aperture"
|
|
in
|
|
hide.long 0x374 "FIFO221,HSMCI FIFO221 Memory Aperture"
|
|
in
|
|
hide.long 0x378 "FIFO222,HSMCI FIFO222 Memory Aperture"
|
|
in
|
|
hide.long 0x37C "FIFO223,HSMCI FIFO223 Memory Aperture"
|
|
in
|
|
hide.long 0x380 "FIFO224,HSMCI FIFO224 Memory Aperture"
|
|
in
|
|
hide.long 0x384 "FIFO225,HSMCI FIFO225 Memory Aperture"
|
|
in
|
|
hide.long 0x388 "FIFO226,HSMCI FIFO226 Memory Aperture"
|
|
in
|
|
hide.long 0x38C "FIFO227,HSMCI FIFO227 Memory Aperture"
|
|
in
|
|
hide.long 0x390 "FIFO228,HSMCI FIFO228 Memory Aperture"
|
|
in
|
|
hide.long 0x394 "FIFO229,HSMCI FIFO229 Memory Aperture"
|
|
in
|
|
hide.long 0x398 "FIFO230,HSMCI FIFO230 Memory Aperture"
|
|
in
|
|
hide.long 0x39C "FIFO231,HSMCI FIFO231 Memory Aperture"
|
|
in
|
|
hide.long 0x3A0 "FIFO232,HSMCI FIFO232 Memory Aperture"
|
|
in
|
|
hide.long 0x3A4 "FIFO233,HSMCI FIFO233 Memory Aperture"
|
|
in
|
|
hide.long 0x3A8 "FIFO234,HSMCI FIFO234 Memory Aperture"
|
|
in
|
|
hide.long 0x3AC "FIFO235,HSMCI FIFO235 Memory Aperture"
|
|
in
|
|
hide.long 0x3B0 "FIFO236,HSMCI FIFO236 Memory Aperture"
|
|
in
|
|
hide.long 0x3B4 "FIFO237,HSMCI FIFO237 Memory Aperture"
|
|
in
|
|
hide.long 0x3B8 "FIFO238,HSMCI FIFO238 Memory Aperture"
|
|
in
|
|
hide.long 0x3BC "FIFO239,HSMCI FIFO239 Memory Aperture"
|
|
in
|
|
hide.long 0x3C0 "FIFO240,HSMCI FIFO240 Memory Aperture"
|
|
in
|
|
hide.long 0x3C4 "FIFO241,HSMCI FIFO241 Memory Aperture"
|
|
in
|
|
hide.long 0x3C8 "FIFO242,HSMCI FIFO242 Memory Aperture"
|
|
in
|
|
hide.long 0x3CC "FIFO243,HSMCI FIFO243 Memory Aperture"
|
|
in
|
|
hide.long 0x3D0 "FIFO244,HSMCI FIFO244 Memory Aperture"
|
|
in
|
|
hide.long 0x3D4 "FIFO245,HSMCI FIFO245 Memory Aperture"
|
|
in
|
|
hide.long 0x3D8 "FIFO246,HSMCI FIFO246 Memory Aperture"
|
|
in
|
|
hide.long 0x3DC "FIFO247,HSMCI FIFO247 Memory Aperture"
|
|
in
|
|
hide.long 0x3E0 "FIFO248,HSMCI FIFO248 Memory Aperture"
|
|
in
|
|
hide.long 0x3E4 "FIFO249,HSMCI FIFO249 Memory Aperture"
|
|
in
|
|
hide.long 0x3E8 "FIFO250,HSMCI FIFO250 Memory Aperture"
|
|
in
|
|
hide.long 0x3EC "FIFO251,HSMCI FIFO251 Memory Aperture"
|
|
in
|
|
hide.long 0x3F0 "FIFO252,HSMCI FIFO252 Memory Aperture"
|
|
in
|
|
hide.long 0x3F4 "FIFO253,HSMCI FIFO253 Memory Aperture"
|
|
in
|
|
hide.long 0x3F8 "FIFO254,HSMCI FIFO254 Memory Aperture"
|
|
in
|
|
hide.long 0x3FC "FIFO255,HSMCI FIFO255 Memory Aperture"
|
|
in
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9N12")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "FIFO,HSMCI FIFO Memory Aperture"
|
|
button "DATA" "d (0xfffd0000+0x200)--(0xfffd0000+0x5FC) /long"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PDC_MCI 1"
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "MCI1_RPR,MultiMedia Card Interface 1 Receive Pointer Register"
|
|
line.long 0x04 "MCI1_RCR,MultiMedia Card Interface 1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MCI1_TPR,MultiMedia Card Interface 1 Transmit Pointer Register"
|
|
line.long 0x0c "MCI1_TCR,MultiMedia Card Interface 1 Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MCI1_RNPR,MultiMedia Card Interface 1 Receive Next Pointer Register"
|
|
line.long 0x14 "MCI1_RNCR,MultiMedia Card Interface 1 Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "MCI1_TNPR,MultiMedia Card Interface 1 Transmit Next Pointer Register"
|
|
line.long 0x1c "MCI1_TNCR,MultiMedia Card Interface 1 Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MCI1_PTCR,MultiMedia Card Interface 1 PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MCI1_PTSR,MultiMedia Card Interface 1 PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffbc000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
line.long 0x04 "EMAC_NCFG,Network Configuration Register"
|
|
else
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
endif
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
else
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
endif
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xfffbc000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT91CAP9")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT9CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
endif
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_EXCOL,Excessive Collisions Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROVR,Receive Overrun Errors Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25")
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
base ad:0xF802C000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
line.long 0x04 "EMAC_NCFG,Network Configuration Register"
|
|
else
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
endif
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
else
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
endif
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xF802C000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT91CAP9")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT9CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
endif
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_EXCOL,Excessive Collisions Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROVR,Receive Overrun Errors Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25")
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="AT91SAM9G20")
|
|
base ad:0xfffc4000
|
|
width 0xC
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EMAC_NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit Halt" "No effect,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Transmission Start" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back Pressure" "No effect,Collisions"
|
|
bitfld.long 0x00 7. " WESTAT ,Statistics Registers Write Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Statistics Registers Increment" "No effect,Incremented"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Statistics Registers Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Loopback Local" "No loopback,Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LB ,Loopback" "No loopback,Loopback"
|
|
sif (cpu()=="AT91SAM9G46")
|
|
line.long 0x04 "EMAC_NCFG,Network Configuration Register"
|
|
else
|
|
line.long 0x04 "EMAC_NCFGR,Network Configuration Register"
|
|
endif
|
|
bitfld.long 0x04 19. " IRXFCS ,RX FCS Ignore" "Normal,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Half-Duplex Receive Frames Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DRFCS ,Receive FCS Discard" "Not discarded,Discarded"
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length Field Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " RBOF ,Receive Buffer Offset" "No offset,1-byte,2-byte,3-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry Test" "Normal,Retry"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC Clock Divider" "MCK/8,MCK/16,MCK/32,MCK/64"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BIG ,1536 Bytes Frames Receive" "Not received,Received"
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,All Frames Copy" "Not copied,Copied"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full Duplex Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mb/s,100 Mb/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMAC_NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic IDLE" "Running,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIO ,MDIO Pin Status" "Low,High"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "EMAC_TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No underrun,Underrun"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BEX ,Buffers Mid Frame Exhaust" "Not exhausted,Exhausted"
|
|
bitfld.long 0x00 3. " TGO ,Transmit Go" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25")
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
else
|
|
eventfld.long 0x00 2. " RLE ,Retry Limit Exceed" "Not exceeded,Exceeded"
|
|
endif
|
|
eventfld.long 0x00 1. " COL ,Collision Occurence" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "Not read,Read"
|
|
line.long 0x04 "EMAC_RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 4. " ADDR ,Receive Buffer Queue Pointer Address"
|
|
if (((data.long(ad:(0xfffc4000+0x14)))&0x8)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "EMAC_TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x0 2.--31. 4. " ADDR ,Transmit Buffer Queue Pointer Address"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "EMAC_RSR,Receive Status Register"
|
|
eventfld.long 0x0 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0 1. " REC ,Frame Receive" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x0 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x0 "EMAC_ISR,Interrupt Status Register"
|
|
in
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EMAC_IMR,Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT91CAP9")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " WOL_set/clr , Wake On LAN" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause Time Zero" "Enabled,Disabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PFR_set/clr ,Pause Frame Receive" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " HRESP_set/clr ,Hresp Not OK" "Enabled,Disabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive Overrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 07. -0x8 07. -0x4 7. " TCOMP_set/clr ,Transmit Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 06. -0x8 06. -0x4 6. " TXERR_set/clr ,Transmit Buffers Mid-Frame Exhaust Interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 05. -0x8 05. -0x4 5. " RLE_set/clr ,Retry Limit Exceed" "Enabled,Disabled"
|
|
setclrfld.long 0x0 04. -0x8 04. -0x4 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 03. -0x8 03. -0x4 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Enabled,Disabled"
|
|
setclrfld.long 0x0 02. -0x8 02. -0x4 2. " RXUBR_set/clr ,Receive Used Bit Read" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x0 01. -0x8 01. -0x4 1. " RCOMP_set/clr ,Receive Complete" "Enabled,Disabled"
|
|
setclrfld.long 0x0 00. -0x8 00. -0x4 0. " MFD_set/clr ,Management Frame Send" "Enabled,Disabled"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "EMAC_MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. " SOF ,Frame Start" "Not valid,Valid,Not valid,Not valid"
|
|
bitfld.long 0x0 28.--29. " RW ,Read/Write" "Reserved,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--27. 1. " PHYA ,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. " REGA ,Register Address"
|
|
textline " "
|
|
bitfld.long 0x0 16.--17. " CODE ,Code" "00,01,10,11"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,PHY Data"
|
|
line.long 0x4 "EMAC_PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "EMAC_HRB,Hash Register Bottom"
|
|
line.long 0x04 "EMAC_HRT,Hash Register Top"
|
|
tree "Specific Address Registers"
|
|
textline " "
|
|
group.long 0x98++0x1F
|
|
line.long 0x0 "EMAC_SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x4 "EMAC_SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x8 "EMAC_SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0xC "EMAC_SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x10 "EMAC_SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x14 "EMAC_SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
line.long 0x18 "EMAC_SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x1C "EMAC_SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Destination Address Most Significant Bits 32 to 47"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "EMAC_TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TID ,Type ID Checking"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "EMAC_USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Transceiver Input Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RMII ,RMII Operation Mode Enable" "MII,RMII"
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpu()=="AT91SAM9M10"||cpuis("AT9CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "EMAC_WOL, Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI , Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 , Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP , ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG , Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " IP , ARP request IP address"
|
|
endif
|
|
tree "EMAC Statistic Registers"
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "EMAC_PFR,Pause Frames Received Register"
|
|
in
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "EMAC_FTO,Frames Transmitted Ok Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x0 "EMAC_SCF,Single Collision Frames Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "EMAC_MCF,Multicollision Frames Register"
|
|
in
|
|
hgroup.long 0x4c++0x3
|
|
hide.long 0x0 "EMAC_FRO,Frames Received Ok Register"
|
|
in
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "EMAC_FCSE,Frames Check Sequence Errors Register"
|
|
in
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x0 "EMAC_ALE,Alignment Errors Register"
|
|
in
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x0 "EMAC_DTF,Deferred Transmission Frames Register"
|
|
in
|
|
hgroup.long 0x5c++0x3
|
|
hide.long 0x0 "EMAC_LCOL,Late Collisions Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_ECOL,Excessive Collisions Register"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "EMAC_EXCOL,Excessive Collisions Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "EMAC_TUND,Transmit Underrun Errors Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "EMAC_CSE,Carrier Sense Errors Register"
|
|
in
|
|
hgroup.long 0x6c++0x3
|
|
hide.long 0x0 "EMAC_RRE,Receive Resource Errors Register"
|
|
in
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9M11")
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROV,Receive Overrun Errors Register"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "EMAC_ROVR,Receive Overrun Errors Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x0 "EMAC_RSE,Receive Symbol Errors Register"
|
|
in
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x0 "EMAC_ELE,Excessive Length Errors Register"
|
|
in
|
|
hgroup.long 0x7c++0x3
|
|
hide.long 0x0 "EMAC_RJA,Receive Jabbers Register"
|
|
in
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x0 "EMAC_USF,Undersize Frames Register"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x0 "EMAC_STE,SQE Test Errors Register"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x0 "EMAC_RLE,Received Length Field Mismatch Register"
|
|
in
|
|
sif (cpu()!="AT91SAM9G46"&&cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25")
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G35"&&cpu()!="AT91SAM9G25"&&cpu()!="AT91SAM9G15")
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree.open "UHPHS OHCI (USB High Speed Host Port)"
|
|
base ad:0x00700000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00700000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00700000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "UHPHS EHCI (USB High Speed Host Port)"
|
|
base ad:0x00800000
|
|
width 12.
|
|
rgroup.word 0x00++0x01 "Host Controller Capability Registers"
|
|
line.word 0x00 "HCIVERSION,Version Of The EHCI Standard Register"
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "CAPLENGTH,Size Of The Entire Capability Register Area"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "HCSPARAMS,Host Controller Structure Parameters Register"
|
|
bitfld.long 0x00 20.--23. " DPN ,Debug Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " P_INDI ,Port Indicator" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRR ,Port Routing Rule" "N_PCC,HCSP-PORTROUTE"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,N_PORTS" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HCCPARAMS,Parameters Relating Host Controller Capabilities Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "Not cached,Reserved,2 microframes,Reserved,Reserved,Reserved,Reserved,Reserved,Entire frame,?..."
|
|
bitfld.long 0x04 2. " ASPC ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PFLF ,Programmable Frame List Flag" "Fixed 1024,Changed 512-256"
|
|
bitfld.long 0x04 0. " 64AC ,64-Bit Addressing Capability" "32-bit,64-bit"
|
|
width 16.
|
|
if (((data.long(ad:0x00800000+0x04))&0x80)==0x80)
|
|
;HCSPARAMS->PRR==1
|
|
rgroup.long 0x0c++0x07
|
|
line.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign Register"
|
|
line.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign Register"
|
|
else
|
|
hgroup.long 0x0c++0x07
|
|
hide.long 0x00 "HCSP-PORTROUTE0,Companion Host Controller Assign"
|
|
hide.long 0x04 "HCSP-PORTROUTE1,Companion Host Controller Assign"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x01B "Host Controller Operational Registers"
|
|
line.long 0x00 "USBCMD,USBCMD Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASPMC ,RO Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024,512,256,?..."
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
line.long 0x04 "USBSTS,Status Information Register"
|
|
bitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " R ,Reclamation" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HCH ,HC Halted" "Run/Stop==1,Run/Stop==0"
|
|
bitfld.long 0x04 5. " IAA ,Interrupt Async Advance" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " HSE ,Host System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLR ,Frame List Rollover" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PCD ,Port Change Detect" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " UEI ,USB Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "USBINTR,On/off Of Hardware Interrupts Register"
|
|
bitfld.long 0x08 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PCDE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " UEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " UIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FRINDEX, Current Frame Number Register"
|
|
hexmask.long.word 0x0C 0.--13. 1. " FI ,Frame Index"
|
|
width 18.
|
|
line.long 0x10 "CTRLDSSEGMENT,CTRLDSSEGMENT Register"
|
|
line.long 0x14 "PERIODICLISTBASE,Periodic Framelist Base Address Register"
|
|
hexmask.long 0x14 12.--31. 0x1000 " BA ,Base Address"
|
|
line.long 0x18 "ASYNCLISTADDR,Queue Heads Pointer"
|
|
hexmask.long 0x18 5.--31. 0x20 " LPL ,Link Pointer Low"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CONFIGFLAG,Ownership Specification Register"
|
|
bitfld.long 0x00 0. " CF ,Config Flag" "Each port to cHC,All ports to eHC"
|
|
if ((((data.long(ad:0x00800000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00800000+0x54))&0x5)==0x1))
|
|
;HCSPARAMS->P_INDICATOR==1 && this->PED==0 && this->CCS==1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((data.long(ad:0x00800000+0x04))&0x80000)==0x80000)&&(((data.long(ad:0x00800000+0x54))&0x5)!=0x1))
|
|
;HCSPARAMS->P_INDICATOR==1 && this->PED!=0 && this->CCS!=1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((data.long(ad:0x00800000+0x04))&0x80000)==0x00)&&(((data.long(ad:0x00800000+0x54))&0x5)==0x1))
|
|
;HCSPARAMS->P_INDICATOR==0 && this->PED==0 && this->CCS==1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
else
|
|
;HCSPARAMS->P_INDICATOR==0 && this->PED!=0 && this->CCS!=1
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "Not reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()!="AT91SAM9G46")
|
|
tree "UDPHS (USB High Speed Device Port)"
|
|
base ad:0xfff78000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UDPHS_CTRL,UDPHS Control Register"
|
|
bitfld.long 0x00 11. " PULLD_DIS , Pull-Down Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " REWAKEUP , Send Remote Wake Up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DETACH , Detach Command" "Attached,Detached"
|
|
bitfld.long 0x00 8. " EN_UDPHS , UDPHS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FADDR_EN , Function Address Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR , UDPHS Address"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UDPHS_FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x00 31. " FNUM_ERR , Frame Number CRC Error " "No error,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRAME_NUMBER , Frame Number as defined in the Packet Field Formats"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MICRO_FRAME_NUM , Microframe Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UDPHS_IEN,UDPHS Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 15. " EPT_7 , Endpoint 7 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SOF , SOF Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro-SOF Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "UDPHS_INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 15. " EPT_7 , Endpoint 7 Interrupt Enable" "No Interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPEED , Speed Status" "Full,High"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "UDPHS_CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "UDPHS_EPTRST,UDPHS Endpoints Reset Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
bitfld.long 0x04 7. " EPT_7 , Endpoint 7 Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " EPT_6 , Endpoint 6 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " EPT_5 , Endpoint 5 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EPT_4 , Endpoint 4 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 3. " EPT_3 , Endpoint 3 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EPT_2 , Endpoint 2 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 1. " EPT_1 , Endpoint 1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EPT_0 , Endpoint 0 Reset" "No effect,Reset"
|
|
group.long 0xe0++0x03
|
|
line.long 0x00 "UDPHS_TST,UDPHS Test Register"
|
|
bitfld.long 0x00 5. " OPMODE2 , OpMode2" "No effect,OpMode"
|
|
bitfld.long 0x00 4. " TST_PKT , Test Packet Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TST_K , Test K Mode" "No effect,Test"
|
|
bitfld.long 0x00 2. " TST_J , Test J Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SPEED_CFG , Speed Configuration" "Normal Mode,Reserved,High Speed,Full Speed"
|
|
sif (cpuis("AT91CAP9*"))
|
|
rgroup.long 0xf0++0xb
|
|
line.long 0x00 "UDPHS_IPNAME1,UDPHS Name1 Register"
|
|
line.long 0x04 "UDPHS_IPNAME2,UDPHS Name2 Register"
|
|
width 18.
|
|
line.long 0x08 "UDPHS_IPFEATURES,UDPHS Features Register"
|
|
bitfld.long 0x08 31. " ISO_EPT_15 ,Endpoint15 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 30. " ISO_EPT_14 ,Endpoint14 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ISO_EPT_13 ,Endpoint13 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 28. " ISO_EPT_12 ,Endpoint12 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ISO_EPT_11 ,Endpoint11 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 26. " ISO_EPT_10 ,Endpoint10 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ISO_EPT_9 ,Endpoint9 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 24. " ISO_EPT_8 ,Endpoint8 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ISO_EPT_7 ,Endpoint7 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 22. " ISO_EPT_6 ,Endpoint6 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ISO_EPT_5 ,Endpoint5 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 20. " ISO_EPT_4 ,Endpoint4 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ISO_EPT_3 ,Endpoint3 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 18. " ISO_EPT_2 ,Endpoint2 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 17. " ISO_EPT_1 ,Endpoint1 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 16. " DATAB16_8 ,UTMI DataBus16_8" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 15. " BW_DPRAM ,DPRAM Byte Write Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 12.--14. " FIFO_MAX_SIZE ,DPRAM Size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DMA_FIFO_DEPTH ,DMA FIFO Depth in Words" "16 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words"
|
|
bitfld.long 0x08 7. " DMA_B_SIZ ,DMA Buffer Size" "16 bits,24 bits"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " DMA_CHANNEL_NBR ,Number of DMA Channels" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--3. " EPT_NBR_MAX ,Max Number of Endpoints" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 19.
|
|
tree "Endpoint 0"
|
|
if ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x0))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x100)))&0x30)==0x20)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA0,UDPHS Endpoint Set Status Register 0"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA0,UDPHS Endpoint Clear Status Register 0"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x100)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x100)))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
if ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x120)))&0x30)==0x20)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x134++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA1,UDPHS Endpoint Set Status Register 1"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA1,UDPHS Endpoint Clear Status Register 1"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x120)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x120)))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
if ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x140)))&0x30)==0x20)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x154++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA2,UDPHS Endpoint Set Status Register 2"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA2,UDPHS Endpoint Clear Status Register 2"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x140)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x140)))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
if ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x160)))&0x30)==0x20)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x174++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA3,UDPHS Endpoint Set Status Register 3"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA3,UDPHS Endpoint Clear Status Register 3"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x160)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x160)))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
if ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x180)))&0x30)==0x20)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x194++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA4,UDPHS Endpoint Set Status Register 4"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA4,UDPHS Endpoint Clear Status Register 4"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x180)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x180)))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
if ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x20)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1B4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA5,UDPHS Endpoint Set Status Register 5"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA5,UDPHS Endpoint Clear Status Register 5"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1A0)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x1A0)))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
if ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "No effect,?..."
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "User,Hardware"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "No effect,Software,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "No bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x20)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G45")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_set/clr , NYET Disable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1D4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA6,UDPHS Endpoint Set Status Register 6"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA6,UDPHS Endpoint Clear Status Register 6"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleared"
|
|
if ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x10)&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:(0xfff78000+0x1C0)))&0x30)==(0x20||0x30))&&(((d.l(ad:(0xfff78000+0x1C0)))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "DMA channel 1"
|
|
group.long 0x310++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC1, UDPHS DMA Channel Address Register 1"
|
|
line.long 0x04 "UDPHS_DMAADDRESS1, UDPHS DMA Next Descriptor Address Register 1"
|
|
line.long 0x08 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x310+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS1,UDPHS DMA Channel Status Register 1"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x320++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC2, UDPHS DMA Channel Address Register 2"
|
|
line.long 0x04 "UDPHS_DMAADDRESS2, UDPHS DMA Next Descriptor Address Register 2"
|
|
line.long 0x08 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x320+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS2,UDPHS DMA Channel Status Register 2"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x330++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC3, UDPHS DMA Channel Address Register 3"
|
|
line.long 0x04 "UDPHS_DMAADDRESS3, UDPHS DMA Next Descriptor Address Register 3"
|
|
line.long 0x08 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x330+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS3,UDPHS DMA Channel Status Register 3"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x340++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC4, UDPHS DMA Channel Address Register 4"
|
|
line.long 0x04 "UDPHS_DMAADDRESS4, UDPHS DMA Next Descriptor Address Register 4"
|
|
line.long 0x08 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x340+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS4,UDPHS DMA Channel Status Register 4"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x350++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC5, UDPHS DMA Channel Address Register 5"
|
|
line.long 0x04 "UDPHS_DMAADDRESS5, UDPHS DMA Next Descriptor Address Register 5"
|
|
line.long 0x08 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x350+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS5,UDPHS DMA Channel Status Register 5"
|
|
in
|
|
tree.end
|
|
sif (cpuis("AT91CAP9*"))
|
|
tree "DMA channel 6"
|
|
group.long 0x360++0xb
|
|
line.long 0x00 "UDPHS_DMANXTDSC6, UDPHS DMA Channel Address Register 6"
|
|
line.long 0x04 "UDPHS_DMAADDRESS6, UDPHS DMA Next Descriptor Address Register 6"
|
|
line.long 0x08 "UDPHS_DMACONTROL6, UDPHS DMA Channel Control Register 6"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
hgroup.long (0x360+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS6,UDPHS DMA Channel Status Register 6"
|
|
in
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "UDPHS (USB High Speed Device Port)"
|
|
base ad:0xfff78000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UDPHS_CTRL,UDPHS Control Register"
|
|
bitfld.long 0x00 11. " PULLD_DIS , Pull-Down Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " REWAKEUP , Send Remote Wake Up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DETACH , Detach Command" "Attached,Detached"
|
|
bitfld.long 0x00 8. " EN_UDPHS , UDPHS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FADDR_EN , Function Address Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR , UDPHS Address"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UDPHS_FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x00 31. " FNUM_ERR , Frame Number CRC Error " "No error,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRAME_NUMBER , Frame Number as defined in the Packet Field Formats"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MICRO_FRAME_NUM , Microframe Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UDPHS_IEN,UDPHS Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SOF , SOF Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro-SOF Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "UDPHS_INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_INT_6 , DMA Channel 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DMA_INT_5 , DMA Channel 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_INT_4 , DMA Channel 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " DMA_INT_3 , DMA Channel 3 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DMA_INT_2 , DMA Channel 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " DMA_INT_1 , DMA Channel 1 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EPT_6 , Endpoint 6 Interrupt " "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EPT_5 , Endpoint 5 Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EPT_4 , Endpoint 4 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EPT_3 , Endpoint 3 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EPT_2 , Endpoint 2 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " EPT_1 , Endpoint 1 Interrupt " "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPT_0 , Endpoint 0 Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt" "No Interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt" "No Interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPEED , Speed Status" "Full,High"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "UDPHS_CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x00 7. " UPSTR_RES , Upstream Resume Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ENDOFRSM , End Of Resume Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKE_UP , Wake Up CPU Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ENDRESET , End Of Reset Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_SOF , Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " MICRO_SOF , Micro Start Of Frame Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DET_SUSPD , Suspend Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "UDPHS_EPTRST,UDPHS Endpoints Reset Register"
|
|
bitfld.long 0x04 6. " EPT_6 , Endpoint 6 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " EPT_5 , Endpoint 5 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EPT_4 , Endpoint 4 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 3. " EPT_3 , Endpoint 3 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EPT_2 , Endpoint 2 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 1. " EPT_1 , Endpoint 1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EPT_0 , Endpoint 0 Reset" "No effect,Reset"
|
|
group.long 0xe0++0x03
|
|
line.long 0x00 "UDPHS_TST,UDPHS Test Register"
|
|
bitfld.long 0x00 5. " OPMODE2 , OpMode2" "No effect,OpMode"
|
|
bitfld.long 0x00 4. " TST_PKT , Test Packet Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TST_K , Test K Mode" "No effect,Test"
|
|
bitfld.long 0x00 2. " TST_J , Test J Mode" "No effect,Test"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SPEED_CFG , Speed Configuration" "Normal Mode,Reserved,High Speed,Full Speed"
|
|
width 18.
|
|
rgroup.long 0xf0++0xb
|
|
line.long 0x00 "UDPHS_IPNAME1,UDPHS Name1 Register"
|
|
line.long 0x04 "UDPHS_IPNAME2,UDPHS Name2 Register"
|
|
line.long 0x08 "UDPHS_IPFEATURES,UDPHS Features Register"
|
|
bitfld.long 0x08 31. " ISO_EPT_15 ,Endpoint15 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 30. " ISO_EPT_14 ,Endpoint14 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ISO_EPT_13 ,Endpoint13 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 28. " ISO_EPT_12 ,Endpoint12 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ISO_EPT_11 ,Endpoint11 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 26. " ISO_EPT_10 ,Endpoint10 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ISO_EPT_9 ,Endpoint9 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 24. " ISO_EPT_8 ,Endpoint8 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ISO_EPT_7 ,Endpoint7 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 22. " ISO_EPT_6 ,Endpoint6 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ISO_EPT_5 ,Endpoint5 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 20. " ISO_EPT_4 ,Endpoint4 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ISO_EPT_3 ,Endpoint3 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 18. " ISO_EPT_2 ,Endpoint2 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x08 17. " ISO_EPT_1 ,Endpoint1 High Bandwidth Isochronous Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 16. " DATAB16_8 ,UTMI DataBus16_8" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 15. " BW_DPRAM ,DPRAM Byte Write Capability" "Not implemented,Implemented"
|
|
bitfld.long 0x08 12.--14. " FIFO_MAX_SIZE ,DPRAM Size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DMA_FIFO_DEPTH ,DMA FIFO Depth in Words" "16 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words"
|
|
bitfld.long 0x08 7. " DMA_B_SIZ ,DMA Buffer Size" "16 bits,24 bits"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " DMA_CHANNEL_NBR ,Number of DMA Channels" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--3. " EPT_NBR_MAX ,Max Number of Endpoints" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 19.
|
|
tree "Endpoint 0"
|
|
if ((((d.l(ad:0xfff78000+0x100))&0x30)==0x0))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x100))&0x30)==0x10))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG0,UDPHS Endpoint Configuration Register 0"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x100))&0x30)==0x20)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x100))&0x30)==0x10)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL0,UDPHS Endpoint Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA0,UDPHS Endpoint Set Status Register 0"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA0,UDPHS Endpoint Clear Status Register 0"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x100))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x100))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x100))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x100))&0x8)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x100))&0x30)==0x0))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x100))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x100))&0x8)==0x8))
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA0,UDPHS Endpoint Status Register 0"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
if ((((d.l(ad:0xfff78000+0x120))&0x30)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x120))&0x30)==0x10))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG1,UDPHS Endpoint Configuration Register 1"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x120))&0x30)==0x20)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x120))&0x30)==0x10)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL1,UDPHS Endpoint Set/Clr Register 1"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x134++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA1,UDPHS Endpoint Set Status Register 1"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA1,UDPHS Endpoint Clear Status Register 1"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x120))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x120))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x120))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x120))&0x8)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x120))&0x30)==0x0))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x120))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x120))&0x8)==0x8))
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x13C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA1,UDPHS Endpoint Status Register 1"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
if ((((d.l(ad:0xfff78000+0x140))&0x30)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x140))&0x30)==0x10))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG2,UDPHS Endpoint Configuration Register 2"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x140))&0x30)==0x20)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x140))&0x30)==0x10)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL2,UDPHS Endpoint Set/Clr Register 2"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x154++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA2,UDPHS Endpoint Set Status Register 2"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA2,UDPHS Endpoint Clear Status Register 2"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x140))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x140))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x140))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x140))&0x8)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x140))&0x30)==0x0))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x140))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x140))&0x8)==0x8))
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x15C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA2,UDPHS Endpoint Status Register 2"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
if ((((d.l(ad:0xfff78000+0x160))&0x30)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x160))&0x30)==0x10))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG3,UDPHS Endpoint Configuration Register 3"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x160))&0x30)==0x20)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x160))&0x30)==0x10)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL3,UDPHS Endpoint Set/Clr Register 3"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x174++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA3,UDPHS Endpoint Set Status Register 3"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA3,UDPHS Endpoint Clear Status Register 3"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x160))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x160))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x160))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x160))&0x8)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x160))&0x30)==0x0))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x160))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x160))&0x8)==0x8))
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x17C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA3,UDPHS Endpoint Status Register 3"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
if ((((d.l(ad:0xfff78000+0x180))&0x30)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x180))&0x30)==0x10))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG4,UDPHS Endpoint Configuration Register 4"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x180))&0x30)==0x20)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x180))&0x30)==0x10)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL4,UDPHS Endpoint Set/Clr Register 4"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x194++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA4,UDPHS Endpoint Set Status Register 4"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA4,UDPHS Endpoint Clear Status Register 4"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x180))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x180))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x180))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x180))&0x8)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x180))&0x30)==0x0))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x180))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x180))&0x8)==0x8))
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA4,UDPHS Endpoint Status Register 4"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
if ((((d.l(ad:0xfff78000+0x1A0))&0x30)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x1A0))&0x30)==0x10))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG5,UDPHS Endpoint Configuration Register 5"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x1A0))&0x30)==0x20)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x1A0))&0x30)==0x10)
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL5,UDPHS Endpoint Set/Clr Register 5"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1B4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA5,UDPHS Endpoint Set Status Register 5"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA5,UDPHS Endpoint Clear Status Register 5"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x1A0))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x1A0))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1A0))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x1A0))&0x8)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1A0))&0x30)==0x0))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1A0))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x1A0))&0x8)==0x8))
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1BC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA5,UDPHS Endpoint Status Register 5"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
if ((((d.l(ad:0xfff78000+0x1C0))&0x30)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
elif ((((d.l(ad:0xfff78000+0x1C0))&0x30)==0x10))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDPHS_EPTCFG6,UDPHS Endpoint Configuration Register 6"
|
|
bitfld.long 0x00 31. " EPT_MAPD , Endpoint Mapped" "0,1"
|
|
bitfld.long 0x00 8.--9. " NB_TRANS , Number Of Transaction per Microframe" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BK_NUMBER , Number of Banks" "Zero bank,One bank,Double bank,Triple bank"
|
|
bitfld.long 0x00 4.--5. " EPT_TYPE , Endpoint Type " "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPT_DIR , Endpoint Direction" "Out,In"
|
|
bitfld.long 0x00 0.--2. " EPT_SIZE , Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,?..."
|
|
endif
|
|
if (((d.l(ad:0xfff78000+0x1C0))&0x30)==0x20)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " NYET_DIS_set/clr , NYET Disable" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xfff78000+0x1C0))&0x30)==0x10)
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " MDATA_RX_set/clr ,MDATA Interrupt " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DATAX_RX_set/clr ,DATAX_RX, DATAx Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UDPHS_EPTCTL6,UDPHS Endpoint Set/Clr Register 6"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " SHRT_PCKT_set/clr ,Short Packet Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " BUSY_BANK_set/clr ,Busy Bank Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NAK_OUT_set/clr , NAKOUT Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NAK_IN/ERR_FLUSH_set/clr , NAKIN/bank flush error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " STALL_SNT/ERR_CRISO/ERR_NBTRA_set/clr , Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RX_SETUP/ERR_FL_ISO_set/clr ,Received SETUP/Error Flow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TX_PK_RDY/ERR_TRANS_set/clr ,TX Packet Ready/Transaction Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TX_COMPLT_set/clr ,Transmitted IN Data Complete Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RX_BK_RDY_set/clr ,Received OUT Data Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ERR_OVFLW_set/clr ,Overflow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INTDIS_DMA_set/clr ,Interrupts DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " AUTO_VALID_set/clr ,Packet Auto-Valid" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EPT_ENABL_set/clr ,Endpoint" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1D4++0x7
|
|
line.long 0x00 "UDPHS_EPTSETSTA6,UDPHS Endpoint Set Status Register 6"
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready Set" "No effect,Packet Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank Set (for IN Endpoint)" "No effect,KILL Bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRCESTALL ,Stall Handshake Request Set" "No effect,Request a STALL"
|
|
line.long 0x04 "UDPHS_EPTCLRSTA6,UDPHS Endpoint Clear Status Register 6"
|
|
bitfld.long 0x04 15. " NAK_OUT , NAKOUT Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NAK_IN/ERR_FLUSH , NAKIN/Bank Flush Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 13. " STALL_SNT/ERR_NBTRA , Stall Sent/Number of Transaction Error Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_SETUP/ERR_FL_ISO , Received SETUP/Error Flow Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TX_COMPLT , Transmitted IN Data Complete Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX_BK_RDY , Received OUT Data Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TOGGLESQ , Data Toggle Clear" "No effect,Cleare"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FRCESTALL , Stall Handshake Request Clear" "No effect,Cleare"
|
|
if ((((d.l(ad:0xfff78000+0x1C0))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x1C0))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ERR_FLUSH ,Bank Flush Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_NBTRA , Number of Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY ,TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1C0))&0x30)==0x10)&&(((d.l(ad:0xfff78000+0x1C0))&0x8)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN ,NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR_CRISO , CRC ISO Error" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ERR_FL_ISO , Error Flow" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERR_TRANS ,Transaction Error" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,Data 2,MData"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1C0))&0x30)==0x0))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CONTROL_DIR ,Control Direction" "Write,Read,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RX_SETUP , Received SETUP" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RDY , Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
elif ((((d.l(ad:0xfff78000+0x1C0))&0x30)==(0x20||0x30))&&(((d.l(ad:0xfff78000+0x1C0))&0x8)==0x8))
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent " "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " KILL_BANK , KILL Bank" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "0,1,2,3"
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
else
|
|
rgroup.long 0x1DC++0x3
|
|
line.long 0x00 "UDPHS_EPTSTA6,UDPHS Endpoint Status Register 6"
|
|
bitfld.long 0x00 31. " SHRT_PCKT , Short Packet" "Not detected,Detected"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYTE_COUNT , UDPHS Byte Count"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " BUSY_BANK_STA , Busy Bank Number" "All free,1 busy,2 busy,3 busy"
|
|
bitfld.long 0x00 16.--17. " CURRENT_BANK , Current Bank" "Bank 0,Bank 1,Bank 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " NAK_OUT , NAK OUT" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " NAK_IN , NAK IN" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STALL_SNT , Stall Sent" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_PK_RDY , TX Packet Ready" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " TX_COMPLT , Transmitted IN Data Complete" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX_BK_RD ,Received OUT Data" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ERR_OVFLW , Overflow Error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TOGGLESQ_STA , Toggle Sequencing" "Data 0,Data 1,?..."
|
|
bitfld.long 0x00 5. " FRCESTALL , Stall Handshake Request" "No effect,Request"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "DMA channel 1"
|
|
group.long 0x320++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC1,UDPHS DMA Next Descriptor Address Register 1"
|
|
line.long 0x04 "UDPHS_DMAADDRESS1,UDPHS DMA Channel Address Register 1"
|
|
if ((d.l(ad:0xfff78000+0x100)&0x8)==0x0)
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL1, UDPHS DMA Channel Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x320+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS1,UDPHS DMA Channel Status Register 1"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x330++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC2,UDPHS DMA Next Descriptor Address Register 2"
|
|
line.long 0x04 "UDPHS_DMAADDRESS2,UDPHS DMA Channel Address Register 2"
|
|
if ((d.l(ad:0xfff78000+0x120)&0x8)==0x0)
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL2, UDPHS DMA Channel Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x330+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS2,UDPHS DMA Channel Status Register 2"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x340++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC3,UDPHS DMA Next Descriptor Address Register 3"
|
|
line.long 0x04 "UDPHS_DMAADDRESS3,UDPHS DMA Channel Address Register 3"
|
|
if ((d.l(ad:0xfff78000+0x140)&0x8)==0x0)
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL3, UDPHS DMA Channel Control Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x340+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS3,UDPHS DMA Channel Status Register 3"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x350++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC4,UDPHS DMA Next Descriptor Address Register 4"
|
|
line.long 0x04 "UDPHS_DMAADDRESS4,UDPHS DMA Channel Address Register 4"
|
|
if ((d.l(ad:0xfff78000+0x160)&0x8)==0x0)
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL4, UDPHS DMA Channel Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x350+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS4,UDPHS DMA Channel Status Register 4"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x360++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC5,UDPHS DMA Next Descriptor Address Register 5"
|
|
line.long 0x04 "UDPHS_DMAADDRESS5,UDPHS DMA Channel Address Register 5"
|
|
if ((d.l(ad:0xfff78000+0x180)&0x8)==0x0)
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL5, UDPHS DMA Channel Control Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x360+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS5,UDPHS DMA Channel Status Register 5"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 6"
|
|
group.long 0x370++0x7
|
|
line.long 0x00 "UDPHS_DMANXTDSC6,UDPHS DMA Next Descriptor Address Register 6"
|
|
line.long 0x04 "UDPHS_DMAADDRESS6,UDPHS DMA Channel Address Register 6"
|
|
if ((d.l(ad:0xfff78000+0x1A0)&0x8)==0x0)
|
|
group.long (0x370+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL6, UDPHS DMA Channel Control Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " END_TR_EN , End of Transfer Enable (Control)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
else
|
|
group.long (0x370+0x08)++0x03
|
|
line.long 0x00 "UDPHS_DMACONTROL6, UDPHS DMA Channel Control Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH , Buffer Byte Length"
|
|
bitfld.long 0x00 7. " BURST_LCK , Burst Lock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DESC_LD_IT , Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT , End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TR_IT , End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN , End of Buffer Enable (Control)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LDNXT_DSC , Load Next Channel Transfer Descriptor Enable (Command)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANN_ENB , Channel Enable Command" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long (0x370+0xc)++0x3
|
|
hide.long 0x00 "UDPHS_DMASTATUS6,UDPHS DMA Channel Status Register 6"
|
|
in
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
else
|
|
tree "UDP (USB Device Port)"
|
|
base ad:0xfffa4000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register"
|
|
bitfld.long 0x00 17. " FRM_OK ,Frame OK" "SOF_PID,SOF_EOP"
|
|
bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FRM_NUM[10:0] ,Frame Number as Defined In the Packet Field Formats"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "UDP_GLB_STAT,UDP Global State Register"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G20")
|
|
bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RSMINPR ,A Resume Has Been Sent to the Host" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ESR ,Enable Send Resume" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " CONFG ,Configured" "Not configured,Configured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Disabled,Enabled"
|
|
line.long 0x4 "UDP_FADDR,UDP Function Address Register"
|
|
bitfld.long 0x4 8. " FEN ,Function Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--6. 1. " FADD[6:0] ,Function Address Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "UDP_IMR,UDP Interrupt Mask Register"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G10")
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " WAKEUP_set/clr ,USB Bus WAKEUP Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BIT12 ,UDP_IMR Bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " SOFINT_set/clr ,Mask Start Of Frame Interrupt" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " EXTRSM_set/clr ,Mask UDP External Resume Interrupt" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " RXRSM_set/clr ,Mask UDP Resume Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " RXSUSP_set/clr ,Mask UDP Suspend Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " EP5INT_set/clr ,Mask Endpoint 5 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " EP4INT_set/clr ,Mask Endpoint 4 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " EP3INT_set/clr ,Mask Endpoint 3 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EP2INT_set/clr ,Mask Endpoint 2 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " EP1INT_set/clr ,Mask Endpoint 1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " EP0INT_set/clr ,Mask Endpoint 0 Interrupt" "Disabled,Enabled"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "UDP_ISR,UDP Interrupt Status Register"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x0 13. " WAKEUP ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " SOFINT ,Start of Frame Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x0 10. " EXTRSM ,UDP External Resume Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 9. " RXRSM ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RXSUSP ,UDP Suspend Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 5. " EP5INT ,Endpoint 5 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 4. " EP4INT ,Endpoint 4 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 3. " EP3INT ,Endpoint 3 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 2. " EP2INT ,Endpoint 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 1. " EP1INT ,Endpoint 1 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 0. " EP0INT ,Endpoint 0 Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G10")
|
|
bitfld.long 0x0 13. " WAKEUP ,Clear Wakeup Interrupt" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ENDBUSRES ,Clear End of BUS Reset Interrupt" "No effect,Clear"
|
|
bitfld.long 0x0 11. " SOFINT ,Clear Start Of Frame Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXRSM ,Clear UDP Resume Interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RXSUSP ,Clear UDP Suspend Interrupt" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register"
|
|
bitfld.long 0x00 5. " EP5 ,Reset Endpoint 5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " EP4 ,Reset Endpoint 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EP3 ,Reset Endpoint 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EP2 ,Reset Endpoint 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP1 ,Reset Endpoint 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " EP0 ,Reset Endpoint 0" "No reset,Reset"
|
|
width 0xA
|
|
tree "Endpoint Control and Status Registers"
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x000)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x500))
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x700))
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x0)))&0x700)==0x400)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x000)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x500))
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x700))
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x4)))&0x700)==0x400)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x000)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x500))
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x700))
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x8)))&0x700)==0x400)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x000)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x500))
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x700))
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0xC)))&0x700)==0x400)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x000)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x500))
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x700))
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x10)))&0x700)==0x400)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x000)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x100)||(((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x500))
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x300)||(((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x700))
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
sif (cpu()!="AT91SAM9N12")
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif (((d.l(ad:(0xfffa4000+0x30+0x14)))&0x700)==0x400)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous OUT,Bulk OUT,Interrupt OUT,Reserved,Isochronous IN,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Sends STALL to the Host" "Not sent,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
tree.end
|
|
tree "UDP Endpoint FIFO Data Registers"
|
|
textline " "
|
|
hgroup.long 0x50++0x17
|
|
hide.long 0x0 "UDP_FDR0,UDP Endpoint 0 FIFO Data Register"
|
|
in
|
|
hide.long 0x4 "UDP_FDR1,UDP Endpoint 1 FIFO Data Register"
|
|
in
|
|
hide.long 0x8 "UDP_FDR2,UDP Endpoint 2 FIFO Data Register"
|
|
in
|
|
hide.long 0xC "UDP_FDR3,UDP Endpoint 3 FIFO Data Register"
|
|
in
|
|
hide.long 0x10 "UDP_FDR4,UDP Endpoint 4 FIFO Data Register"
|
|
in
|
|
hide.long 0x14 "UDP_FDR5,UDP Endpoint 5 FIFO Data Register"
|
|
in
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
base ad:0xfffa4000
|
|
tree.end
|
|
textline " "
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register"
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9G20")
|
|
bitfld.long 0x00 9. " PUON ,Pullup On" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "No,Yes"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "UHP (USB Host Port)"
|
|
base ad:0x00500000
|
|
width 20.
|
|
tree "Control and Status Partition"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote Wakeup Connected" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IR ,Interrupt Routing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control Bulk Service Ratio (Control/Bulk)" "1 : 1,2 : 1,3 : 1,4 : 1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
width 20.
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
eventfld.long 0x00 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "HCINTERRUPTENABLE,HcInterruptEnable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " OC ,OC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,RHSC Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,FNO Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,UE Interrupt Enable" "Inore,Enabled"
|
|
bitfld.long 0x00 3. " RD ,RD Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 2. " SF ,SF Interrupt Enable" "Ignore,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,WDH Interrupt Enable" "Ignore,Enabled"
|
|
bitfld.long 0x00 0. " SO ,SO Interrupt Enable" "Ignore,Enabled"
|
|
line.long 0x04 "HCINTERRUPTDISABLE,HcInterruptDisable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 30. " OC ,OC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 6. " RHSC ,RHSC Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 5. " FNO ,FNO Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,UE Interrupt Disable" "Inore,Disabled"
|
|
bitfld.long 0x04 3. " RD ,RD Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 2. " SF ,SF Interrupt Disable" "Ignore,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,WDH Interrupt Disable" "Ignore,Disabled"
|
|
bitfld.long 0x04 0. " SO ,SO Interrupt Disable" "Ignore,Disabled"
|
|
tree.end
|
|
tree "Memory Pointer Partition"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "HCHCCA,Hc HCCA Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
line.long 0x04 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PCED ,Period Current ED"
|
|
line.long 0x08 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " CHED ,Control Head ED"
|
|
line.long 0x0c "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " CCED ,Control Current ED"
|
|
line.long 0x10 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x10 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
line.long 0x14 "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x14 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Done Head"
|
|
tree.end
|
|
width 17.
|
|
tree "Frame Counter Partition"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame Interval"
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,LS Threshold"
|
|
tree.end
|
|
width 20.
|
|
tree "Root Hub Partition"
|
|
if (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x0)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x1000)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x00 11. " OCPM ,Over Current Protection Mode" "All protected,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
elif (((d.l(ad:(0x00500000+0x48)))&0x1100)==0x100)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 9. " PSM ,Power Switching Mode" "Same time,Individually"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x00 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DT ,Device Type" "No device,Device"
|
|
bitfld.long 0x00 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
endif
|
|
width 20.
|
|
if (((d.l(ad:(0x00500000+0x48)))&0x200)==0x200)
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 31. " PPCM[15] ,Port Power Control Mask[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " PPCM[14] ,Port Power Control Mask[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PPCM[13] ,Port Power Control Mask[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " PPCM[12] ,Port Power Control Mask[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PPCM[11] ,Port Power Control Mask[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " PPCM[10] ,Port Power Control Mask[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPCM[9] ,Port Power Control Mask[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " PPCM[8] ,Port Power Control Mask[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PPCM[7] ,Port Power Control Mask[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " PPCM[6] ,Port Power Control Mask[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCM[5] ,Port Power Control Mask[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " PPCM[4] ,Port Power Control Mask[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port Power Control Mask[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port Power Control Mask[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port Power Control Mask[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
else
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
bitfld.long 0x00 15. " DR[15] ,Device Removable[15]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 14. " DR[14] ,Device Removable[14]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DR[13] ,Device Removable[13]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 12. " DR[12] ,Device Removable[12]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DR[11] ,Device Removable[11]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 10. " DR[10] ,Device Removable[10]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR[9] ,Device Removable[9]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 8. " DR[8] ,Device Removable[8]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR[7] ,Device Removable[7]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 6. " DR[6] ,Device Removable[6]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DR[5] ,Device Removable[5]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 4. " DR[4] ,Device Removable[4]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DR[3] ,Device Removable[3]" "Removabled,Not removabled"
|
|
bitfld.long 0x00 2. " DR[2] ,Device Removable[2]" "Removabled,Not removabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DR[1] ,Device Removable[1]" "Removabled,Not removabled"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CCIC ,Over Current Indicator Change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local Power Status Change/Set Global Power" "No effect,On all ports"
|
|
bitfld.long 0x00 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Over Current Indicator" "Low,High"
|
|
bitfld.long 0x00 0. " LPS ,Local Power Status/Clear Global Power" "No effect,Off all ports"
|
|
width 20.
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[0],Hc Rh Port Status [0]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[1],Hc Rh Port Status [1]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[2],Hc Rh Port Status [2]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[3],Hc Rh Port Status [3]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[4],Hc Rh Port Status [4]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[5],Hc Rh Port Status [5]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[6],Hc Rh Port Status [6]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[7],Hc Rh Port Status [7]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[8],Hc Rh Port Status [8]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[9],Hc Rh Port Status [9]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[10],Hc Rh Port Status [10]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[11],Hc Rh Port Status [11]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[12],Hc Rh Port Status [12]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[13],Hc Rh Port Status [13]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS[14],Hc Rh Port Status [14]"
|
|
eventfld.long 0x00 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x00 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Low Speed Device Attached/Clear Port Power" "Full/No effect,Low/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port Power Status/Set Port Power" "Off/No effect,On/Set"
|
|
bitfld.long 0x00 4. " PRS ,Port Reset Status/Set Port Reset" "Not active/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI ,Port Over Current Indicator/Clear Suspend Status" "Not detected/No effect,Detected/Clear"
|
|
bitfld.long 0x00 2. " PSS ,Port Suspend Status/Set Port Suspend" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES ,PortEnableStatus/SetPortEnable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status/Clear Port Enable" "Not connected/No effect,Connected/Clear"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "ISI (Image Sensor Interface)"
|
|
sif (cpu()=="AT91SAM9G20")
|
|
base ad:0xfffc0000
|
|
width 0xe
|
|
group.long 0x00++7
|
|
line.long 0x00 "ISI_CR1,ISI Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CODEC_ON ,Enable the codec path enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4/8/16,8/16,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " ISI_DIS ,Image sensor disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ISI_RST ,Image sensor interface reset" "No action,Reset"
|
|
line.long 0x04 "ISI_CR2,ISI Control 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,Defines RGB pattern when RGB_MODE is set to 1" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,Defines the YCC image data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
rgroup.long 0x08++3
|
|
line.long 0x00 "SI_SR,ISI Status Register"
|
|
bitfld.long 0x00 9. " FR_OVR ,Frame rate overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " FO_C_EMP ,DMA transfer of the preview FIFO finished" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FO_P_EMP ,DMA transfer of the codec FIFO finished" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " FO_P_OVF ,FIFO preview overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FO_C_OVF ,FIFO codec overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " CRC_ERR ,CRC synchronization error" "No error,Error"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9XE128"||cpu()=="AT91SAM9XE256"||cpu()=="AT91SAM9XE512"||cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 3. " CDC_PND , Codec request pending" "Not requested,Requested"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SOFTRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " DIS ,Image Sensor Interface disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOF ,Start of frame" "Not detected,Detected"
|
|
group.long 0x14++3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " FR_OVR_set/clr ,Frame overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " FO_C_EMP_set/clr ,Codec FIFO Empty" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " FO_P_EMP_set/clr ,Preview FIFO Empty" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FO_P_OVF_set/clr ,FIFO preview Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " FO_C_OVF_set/clr ,FIFO codec Overflow" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CRC_ERR_set/clr ,CRC synchronization error" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SOFTRST_set/clr ,Soft Reset" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_set/clr ,Image Sensor Interface disable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_set/clr ,Start of Frame" "Disabled,Enabled"
|
|
group.long 0x20++0x23
|
|
line.long 0x00 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x00 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x00 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x04 "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x08 "ISI_PPFBD,ISI Preview Primary FBD Register"
|
|
line.long 0x0c "ISI_CDBA,ISI Codec DMA Base Address Register"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI CSC YCrCb To RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI CSC YCrCb To RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI CSC RGB To YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI CSC RGB To YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI CSC RGB To YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0xfffb4000
|
|
width 14.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "ISI_CFG1,ISI Configuration 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4 beats,4/8 beats,4/8/16 beats,?..."
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DISCR ,Disable Codec Request" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
line.long 0x04 "ISI_CFG2,ISI Configuration 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,RGB Pattern" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,YCC Image Data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
line.long 0x08 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x08 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x08 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x0c "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI Color Space Conversion YCrCb to RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI Color Space Conversion YCrCb to RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI Color Space Conversion RGB to YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI Color Space Conversion RGB to YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI Color Space Conversion RGB to YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "ISI_CTRL,ISI Control Register"
|
|
bitfld.long 0x00 8. " ISI_CDC ,ISI Codec Request" "No effect,Enable"
|
|
bitfld.long 0x00 2. " ISI_SRST ,ISI Software Reset Request" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISI_DIS ,ISI Module Disable Request" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ISI_EN ,ISI Module Enable Request" "No effect,Enable"
|
|
hgroup.long 0x28++0x3
|
|
sif (cpu()=="AT91SAMG25"||cpu()=="AT91SAMG46")
|
|
hide.long 0x00 "ISI_SR,ISI Status Register"
|
|
in
|
|
else
|
|
hide.long 0x00 "ISI_STATUS,ISI Status Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " FR_OVR_set/clr ,Frame Rate Overrun Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " CRC_ERR_set/clr ,CRC Synchronization Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " C_OVR_set/clr ,FIFO Codec Overflow Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " P_OVR_set/clr ,FIFO Preview Overflow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " CXFR_DONE_set/clr ,Codec DMA Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " PXFR_DONE_set/clr ,Preview DMA Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " VSYNC_set/clr ,Vertical Synchronization Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SRST_set/clr ,Software Reset Completed Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_DONE_set/clr ,Module Disable Request Termination Interrupt" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DMA_CHSR,DMA Channel Status Register"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " C_CH_S_set/clr ,Preview DMA channel" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " P_CH_S_set/clr ,Codec DMA channel" "Disabled,Enabled"
|
|
group.long 0x44++0x17
|
|
line.long 0x00 "DMA_P_ADDR,DMA Preview Base Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " P_ADDR ,Preview Image Base Address"
|
|
line.long 0x04 "DMA_P_CTRL ,DMA Preview Control Register"
|
|
bitfld.long 0x04 3. " P_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " P_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " P_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x08 "DMA_P_DSCR,DMA Preview Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x4 " P_DSCR ,Preview Descriptor Base Address"
|
|
line.long 0x0c "DMA_C_ADDR,DMA Codec Base Address Register"
|
|
sif (cpu()=="AT91SAMG46"||cpu()=="AT91SAMG25")
|
|
hexmask.long 0x0c 2.--31. 0x4 " C_ADDR ,Codec Image Base Address"
|
|
else
|
|
hexmask.long 0x0c 2.--31. 0x4 " C_ADDR ,Preview Image Base Address"
|
|
endif
|
|
line.long 0x10 "DMA_C_CTRL ,DMA Codec Control Register"
|
|
bitfld.long 0x10 3. " C_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x10 2. " C_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " C_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " C_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x14 "DMA_C_DSCR,DMA Codec Descriptor Address Register"
|
|
hexmask.long 0x14 2.--31. 0x4 " C_DSCR ,Codec Descriptor Base Address"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "ISI_WPCR,ISI Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "ISI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G25")
|
|
base ad:0xF8048000
|
|
width 14.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "ISI_CFG1,ISI Configuration 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of Frame Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of Line Delay"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "4 beats,4/8 beats,4/8/16 beats,?..."
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DISCR ,Disable Codec Request" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate captured" "All,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization" "No CRC,CRC"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising,Falling"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
line.long 0x04 "ISI_CFG2,ISI Configuration 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,RGB Pattern" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,YCC Image Data" "Default,Mode1,Mode2,Mode3"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--26. 1. " IM_HSIZE ,Horizontal size of the Image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
textline " "
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB Swap" "D7 -> R7,D0 -> R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Gray Scale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8 24 bits,5:6:5 16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,GS Mode" "2 pixels per word,1 pixel per word"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. " IM_VSIZE ,Vertical size of the Image sensor"
|
|
line.long 0x08 "ISI_PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x08 16.--25. 1. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x08 0.--9. 1. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x0c "ISI_PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x10 "ISI_Y2R_SET0,ISI Color Space Conversion YCrCb to RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color Space Conversion Matrix Coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "ISI_Y2R_SET1,ISI Color Space Conversion YCrCb to RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " Cboff ,Color Space Conversion Blue Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " Croff ,Color Space Conversion Red Chrominance default offset" "No offset,Offset=16"
|
|
textline " "
|
|
bitfld.long 0x14 12. " Yoff ,Color Space Conversion Luminance default offset" "No offset,Offset=128"
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
line.long 0x18 "ISI_R2Y_SET0,ISI Color Space Conversion RGB to YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " Roff ,Color Space Conversion Red component offset" "No offset,Offset=16"
|
|
hexmask.long.byte 0x18 16.--23. 1. " C2 ,Color Space Conversion Matrix coefficient C2"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " C1 ,Color Space Conversion Matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " C0 ,Color Space Conversion Matrix coefficient C0"
|
|
line.long 0x1c "ISI_R2Y_SET1,ISI Color Space Conversion RGB to YCrCb Set 1 Register"
|
|
bitfld.long 0x1c 24. " Goff ,Color Space Conversion Green component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x1c 16.--23. 1. " C5 ,Color Space Conversion Matrix coefficient C5"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 8.--15. 1. " C4 ,Color Space Conversion Matrix coefficient C4"
|
|
hexmask.long.byte 0x1c 0.--7. 1. " C3 ,Color Space Conversion Matrix coefficient C3"
|
|
line.long 0x20 "ISI_R2Y_SET2,ISI Color Space Conversion RGB to YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " Boff ,Color Space Conversion Blue component offset" "No offset,Offset=128"
|
|
hexmask.long.byte 0x20 16.--23. 1. " C8 ,Color Space Conversion Matrix coefficient C8"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " C7 ,Color Space Conversion Matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--7. 1. " C6 ,Color Space Conversion Matrix coefficient C6"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "ISI_CTRL,ISI Control Register"
|
|
bitfld.long 0x00 8. " ISI_CDC ,ISI Codec Request" "No effect,Enable"
|
|
bitfld.long 0x00 2. " ISI_SRST ,ISI Software Reset Request" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISI_DIS ,ISI Module Disable Request" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ISI_EN ,ISI Module Enable Request" "No effect,Enable"
|
|
hgroup.long 0x28++0x3
|
|
sif (cpu()=="AT91SAMG25"||cpu()=="AT91SAMG46")
|
|
hide.long 0x00 "ISI_SR,ISI Status Register"
|
|
in
|
|
else
|
|
hide.long 0x00 "ISI_STATUS,ISI Status Register"
|
|
in
|
|
endif
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "ISI_IMR,ISI Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " FR_OVR_set/clr ,Frame Rate Overrun Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " CRC_ERR_set/clr ,CRC Synchronization Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " C_OVR_set/clr ,FIFO Codec Overflow Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " P_OVR_set/clr ,FIFO Preview Overflow Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " CXFR_DONE_set/clr ,Codec DMA Transfer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " PXFR_DONE_set/clr ,Preview DMA Transfer Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " VSYNC_set/clr ,Vertical Synchronization Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " SRST_set/clr ,Software Reset Completed Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIS_DONE_set/clr ,Module Disable Request Termination Interrupt" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DMA_CHSR,DMA Channel Status Register"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " C_CH_S_set/clr ,Preview DMA channel" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " P_CH_S_set/clr ,Codec DMA channel" "Disabled,Enabled"
|
|
group.long 0x44++0x17
|
|
line.long 0x00 "DMA_P_ADDR,DMA Preview Base Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " P_ADDR ,Preview Image Base Address"
|
|
line.long 0x04 "DMA_P_CTRL ,DMA Preview Control Register"
|
|
bitfld.long 0x04 3. " P_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " P_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " P_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x08 "DMA_P_DSCR,DMA Preview Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x4 " P_DSCR ,Preview Descriptor Base Address"
|
|
line.long 0x0c "DMA_C_ADDR,DMA Codec Base Address Register"
|
|
sif (cpu()=="AT91SAMG46"||cpu()=="AT91SAMG25")
|
|
hexmask.long 0x0c 2.--31. 0x4 " C_ADDR ,Codec Image Base Address"
|
|
else
|
|
hexmask.long 0x0c 2.--31. 0x4 " C_ADDR ,Preview Image Base Address"
|
|
endif
|
|
line.long 0x10 "DMA_C_CTRL ,DMA Codec Control Register"
|
|
bitfld.long 0x10 3. " C_DONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x10 2. " C_IEN ,Transfer Done Flag Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " C_WB ,Descriptor Writeback Control Field" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " C_FETCH ,Descriptor Fetch Control Field" "Disabled,Enabled"
|
|
line.long 0x14 "DMA_C_DSCR,DMA Codec Descriptor Address Register"
|
|
hexmask.long 0x14 2.--31. 0x4 " C_DSCR ,Codec Descriptor Base Address"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "ISI_WPCR,ISI Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "ISI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G20")
|
|
tree "ADC (Analog-to-digital Converter)"
|
|
base ad:0xfffe0000
|
|
width 0xa
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Started"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
sif (cpuis("AT91CAP9*")||cpuis("AT91SAM9XE*"))
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "0,1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock"
|
|
else
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock,16/clock"
|
|
endif
|
|
bitfld.long 0x00 16.--20. " STARTUP ,Start Up Time" "8/clock,16/clock,24/clock,32/clock,40/clock,48/clock,56/clock,64/clock,72/clock,80/clock,88/clock,96/clock,104/clock,112/clock,120/clock,128/clock,136/clock,144/clock,152/clock,160/clock,168/clock,176/clock,184/clock,192/clock,200/clock,208/clock,216/clock,224/clock,232/clock,240/clock,248/clock,256/clock"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PRESCAL ,Prescaler Rate Selection" "MCK/2,MCK/4,MCK/6,MCK/8,MCK/10,MCK/12,MCK/14,MCK/16,MCK/18,MCK/20,MCK/22,MCK/24,MCK/26,MCK/28,MCK/30,MCK/32,MCK/34,MCK/36,MCK/38,MCK/40,MCK/42,MCK/44,MCK/46,MCK/48,MCK/50,MCK/52,MCK/54,MCK/56,MCK/58,MCK/60,MCK/62,MCK/64,MCK/66,MCK/68,MCK/70,MCK/72,MCK/74,MCK/76,MCK/78,MCK/80,MCK/82,MCK/84,MCK/86,MCK/88,MCK/90,MCK/92,MCK/94,MCK/96,MCK/98,MCK/100,MCK/102,MCK/104,MCK/106,MCK/108,MCK/110,MCK/112,MCK/114,MCK/116,MCK/118,MCK/120,MCK/122,MCK/124,MCK/126,MCK/128"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
sif (cpuis("AT91CAP9*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "TIOA/Timer 0,TIOA/Timer 1,TIOA/Timer 2,TIOB/Timer 0,TIOB/Timer 1,TIOB/Timer 2,External,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "Channel 0,Channel 1,Channel 2,Reserved,Reserved,Reserved,External,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x0 "ADC_CHSR,ADC Channel Status Register"
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "ADC_SR,ADC Status Register"
|
|
in
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "ADC_LCDR,ADC Last Converted Data Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " OVRE7 ,Overrun Error Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " OVRE6 ,Overrun Error Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " OVRE5 ,Overrun Error Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " OVRE4 ,Overrun Error Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " OVRE3 ,Overrun Error Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " OVRE2 ,Overrun Error Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " OVRE1 ,Overrun Error Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " OVRE0 ,Overrun Error Interrupt Mask 0" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91CAP9*"))
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "ADC_CDR0,ADC Channel Data Register 0"
|
|
in
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x00 "ADC_CDR1,ADC Channel Data Register 1"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "ADC_CDR2,ADC Channel Data Register 2"
|
|
in
|
|
hgroup.long 0x3c++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 3"
|
|
in
|
|
sif (cpuis("AT91CAP9*"))
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "ADC_CDR4,ADC Channel Data Register 4"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "ADC_CDR5,ADC Channel Data Register 5"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 6"
|
|
in
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x00 "ADC_CDR3,ADC Channel Data Register 7"
|
|
in
|
|
endif
|
|
base vm:0x0
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
tree "TSADCC (Touch Screen ADC Controller)"
|
|
base ad:0xfffb0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TSADCC_CR,TSADCC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TSADCC_MR,TSADCC Mode Register"
|
|
bitfld.long 0x00 28.--31. " PENDBC ,Pen Detect debouncing period" "1/clock,2/clock,4/clock,8/clock,16/clock,32/clock,64/clock,128/clock,256/clock,512/clock,1024/clock,2048/clock,4096/clock,8192/clock,16384/clock,32768/clock"
|
|
bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock,16/clock"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " STARTUP ,Start Up Time"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRES ,Pressure Measurement Selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PENDET , Pen Detect Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDCEN ,PDC transfer in Touchscreen/Interleaved mode or Manual mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TSAMOD , Touch Screen ADC Mode" "ADC,Touch Screen,Interleaved,Manual"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TSADCC_TRGR,TSADCC Trigger Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRGPER , Trigger Period"
|
|
bitfld.long 0x00 0.--2. " TRGMOD , Trigger Mode " "No trigger,Rising Edge,Falling Edge,Any Edge,Pen Detect,Periodic,Continuous,?..."
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TSADCC_TSR,TSADCC Touch Screen Register"
|
|
bitfld.long 0x00 24.--27. " TSSHTIM , Sample & Hold Time for Touch Screen Channels" "1/clock,1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock"
|
|
bitfld.long 0x00 0.--3. " TSFREQ ,Touch Screen Frequency in Interleaved Mode" "Trigger freq/6,Trigger freq/6,Trigger freq/8,Trigger freq/16,Trigger freq/32,Trigger freq/64,Trigger freq/128,Trigger freq/256,Trigger freq/512,Trigger freq/1024,Trigger freq/2048,Trigger freq/4096,Trigger freq/8192,Trigger freq/16394,Trigger freq/32768,Trigger freq/65536"
|
|
group.long 0x18++0x03
|
|
line.long 0x0 "TSADCC_CHSR,TSADCC Channel Status Register"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "TSADCC_SR, TSADCC Status Register"
|
|
in
|
|
rgroup.long 0x30++0x1f
|
|
line.long 0x0 "TSADCC_CDR0,TSADCC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x4 "TSADCC_CDR1,TSADCC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x8 "TSADCC_CDR2,TSADCC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0xC "TSADCC_CDR3,TSADCC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x10 "TSADCC_CDR4,TSADCC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x14 "TSADCC_CDR5,TSADCC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x18 "TSADCC_CDR6,TSADCC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Channel Data"
|
|
line.long 0x1C "TSADCC_CDR7,TSADCC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Channel Data"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "TSADCC_LCDR,TSADCC Last Converted Data Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TSADCC_IMR,TSADCC Interrupt Mask Register"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " OVREZ2_set/clr , Overrun Error Interrupt Enable Z2 Measure" "Disabled,Enabled"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " OVREZ1_set/clr , Overrun Error Interrupt Enable Z1 Measure" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " OVREXP_set/clr , Overrun Error Interrupt Enable X Position" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " EOCZ2_set/clr , End of Conversion Z2 Measure" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " EOCZ1_set/clr , End of Conversion Z1 Measure" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " EOCXP_set/clr , End of Conversion X Position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " NOCNT_set/clr , No Contact" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " PENCNT_set/clr , Pen Contact" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " ENDRX_set/clr ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " GOVRE_set/clr ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " DRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " OVRE7_set/clr ,Overrun Error Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " OVRE6_set/clr ,Overrun Error Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " OVRE5_set/clr ,Overrun Error Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " OVRE4_set/clr ,Overrun Error Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " OVRE3_set/clr ,Overrun Error Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " OVRE2_set/clr ,Overrun Error Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " OVRE1_set/clr ,Overrun Error Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " OVRE0_set/clr ,Overrun Error Interrupt Mask 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7_set/clr ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6_set/clr ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5_set/clr ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4_set/clr ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3_set/clr ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2_set/clr ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1_set/clr ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0_set/clr ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
rgroup.long 0x50++0xb
|
|
line.long 0x00 "TSADCC_XPDR,TSADCC X Position Data Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA ,X Position Data"
|
|
line.long 0x04 "TSADCC_Z1DR,TSADCC Z1 Data Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " DATA ,Z1 Measurement Data"
|
|
line.long 0x08 "TSADCC_Z2DR,TSADCC Z2 Data Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " Z2 , Z2 Measurement Data"
|
|
else
|
|
group.long 0x50++0xb
|
|
line.long 0x00 "TSADCC_XPDR,TSADCC X Position Data Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA ,X Position Data"
|
|
line.long 0x04 "TSADCC_Z1DR,TSADCC Z1 Data Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " DATA ,Z1 Measurement Data"
|
|
line.long 0x08 "TSADCC_Z2DR,TSADCC Z2 Data Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " DATA , Z2 Measurement Data"
|
|
endif
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TSADCC_MSCR,TSADCC Manual Switch Command Register"
|
|
bitfld.long 0x00 3. " Y_M ,Switch Command" "Open,Closed"
|
|
bitfld.long 0x00 2. " Y_P ,Switch Command" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " X_M ,Switch Command" "Open,Closed"
|
|
bitfld.long 0x00 0. " X_P ,Switch Command" "Open,Closed"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TSADCC_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " KEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
Hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "TSADCC_WPSR,TSADCC Write Protection Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0xffffec00
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 8. " DICEN ,Descriptor Integrity Check" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
bitfld.long 0x08 15. " DSREQ7 ,Request a destination single transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " SSREQ7 ,Request a source single transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSREQ6 ,Request a destination single transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " SSREQ6 ,Request a source single transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
bitfld.long 0x0C 15. " DCREQ7 ,Request a destination chunk transfer on channel 7" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " SCREQ7 ,Request a source chunk transfer on channel 7" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DCREQ6 ,Request a destination chunk transfer on channel 6" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " SCREQ6 ,Request a source chunk transfer on channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
bitfld.long 0x10 15. " DLAST7 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 14. " SLAST7 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DLAST6 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 12. " SLAST6 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " DICERR7_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DICERR6_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " DICERR5_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " DICERR4_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " DICERR3_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " DICERR2_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " DICERR1_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DICERR0_set/clr ,Descriptor Integrity Check Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " ERR7_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " ERR6_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CBTC7_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CBTC6_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " BTC7_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " BTC6_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x00 31. " DICERR7 ,Channel 7 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 30. " DICERR6 ,Channel 6 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DICERR5 ,Channel 5 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 28. " DICERR4 ,Channel 4 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DICERR3 ,Channel 3 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 26. " DICERR2 ,Channel 2 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DICERR1 ,Channel 1 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
bitfld.long 0x00 24. " DICERR0 ,Channel 0 has detected a Descriptor Integrity Check Error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 23. " ERR7 ,Channel 7 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 ,Channel 6 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 ,Channel 5 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 ,Channel 4 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 ,Channel 3 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 ,Channel 2 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 ,Channel 1 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 ,Channel 0 has detected an AHB Read or Write Error Access" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " ERR7 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 22. " ERR6 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CBTC7 ,Channel 7 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 14. " CBTC6 ,Channel 6 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 ,Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BTC7 ,Channel 7 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 6. " BTC6 ,Channel 6 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTC5 ,Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 ,Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
bitfld.long 0x00 31. " KEEP7 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 30. " KEEP6 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "No resume,Resume"
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
bitfld.long 0x00 31. " STAL7 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 30. " STAL6 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMPT7 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 22. " EMPT6 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " SUSP7_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " SUSP6_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENA7_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA6_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x1f
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR0 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR0_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP0,DMAC Channel 0 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP0,DMAC Channel 0 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x1f
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR1 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR1_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP1,DMAC Channel 1 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP1,DMAC Channel 1 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x1f
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR2 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR2_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP2,DMAC Channel 2 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP2,DMAC Channel 2 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x1f
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR3 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR3_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP3,DMAC Channel 3 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP3,DMAC Channel 3 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x1f
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR4 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR4_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP4,DMAC Channel 4 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP4,DMAC Channel 4 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x1f
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR5 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR5_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP5,DMAC Channel 5 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP5,DMAC Channel 5 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x12C++0x1f
|
|
line.long 0x00 "DMAC_SADDR6,DMAC Channel 6 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR6, DMAC Channel 6 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR6,DMAC Channel 6 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR6 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR6_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA6,DMAC Channel 6 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB6,DMAC Channel 6 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[6] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG6,DMAC Channel 6 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 6 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 6 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 6 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP6,DMAC Channel 6 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP6,DMAC Channel 6 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x154++0x1f
|
|
line.long 0x00 "DMAC_SADDR7,DMAC Channel 7 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR7, DMAC Channel 7 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR7,DMAC Channel 7 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 4. " DSCR7 , Buffer Transfer descriptor address"
|
|
bitfld.long 0x08 0.--1. " DSCR7_IF ,Buffer Transfer descriptor fetched" "AHB-Lite Interface 0,AHB-Lite Interface 1,?..."
|
|
line.long 0x0c "DMAC_CTRLA7,DMAC Channel 7 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "Performed,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB7,DMAC Channel 7 Control B Register"
|
|
bitfld.long 0x10 31. " AUTO , Automatic multiple buffer transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " IEN , BTC[7] flag enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
else
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,Per2Mem | Per,Mem2Per | Per,Per2Per | SrcPer,Per2Per | DstPer"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 12. " DST_PIP , Picture-in-Picture destination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " SRC_PIP , Picture-in-Picture source " "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " DIF , Destination Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SIF , Source Interface Selection Field" "Interface 0,Interface 1,?..."
|
|
line.long 0x14 "DMAC_CFG7,DMAC Channel 7 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 7 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Activated"
|
|
else
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 14.--15. " DST_PER_MSB ,DST_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 12. " DST_REP ,Destination mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
sif (cpu()=="AT91SAM9N12")
|
|
bitfld.long 0x14 10.--11. " SRC_PER_MSB ,SRC_PER Most Significant Bits" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
bitfld.long 0x14 8. " SRC_REP ,Source mode" "Contiguous,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 7 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 7 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DMAC_SPIP7,DMAC Channel 7 Source Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x18 16.--25. 1. " SPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x18 0.--15. 1. " SPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
line.long 0x1c "DMAC_DPIP7,DMAC Channel 7 Destination Picture in Picture Configuration Register"
|
|
hexmask.long.word 0x1c 16.--25. 1. " DPIP_BOUNDARY , Number of source transfers to perform"
|
|
hexmask.long.word 0x1c 0.--15. 1. " DPIP_HOLE ,Value to add to the address when the programmable boundary has been reached"
|
|
tree.end
|
|
textline ""
|
|
sif (cpu()=="AT91SAM9G35"||cpu()=="AT91SAM9G25"||cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9N12")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "DMAC_WPMR,DMAC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection KEY Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x04 "DMAC_WPSR,DMAC Write Protect Status Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0xfffb8000
|
|
width 0x9
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PWM_MR,PWM Mode Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0xc++3
|
|
line.long 0x0 "PWM_SR,PWM Status Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM Output for Channel 3 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM Output for Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM Output for Channel 1 Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM Output for Channel 0 Enable" "Disabled,Enabled"
|
|
group.long 0x18++3
|
|
line.long 0x0 "PWM_IMR,PWM Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Enable Interrupt for PWM Channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Enable Interrupt for PWM Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Enable Interrupt for PWM Channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CHID0_set/clr ,Enable Interrupt for PWM Channel 0" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PWM_ISR,PWM Interrupt Status Register"
|
|
in
|
|
wgroup 0x0++0x0
|
|
width 0xb
|
|
tree "Channel 0 Registers"
|
|
group.long (0x200+(0*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR0,PWM Channel 0 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
rgroup.long (0x20C+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
wgroup.long (0x210+(0*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD0,PWM Channel 0 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 1 Registers"
|
|
group.long (0x200+(1*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR1,PWM Channel 1 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
rgroup.long (0x20C+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
wgroup.long (0x210+(1*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD1,PWM Channel 1 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 2 Registers"
|
|
group.long (0x200+(2*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR2,PWM Channel 2 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
rgroup.long (0x20C+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
wgroup.long (0x210+(2*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD2,PWM Channel 2 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree "Channel 3 Registers"
|
|
group.long (0x200+(3*0x20))++0x0b
|
|
line.long 0x00 "PWM_CMR3,PWM Channel 3 Mode Register"
|
|
bitfld.long 0x00 10. " CPD ,Channel Update Period" "Duty cycle,Period"
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low,High"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-Scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
line.long 0x04 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
line.long 0x08 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
rgroup.long (0x20C+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
wgroup.long (0x210+(3*0x20))++0x03
|
|
line.long 0x00 "PWM_CUPD3,PWM Channel 3 Update Register"
|
|
tree.end
|
|
width 0xb
|
|
width 0xb
|
|
tree.end
|
|
tree "AC97 (Audio Codec 97)"
|
|
base ad:0xfffac000
|
|
width 13.
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "AC97C_MR,Mode Register"
|
|
bitfld.long 0x00 2. " VRA ,Variable Rate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " WRST ,Warm Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA ,AC97 Controller Global Enable" "No effect,Enabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "AC97C_ICA,Input Channel Assignment Register"
|
|
bitfld.long 0x00 27.--29. " CHID12 ,Channel ID for the input slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 24.--26. " CHID11 ,Channel ID for the input slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CHID10 ,Channel ID for the input slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 18.--20. " CHID9 ,Channel ID for the input slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CHID8 ,Channel ID for the input slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 12.--14. " CHID7 ,Channel ID for the input slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CHID6 ,Channel ID for the input slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 6.--8. " CHID5 ,Channel ID for the input slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CHID4 ,Channel ID for the input slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x00 0.--2. " CHID3 ,Channel ID for the input slot 3" "None,Channel A,Channel B,?..."
|
|
line.long 0x04 "AC97C_OCA,Output Channel Assignment Register"
|
|
bitfld.long 0x04 27.--29. " CHID12 ,Channel ID for the output slot 12" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 24.--26. " CHID11 ,Channel ID for the output slot 11" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " CHID10 ,Channel ID for the output slot 10" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 18.--20. " CHID9 ,Channel ID for the output slot 9" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " CHID8 ,Channel ID for the output slot 8" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 12.--14. " CHID7 ,Channel ID for the output slot 7" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " CHID6 ,Channel ID for the output slot 6" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 6.--8. " CHID5 ,Channel ID for the output slot 5" "None,Channel A,Channel B,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " CHID4 ,Channel ID for the output slot 4" "None,Channel A,Channel B,?..."
|
|
bitfld.long 0x04 0.--2. " CHID3 ,Channel ID for the output slot 3" "None,Channel A,Channel B,?..."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "AC97C_CORHR,Codec Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDATA ,Status Data"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x00 "AC97C_COTHR,Codec Transmit Holding Register"
|
|
bitfld.long 0x00 23. " READ ,Read/Write command" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CADDR ,CODEC control register index"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CDATA ,Command Data"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "AC97C_CARHR,Channel A Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "AC97C_CBRHR,Channel B Receive Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDATA ,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "AC97C_CATHR,Channel A Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "AC97C_CBTHR,Channel B Transmit Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TDATA ,Data to Transmit"
|
|
hgroup.long 0x28++3
|
|
hide.long 0x00 "AC97C_CASR,Channel A Status Register"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "AC97C_CBSR,Channel B Status Register"
|
|
in
|
|
hgroup.long 0x48++3
|
|
hide.long 0x00 "AC97C_COSR,Codec Status Register"
|
|
in
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "AC97C_CAMR,Channel A Mode Register"
|
|
bitfld.long 0x00 22. " PDCEN ,Peripheral Data Controller Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CEN ,Channel A Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CEM ,Channel A Endian Mode" "Little,Big"
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel A Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for channel A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for channel A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for channel A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for channel A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "AC97C_CBMR,Channel B Mode Register"
|
|
bitfld.long 0x00 22. " PDCEN ,Peripheral Data Controller Channel Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CEN ,Channel B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CEM ,Channel B Endian Mode" "Little,Big"
|
|
bitfld.long 0x00 16.--17. " SIZE ,Channel B Data Size" "20 bits,18 bits,16 bits,10 bits"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXBUFF ,Receive Buffer Full for channel B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENDRX ,End of Reception for channel B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,Transmit Buffer Empty for channel B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENDTX ,End of Transmission for channel B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "AC97C_COMR,Codec Mode Register"
|
|
bitfld.long 0x00 5. " OVRUN ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRDY ,Channel Receive Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UNRUN ,Transmit Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXEMPTY ,Channel Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TXRDY ,Channel Transmit Ready Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "AC97C_SR,Status Register"
|
|
in
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "AC97C_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CBEVT_set/clr ,Channel B Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CAEVT_set/clr ,Channel A Event" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " COEVT_set/clr ,CODEC Channel Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " WKUP_set/clr ,Wake Up detection" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " SOF_set/clr ,Start Of Frame" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="AT91SAM9G46")
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0xFFFC0000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES Control Register"
|
|
bitfld.long 0x00 16. " LOADSEED ,Random Number Generator Seed Loading" "No effect,Reset"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AES_MR,AES Mode Register"
|
|
bitfld.long 0x00 28. " CMTYP5 ,CounterMeasure Type 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CMTYP4 ,CounterMeasure Type 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CMTYP3 ,CounterMeasure Type 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CMTYP2 ,CounterMeasure Type 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CMTYP1 ,CounterMeasure Type 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " CKEY ,Countermeasure Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher Feedback Data Size" "128-bit,64-bit,32-bit,16-bit,8-bit,?..."
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB,CTR,?..."
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key Size" "AES128,AES192,AES256,?..."
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "MANUAL_START,AUTO_START,IDATAR0_START,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypts data,Encrypts data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AES_IMR,AES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt Mask" "Not enabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "AES_ISR,AES Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x0 "AES_KEYWR0,AES Key Word Register 0"
|
|
line.long 0x4 "AES_KEYWR1,AES Key Word Register 1"
|
|
line.long 0x8 "AES_KEYWR2,AES Key Word Register 2"
|
|
line.long 0xC "AES_KEYWR3,AES Key Word Register 3"
|
|
line.long 0x10 "AES_KEYWR4,AES Key Word Register 4"
|
|
line.long 0x14 "AES_KEYWR5,AES Key Word Register 5"
|
|
line.long 0x18 "AES_KEYWR6,AES Key Word Register 6"
|
|
line.long 0x1C "AES_KEYWR7,AES Key Word Register 7"
|
|
wgroup.long 0x40++0xF
|
|
line.long 0x0 "AES_IDATAR0,AES Input Data Register 0"
|
|
line.long 0x4 "AES_IDATAR1,AES Input Data Register 1"
|
|
line.long 0x8 "AES_IDATAR2,AES Input Data Register 2"
|
|
line.long 0xC "AES_IDATAR3,AES Input Data Register 3"
|
|
rgroup.long 0x50++0x0F
|
|
line.long 0x0 "AES_ODATAR0,AES Output Data Register 0"
|
|
line.long 0x4 "AES_ODATAR1,AES Output Data Register 1"
|
|
line.long 0x8 "AES_ODATAR2,AES Output Data Register 2"
|
|
line.long 0xC "AES_ODATAR3,AES Output Data Register 3"
|
|
if ((d.l(ad:(ad:0xFFFC0000+0x04))&0x7000)==0x0)
|
|
hgroup.long 0x60++0x0F
|
|
hide.long 0x0 "AES_IVR0,AES Initialization Vector Register 0"
|
|
hide.long 0x4 "AES_IVR1,AES Initialization Vector Register 1"
|
|
hide.long 0x8 "AES_IVR2,AES Initialization Vector Register 2"
|
|
hide.long 0xC "AES_IVR3,AES Initialization Vector Register 3"
|
|
else
|
|
wgroup.long 0x60++0x0F
|
|
line.long 0x0 "AES_IVR0,AES Initialization Vector Register 0"
|
|
line.long 0x4 "AES_IVR1,AES Initialization Vector Register 1"
|
|
line.long 0x8 "AES_IVR2,AES Initialization Vector Register 2"
|
|
line.long 0xC "AES_IVR3,AES Initialization Vector Register 3"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TDES (Triple Data Encryption Standard)"
|
|
base ad:0xFFFC4000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TDES_CR,AES Control Register"
|
|
bitfld.long 0x00 16. " LOADSEED ,Random Number Generator Seed Loading" "No effect,Reset"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TDES_MR,TDES Mode Register"
|
|
bitfld.long 0x00 28. " CTYPE5 ,Countermeasure type 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CTYPE4 ,Countermeasure type 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CTYPE3 ,Countermeasure type 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CTYPE2 ,Countermeasure type 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CTYPE1 ,Countermeasure type 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " CKEY ,Countermeasure Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CFBS ,Cipher Feedback Data Size" "64-bit,32-bit,16-bit,8-bit"
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB"
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "Manual Mode,Auto Mode,PDC Mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " KEYMOD ,Key Mode" "Three-key,Two-key"
|
|
bitfld.long 0x00 1.--2. " TDESMOD ,ALGORITHM mode" "Single DES,Triple DES,XTEA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypts data,Encrypts data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TDES_IMR,TDES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "TDES_ISR,TDES Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x20++0x17
|
|
line.long 0x0 "TDES_KEY1W1R,Key 1 Word 1 Register"
|
|
line.long 0x0+0x04 "TDES_KEY1W2R,Key 1 Word 2 Register"
|
|
line.long 0x8 "TDES_KEY2W1R,Key 2 Word 1 Register"
|
|
line.long 0x8+0x04 "TDES_KEY2W2R,Key 2 Word 2 Register"
|
|
line.long 0x10 "TDES_KEY3W1R,Key 3 Word 1 Register"
|
|
line.long 0x10+0x04 "TDES_KEY3W2R,Key 3 Word 2 Register"
|
|
wgroup.long 0x40++0x07
|
|
line.long 0x00 "TDES_IDATA1R,TDES Input Data 1 Register"
|
|
line.long 0x04 "TDES_IDATA2R,TDES Input Data 2 Register"
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "TDES_ODATA1R,TDES Output Data 1 Register"
|
|
line.long 0x04 "TDES_ODATA2R,TDES Output Data 2 Register"
|
|
if ((d.l(ad:(ad:0xFFFC4000+0x04))&0x7000)==0x0)
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "TDES_IV1R,TDES Initialization Vector 1 Register"
|
|
hide.long 0x04 "TDES_IV2R,TDES Initialization Vector 2 Register"
|
|
else
|
|
wgroup.long 0x60++0x07
|
|
line.long 0x00 "TDES_IV1R,TDES Initialization Vector 1 Register"
|
|
line.long 0x04 "TDES_IV2R,TDES Initialization Vector 2 Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TDES_XTEA_RNDR,TDES XTEA Rounds Register"
|
|
bitfld.long 0x00 0.--5. " XTEA_RNDS ,Number of Rounds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree "PDC_TDES"
|
|
base ad:0xFFFC4000
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "TDES_RPR,Triple Data Encryption Standard Receive Pointer Register"
|
|
line.long 0x04 "TDES_RCR,Triple Data Encryption Standard Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TDES_TPR,Triple Data Encryption Standard Transmit Pointer Register"
|
|
line.long 0x0c "TDES_TCR,Triple Data Encryption Standard Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TDES_RNPR,Triple Data Encryption Standard Receive Next Pointer Register"
|
|
line.long 0x14 "TDES_RNCR,Triple Data Encryption Standard Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "TDES_TNPR,Triple Data Encryption Standard Transmit Next Pointer Register"
|
|
line.long 0x1c "TDES_TNCR,Triple Data Encryption Standard Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TDES_PTCR,Triple Data Encryption Standard PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TDES_PTSR,Triple Data Encryption Standard PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0xFFFC8000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SHA_CR,SHA Control Register"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 4. " FIRST ,First Block of a Message" "No effect,Indicate"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SHA_MR,SHA Mode Register"
|
|
bitfld.long 0x00 8. " ALGO ,SHA Algorithm" "SHA1,SHA256"
|
|
bitfld.long 0x00 4. " PROCDLY ,Processing Delay" "85 or 72 clock cycles,326 or 265 clock cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SMOD ,Start Mode" "Manual,Auto,PDC,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TDES_IMR,TDES Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD_set/clr ,Unspecified Register Access Detection Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SHA_ISR,SHA Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x40++0x3F
|
|
line.long 0x0 "SHA_IDATA1R,SHA Input Data 1 Register"
|
|
line.long 0x4 "SHA_IDATA2R,SHA Input Data 2 Register"
|
|
line.long 0x8 "SHA_IDATA3R,SHA Input Data 3 Register"
|
|
line.long 0xC "SHA_IDATA4R,SHA Input Data 4 Register"
|
|
line.long 0x10 "SHA_IDATA5R,SHA Input Data 5 Register"
|
|
line.long 0x14 "SHA_IDATA6R,SHA Input Data 6 Register"
|
|
line.long 0x18 "SHA_IDATA7R,SHA Input Data 7 Register"
|
|
line.long 0x1C "SHA_IDATA8R,SHA Input Data 8 Register"
|
|
line.long 0x20 "SHA_IDATA9R,SHA Input Data 9 Register"
|
|
line.long 0x24 "SHA_IDATA10R,SHA Input Data 10 Register"
|
|
line.long 0x28 "SHA_IDATA11R,SHA Input Data 11 Register"
|
|
line.long 0x2C "SHA_IDATA12R,SHA Input Data 12 Register"
|
|
line.long 0x30 "SHA_IDATA13R,SHA Input Data 13 Register"
|
|
line.long 0x34 "SHA_IDATA14R,SHA Input Data 14 Register"
|
|
line.long 0x38 "SHA_IDATA15R,SHA Input Data 15 Register"
|
|
line.long 0x3C "SHA_IDATA16R,SHA Input Data 16 Register"
|
|
rgroup.long 0x80++0x1F
|
|
line.long 0x0 "SHA_ODATA1R,SHA Output Data 1 Register"
|
|
line.long 0x4 "SHA_ODATA2R,SHA Output Data 2 Register"
|
|
line.long 0x8 "SHA_ODATA3R,SHA Output Data 3 Register"
|
|
line.long 0xC "SHA_ODATA4R,SHA Output Data 4 Register"
|
|
line.long 0x10 "SHA_ODATA5R,SHA Output Data 5 Register"
|
|
line.long 0x14 "SHA_ODATA6R,SHA Output Data 6 Register"
|
|
line.long 0x18 "SHA_ODATA7R,SHA Output Data 7 Register"
|
|
line.long 0x1C "SHA_ODATA8R,SHA Output Data 8 Register"
|
|
width 0xB
|
|
tree "PDC_SHA"
|
|
base ad:0xFFFC8000
|
|
width 13.
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "SHA_RPR,Secure Hash Algorithm Receive Pointer Register"
|
|
line.long 0x04 "SHA_RCR,Secure Hash Algorithm Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SHA_TPR,Secure Hash Algorithm Transmit Pointer Register"
|
|
line.long 0x0c "SHA_TCR,Secure Hash Algorithm Transmit Counter Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SHA_RNPR,Secure Hash Algorithm Receive Next Pointer Register"
|
|
line.long 0x14 "SHA_RNCR,Secure Hash Algorithm Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCTR ,Receive Next Counter Value"
|
|
line.long 0x18 "SHA_TNPR,Secure Hash Algorithm Transmit Next Pointer Register"
|
|
line.long 0x1c "SHA_TNCR,Secure Hash Algorithm Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCTR ,Transmit Counter Next Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SHA_PTCR,Secure Hash Algorithm PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SHA_PTSR,Secure Hash Algorithm PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()!="AT91SAM9G46")
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xfffcc000
|
|
width 0x10
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "TRNG_CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 100. " KEY ,Key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disables,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TRNG_IMR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "TRNG_ISR,TRNG Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "TRNG_ODATA ,TRNG Output Data Register"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "LCDC (LCD Controller)"
|
|
sif (cpu()=="AT91SAM9G10")
|
|
base ad:0x00600000
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
sif (cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
hexmask.long 0x00 2.--31. 0x4 " BADDR-U ,Base Address for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
else
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
endif
|
|
line.long 0x04 "DMABADDR2,DMA Base Address Register 2"
|
|
rgroup.long 0x08++0xf
|
|
line.long 0x00 "DMAFRMPT1,DMA Frame Pointer Register 1"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMPT-U ,Current value of frame pointer for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMAFRMPT2,DMA Frame Pointer Register 2"
|
|
hexmask.long.tbyte 0x04 0.--22. 1. " FRMPT-L ,Current value of frame pointer for the Lower panel in dual scan mode"
|
|
line.long 0x8 "DMAFRMADD1,DMA Frame Address Register 1"
|
|
line.long 0xC "DMAFRMADD2,DMA Frame Address Register 2"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DMAFRMCFG,DMA Frame Configuration Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BRSTLN ,Burst Length"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMSIZE ,Frame Size"
|
|
line.long 0x4 "DMACON,DMA Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x4 4. " DMA2DEN ,DMA 2D Adressing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " DMAUPDT ,DMA Configuration Update" "No effect,Updated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 2. " DMABUSY ,DMA Busy" "Idle,Busy"
|
|
bitfld.long 0x4 1. " DMARST ,DMA Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x20++0x03
|
|
line.long 0x0 "DMA2DCFG,DMA 2D Adressing Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " PIXELOFF ,DAM2D Addressing Pixel Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRINC ,DMA 2D Addressing Address increment"
|
|
endif
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LCDCON1,LCD Control Register 1"
|
|
hexmask.long.word 0x00 21.--31. 1. " LINECNT ,Line Counter"
|
|
hexmask.long.word 0x00 12.--20. 1. " CLKVAL ,Clock Divider"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass lcd_pclk Divider" "Not bypassed,Bypassed"
|
|
if ((d.l(ad:0x00600000+0x804)&0x3)==0x2)
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,24 bpp/unpacked,?..."
|
|
else
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00600000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00600000+0x804)&0x4)==(0x4)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "Reserved,8-bit,16-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00600000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00600000+0x804)&0x4)==(0x0)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "4-bit,8-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
else
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
endif
|
|
group.long 0x808++0xf
|
|
line.long 0x0 "LCDTIM1,LCD Timing Configuration Register 1"
|
|
bitfld.long 0x0 24.--27. " VHDLY ,Vertical to horizontal delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0 16.--21. 1. 1. " VPW ,Vertical Synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VFP ,Vertical Front Porch"
|
|
line.long 0x4 "LCDTIM2,LCD Timing Configuration Register 2"
|
|
hexmask.long.word 0x4 21.--31. 1. 1. " HFP ,Horizontal Front Porch"
|
|
hexmask.long.byte 0x4 8.--13. 1. 1. " HPW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. 1. " HBP ,Horizontal Back Porch"
|
|
line.long 0x8 "LCDFRMCFG,LCD Frame Configuration Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
hexmask.long.word 0x8 21.--31. 1. " LINESIZE ,Horizontal size of LCD module"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x8 21.--31. 1. " HOZVAL ,Horizontal size of LCD module"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x8 0.--10. 1. " LINEVAL ,Vertical size of LCD module"
|
|
line.long 0xC "LCDFIFO,LCD FIFO Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " FIFOTH ,FIFO Threshold"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x818++0x3
|
|
line.long 0x0 "LCDMVAL,LCD_MODE Toggle Rate Value Register"
|
|
bitfld.long 0x0 31. " MMODE ,LCD_MODE toggle rate select" "Each frame,MVAL"
|
|
hexmask.long.byte 0x0 0.--7. 1. 1. " MVAL ,LCD_MODE toggle rate value"
|
|
endif
|
|
group.long 0x81c--0x847
|
|
line.long 0x00 "DP1_2,Dithering Pattern DP1_2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DP1_2 ,Pattern value for 1/2 duty cycle"
|
|
line.long 0x04 "DP4_7,Dithering Pattern DP4_7 Register"
|
|
hexmask.long 0x04 0.--27. 1. " DP4_7 ,Pattern value for 4/7 duty cycle"
|
|
line.long 0x8 "DP3_5,Dithering Pattern DP3_5 Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. " DP3_5 ,Pattern value for 3/5 duty cycle"
|
|
line.long 0xc "DP2_3,Dithering Pattern DP2_3 Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " DP2_3 ,Pattern value for 2/3 duty cycle"
|
|
line.long 0x10 "DP5_7,Dithering Pattern DP5_7 Register"
|
|
hexmask.long 0x10 0.--27. 1. " DP5_7 ,Pattern value for 5/7 duty cycle"
|
|
line.long 0x14 "DP3_4,Dithering Pattern DP3_4 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DP3_4 ,Pattern value for 3/4 duty cycle"
|
|
line.long 0x18 "DP4_5,Dithering Pattern DP4_5 Register"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " DP4_5 ,Pattern value for 4/5 duty cycle"
|
|
line.long 0x1c "DP6_7,Dithering Pattern DP6_7 Register"
|
|
hexmask.long 0x1c 0.--27. 1. " DP6_7 ,Pattern value for 6/7 duty cycle"
|
|
line.long 0x20 "PWRCON,Power Control Register"
|
|
bitfld.long 0x20 31. " LCD_BUSY ,LCD Busy" "Idle,Busy"
|
|
hexmask.long.byte 0x20 1.--7. 1. " GUARD_TIME ,Guard Time"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LCD_PWR ,LCD module power control" "Low,High"
|
|
line.long 0x24 "CONTRAST_CTR,Contrast Control Register"
|
|
bitfld.long 0x24 3. " ENA ,PWM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " POL ,Output polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Prescaler" "fLCDC_CLOCK,fLCDC_CLOCK/2,fLCDC_CLOCK/4,fLCDC_CLOCK/8"
|
|
line.long 0x28 "CONTRAST_VAL,Contrast Value Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " CVAL ,PWM compare value"
|
|
group.long 0x850++0x3
|
|
line.long 0x0 "LCD_IMR,LCD Interrupt Mask Register"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " MERIM_set/clr ,DMA Memory error Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OWRIM_set/clr ,FIFO overwrite Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " UFLWIM_set/clr ,FIFO underflow Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EOFIM_set/clr ,DMA End of frame Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " LSTLNIM_set/clr ,Last line Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " LNIM_set/clr ,Line Interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x3
|
|
line.long 0x0 "LCD_ISR,LCD Interrupt Status Register"
|
|
bitfld.long 0x0 6. " MERIS ,DMA Memory error Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 5. " OWRIS ,FIFO overwrite Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UFLWIS ,FIFO underflow Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 2. " EOFIS ,DMA End of frame Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LSTLNIS ,Last line Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 0. " LNIS ,Line Interrupt status" "Not active,Active"
|
|
wgroup.long 0x858++0x3
|
|
line.long 0x00 "LCD_ICR,LCD Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MERIC ,DMA Memory error Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OWRIC ,FIFO overwrite Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIC ,FIFO underflow Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " EOFIC ,DMA End of frame Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIC ,Last line Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " LNIC ,Line Interrupt clear" "No effect,Clear"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x860++03
|
|
line.long 0x00 "LCD_ITR,LCD Interrupt Test Register"
|
|
bitfld.long 0x00 6. " MERIT ,DMA Memory error interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 5. " OWRIT ,FIFO overwrite interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIT ,FIFO underflow interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 2. " EOFIT ,DMA End of frame interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIT ,Last line interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 0. " LNIT ,Line interrupt test" "No effect,Set"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
else
|
|
rgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "LCD_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "LCD_WPSR,LCD Write Protect Status Register"
|
|
in
|
|
endif
|
|
tree "Palette Entry Registers"
|
|
tree "0-63"
|
|
group.long 0xc00++0xff
|
|
line.long 0x0 "LUT_ENTRY_0 ,Palette Entry 0 "
|
|
line.long 0x4 "LUT_ENTRY_1 ,Palette Entry 1 "
|
|
line.long 0x8 "LUT_ENTRY_2 ,Palette Entry 2 "
|
|
line.long 0xC "LUT_ENTRY_3 ,Palette Entry 3 "
|
|
line.long 0x10 "LUT_ENTRY_4 ,Palette Entry 4 "
|
|
line.long 0x14 "LUT_ENTRY_5 ,Palette Entry 5 "
|
|
line.long 0x18 "LUT_ENTRY_6 ,Palette Entry 6 "
|
|
line.long 0x1C "LUT_ENTRY_7 ,Palette Entry 7 "
|
|
line.long 0x20 "LUT_ENTRY_8 ,Palette Entry 8 "
|
|
line.long 0x24 "LUT_ENTRY_9 ,Palette Entry 9 "
|
|
line.long 0x28 "LUT_ENTRY_10 ,Palette Entry 10 "
|
|
line.long 0x2C "LUT_ENTRY_11 ,Palette Entry 11 "
|
|
line.long 0x30 "LUT_ENTRY_12 ,Palette Entry 12 "
|
|
line.long 0x34 "LUT_ENTRY_13 ,Palette Entry 13 "
|
|
line.long 0x38 "LUT_ENTRY_14 ,Palette Entry 14 "
|
|
line.long 0x3C "LUT_ENTRY_15 ,Palette Entry 15 "
|
|
line.long 0x40 "LUT_ENTRY_16 ,Palette Entry 16 "
|
|
line.long 0x44 "LUT_ENTRY_17 ,Palette Entry 17 "
|
|
line.long 0x48 "LUT_ENTRY_18 ,Palette Entry 18 "
|
|
line.long 0x4C "LUT_ENTRY_19 ,Palette Entry 19 "
|
|
line.long 0x50 "LUT_ENTRY_20 ,Palette Entry 20 "
|
|
line.long 0x54 "LUT_ENTRY_21 ,Palette Entry 21 "
|
|
line.long 0x58 "LUT_ENTRY_22 ,Palette Entry 22 "
|
|
line.long 0x5C "LUT_ENTRY_23 ,Palette Entry 23 "
|
|
line.long 0x60 "LUT_ENTRY_24 ,Palette Entry 24 "
|
|
line.long 0x64 "LUT_ENTRY_25 ,Palette Entry 25 "
|
|
line.long 0x68 "LUT_ENTRY_26 ,Palette Entry 26 "
|
|
line.long 0x6C "LUT_ENTRY_27 ,Palette Entry 27 "
|
|
line.long 0x70 "LUT_ENTRY_28 ,Palette Entry 28 "
|
|
line.long 0x74 "LUT_ENTRY_29 ,Palette Entry 29 "
|
|
line.long 0x78 "LUT_ENTRY_30 ,Palette Entry 30 "
|
|
line.long 0x7C "LUT_ENTRY_31 ,Palette Entry 31 "
|
|
line.long 0x80 "LUT_ENTRY_32 ,Palette Entry 32 "
|
|
line.long 0x84 "LUT_ENTRY_33 ,Palette Entry 33 "
|
|
line.long 0x88 "LUT_ENTRY_34 ,Palette Entry 34 "
|
|
line.long 0x8C "LUT_ENTRY_35 ,Palette Entry 35 "
|
|
line.long 0x90 "LUT_ENTRY_36 ,Palette Entry 36 "
|
|
line.long 0x94 "LUT_ENTRY_37 ,Palette Entry 37 "
|
|
line.long 0x98 "LUT_ENTRY_38 ,Palette Entry 38 "
|
|
line.long 0x9C "LUT_ENTRY_39 ,Palette Entry 39 "
|
|
line.long 0xA0 "LUT_ENTRY_40 ,Palette Entry 40 "
|
|
line.long 0xA4 "LUT_ENTRY_41 ,Palette Entry 41 "
|
|
line.long 0xA8 "LUT_ENTRY_42 ,Palette Entry 42 "
|
|
line.long 0xAC "LUT_ENTRY_43 ,Palette Entry 43 "
|
|
line.long 0xB0 "LUT_ENTRY_44 ,Palette Entry 44 "
|
|
line.long 0xB4 "LUT_ENTRY_45 ,Palette Entry 45 "
|
|
line.long 0xB8 "LUT_ENTRY_46 ,Palette Entry 46 "
|
|
line.long 0xBC "LUT_ENTRY_47 ,Palette Entry 47 "
|
|
line.long 0xC0 "LUT_ENTRY_48 ,Palette Entry 48 "
|
|
line.long 0xC4 "LUT_ENTRY_49 ,Palette Entry 49 "
|
|
line.long 0xC8 "LUT_ENTRY_50 ,Palette Entry 50 "
|
|
line.long 0xCC "LUT_ENTRY_51 ,Palette Entry 51 "
|
|
line.long 0xD0 "LUT_ENTRY_52 ,Palette Entry 52 "
|
|
line.long 0xD4 "LUT_ENTRY_53 ,Palette Entry 53 "
|
|
line.long 0xD8 "LUT_ENTRY_54 ,Palette Entry 54 "
|
|
line.long 0xDC "LUT_ENTRY_55 ,Palette Entry 55 "
|
|
line.long 0xE0 "LUT_ENTRY_56 ,Palette Entry 56 "
|
|
line.long 0xE4 "LUT_ENTRY_57 ,Palette Entry 57 "
|
|
line.long 0xE8 "LUT_ENTRY_58 ,Palette Entry 58 "
|
|
line.long 0xEC "LUT_ENTRY_59 ,Palette Entry 59 "
|
|
line.long 0xF0 "LUT_ENTRY_60 ,Palette Entry 60 "
|
|
line.long 0xF4 "LUT_ENTRY_61 ,Palette Entry 61 "
|
|
line.long 0xF8 "LUT_ENTRY_62 ,Palette Entry 62 "
|
|
line.long 0xFC "LUT_ENTRY_63 ,Palette Entry 63 "
|
|
tree.end
|
|
tree "64-127"
|
|
group.long 0xd00++0xff
|
|
line.long 0x0 "LUT_ENTRY_64 ,Palette Entry 64 "
|
|
line.long 0x4 "LUT_ENTRY_65 ,Palette Entry 65 "
|
|
line.long 0x8 "LUT_ENTRY_66 ,Palette Entry 66 "
|
|
line.long 0xC "LUT_ENTRY_67 ,Palette Entry 67 "
|
|
line.long 0x10 "LUT_ENTRY_68 ,Palette Entry 68 "
|
|
line.long 0x14 "LUT_ENTRY_69 ,Palette Entry 69 "
|
|
line.long 0x18 "LUT_ENTRY_70 ,Palette Entry 70 "
|
|
line.long 0x1C "LUT_ENTRY_71 ,Palette Entry 71 "
|
|
line.long 0x20 "LUT_ENTRY_72 ,Palette Entry 72 "
|
|
line.long 0x24 "LUT_ENTRY_73 ,Palette Entry 73 "
|
|
line.long 0x28 "LUT_ENTRY_74 ,Palette Entry 74 "
|
|
line.long 0x2C "LUT_ENTRY_75 ,Palette Entry 75 "
|
|
line.long 0x30 "LUT_ENTRY_76 ,Palette Entry 76 "
|
|
line.long 0x34 "LUT_ENTRY_77 ,Palette Entry 77 "
|
|
line.long 0x38 "LUT_ENTRY_78 ,Palette Entry 78 "
|
|
line.long 0x3C "LUT_ENTRY_79 ,Palette Entry 79 "
|
|
line.long 0x40 "LUT_ENTRY_80 ,Palette Entry 80 "
|
|
line.long 0x44 "LUT_ENTRY_81 ,Palette Entry 81 "
|
|
line.long 0x48 "LUT_ENTRY_82 ,Palette Entry 82 "
|
|
line.long 0x4C "LUT_ENTRY_83 ,Palette Entry 83 "
|
|
line.long 0x50 "LUT_ENTRY_84 ,Palette Entry 84 "
|
|
line.long 0x54 "LUT_ENTRY_85 ,Palette Entry 85 "
|
|
line.long 0x58 "LUT_ENTRY_86 ,Palette Entry 86 "
|
|
line.long 0x5C "LUT_ENTRY_87 ,Palette Entry 87 "
|
|
line.long 0x60 "LUT_ENTRY_88 ,Palette Entry 88 "
|
|
line.long 0x64 "LUT_ENTRY_89 ,Palette Entry 89 "
|
|
line.long 0x68 "LUT_ENTRY_90 ,Palette Entry 90 "
|
|
line.long 0x6C "LUT_ENTRY_91 ,Palette Entry 91 "
|
|
line.long 0x70 "LUT_ENTRY_92 ,Palette Entry 92 "
|
|
line.long 0x74 "LUT_ENTRY_93 ,Palette Entry 93 "
|
|
line.long 0x78 "LUT_ENTRY_94 ,Palette Entry 94 "
|
|
line.long 0x7C "LUT_ENTRY_95 ,Palette Entry 95 "
|
|
line.long 0x80 "LUT_ENTRY_96 ,Palette Entry 96 "
|
|
line.long 0x84 "LUT_ENTRY_97 ,Palette Entry 97 "
|
|
line.long 0x88 "LUT_ENTRY_98 ,Palette Entry 98 "
|
|
line.long 0x8C "LUT_ENTRY_99 ,Palette Entry 99 "
|
|
line.long 0x90 "LUT_ENTRY_100,Palette Entry 100"
|
|
line.long 0x94 "LUT_ENTRY_101,Palette Entry 101"
|
|
line.long 0x98 "LUT_ENTRY_102,Palette Entry 102"
|
|
line.long 0x9C "LUT_ENTRY_103,Palette Entry 103"
|
|
line.long 0xA0 "LUT_ENTRY_104,Palette Entry 104"
|
|
line.long 0xA4 "LUT_ENTRY_105,Palette Entry 105"
|
|
line.long 0xA8 "LUT_ENTRY_106,Palette Entry 106"
|
|
line.long 0xAC "LUT_ENTRY_107,Palette Entry 107"
|
|
line.long 0xB0 "LUT_ENTRY_108,Palette Entry 108"
|
|
line.long 0xB4 "LUT_ENTRY_109,Palette Entry 109"
|
|
line.long 0xB8 "LUT_ENTRY_110,Palette Entry 110"
|
|
line.long 0xBC "LUT_ENTRY_111,Palette Entry 111"
|
|
line.long 0xC0 "LUT_ENTRY_112,Palette Entry 112"
|
|
line.long 0xC4 "LUT_ENTRY_113,Palette Entry 113"
|
|
line.long 0xC8 "LUT_ENTRY_114,Palette Entry 114"
|
|
line.long 0xCC "LUT_ENTRY_115,Palette Entry 115"
|
|
line.long 0xD0 "LUT_ENTRY_116,Palette Entry 116"
|
|
line.long 0xD4 "LUT_ENTRY_117,Palette Entry 117"
|
|
line.long 0xD8 "LUT_ENTRY_118,Palette Entry 118"
|
|
line.long 0xDC "LUT_ENTRY_119,Palette Entry 119"
|
|
line.long 0xE0 "LUT_ENTRY_120,Palette Entry 120"
|
|
line.long 0xE4 "LUT_ENTRY_121,Palette Entry 121"
|
|
line.long 0xE8 "LUT_ENTRY_122,Palette Entry 122"
|
|
line.long 0xEC "LUT_ENTRY_123,Palette Entry 123"
|
|
line.long 0xF0 "LUT_ENTRY_124,Palette Entry 124"
|
|
line.long 0xF4 "LUT_ENTRY_125,Palette Entry 125"
|
|
line.long 0xF8 "LUT_ENTRY_126,Palette Entry 126"
|
|
line.long 0xFC "LUT_ENTRY_127,Palette Entry 127"
|
|
tree.end
|
|
tree "128-191"
|
|
group.long 0xe00++0xff
|
|
line.long 0x0 "LUT_ENTRY_128,Palette Entry 128"
|
|
line.long 0x4 "LUT_ENTRY_129,Palette Entry 129"
|
|
line.long 0x8 "LUT_ENTRY_130,Palette Entry 130"
|
|
line.long 0xC "LUT_ENTRY_131,Palette Entry 131"
|
|
line.long 0x10 "LUT_ENTRY_132,Palette Entry 132"
|
|
line.long 0x14 "LUT_ENTRY_133,Palette Entry 133"
|
|
line.long 0x18 "LUT_ENTRY_134,Palette Entry 134"
|
|
line.long 0x1C "LUT_ENTRY_135,Palette Entry 135"
|
|
line.long 0x20 "LUT_ENTRY_136,Palette Entry 136"
|
|
line.long 0x24 "LUT_ENTRY_137,Palette Entry 137"
|
|
line.long 0x28 "LUT_ENTRY_138,Palette Entry 138"
|
|
line.long 0x2C "LUT_ENTRY_139,Palette Entry 139"
|
|
line.long 0x30 "LUT_ENTRY_140,Palette Entry 140"
|
|
line.long 0x34 "LUT_ENTRY_141,Palette Entry 141"
|
|
line.long 0x38 "LUT_ENTRY_142,Palette Entry 142"
|
|
line.long 0x3C "LUT_ENTRY_143,Palette Entry 143"
|
|
line.long 0x40 "LUT_ENTRY_144,Palette Entry 144"
|
|
line.long 0x44 "LUT_ENTRY_145,Palette Entry 145"
|
|
line.long 0x48 "LUT_ENTRY_146,Palette Entry 146"
|
|
line.long 0x4C "LUT_ENTRY_147,Palette Entry 147"
|
|
line.long 0x50 "LUT_ENTRY_148,Palette Entry 148"
|
|
line.long 0x54 "LUT_ENTRY_149,Palette Entry 149"
|
|
line.long 0x58 "LUT_ENTRY_150,Palette Entry 150"
|
|
line.long 0x5C "LUT_ENTRY_151,Palette Entry 151"
|
|
line.long 0x60 "LUT_ENTRY_152,Palette Entry 152"
|
|
line.long 0x64 "LUT_ENTRY_153,Palette Entry 153"
|
|
line.long 0x68 "LUT_ENTRY_154,Palette Entry 154"
|
|
line.long 0x6C "LUT_ENTRY_155,Palette Entry 155"
|
|
line.long 0x70 "LUT_ENTRY_156,Palette Entry 156"
|
|
line.long 0x74 "LUT_ENTRY_157,Palette Entry 157"
|
|
line.long 0x78 "LUT_ENTRY_158,Palette Entry 158"
|
|
line.long 0x7C "LUT_ENTRY_159,Palette Entry 159"
|
|
line.long 0x80 "LUT_ENTRY_160,Palette Entry 160"
|
|
line.long 0x84 "LUT_ENTRY_161,Palette Entry 161"
|
|
line.long 0x88 "LUT_ENTRY_162,Palette Entry 162"
|
|
line.long 0x8C "LUT_ENTRY_163,Palette Entry 163"
|
|
line.long 0x90 "LUT_ENTRY_164,Palette Entry 164"
|
|
line.long 0x94 "LUT_ENTRY_165,Palette Entry 165"
|
|
line.long 0x98 "LUT_ENTRY_166,Palette Entry 166"
|
|
line.long 0x9C "LUT_ENTRY_167,Palette Entry 167"
|
|
line.long 0xA0 "LUT_ENTRY_168,Palette Entry 168"
|
|
line.long 0xA4 "LUT_ENTRY_169,Palette Entry 169"
|
|
line.long 0xA8 "LUT_ENTRY_170,Palette Entry 170"
|
|
line.long 0xAC "LUT_ENTRY_171,Palette Entry 171"
|
|
line.long 0xB0 "LUT_ENTRY_172,Palette Entry 172"
|
|
line.long 0xB4 "LUT_ENTRY_173,Palette Entry 173"
|
|
line.long 0xB8 "LUT_ENTRY_174,Palette Entry 174"
|
|
line.long 0xBC "LUT_ENTRY_175,Palette Entry 175"
|
|
line.long 0xC0 "LUT_ENTRY_176,Palette Entry 176"
|
|
line.long 0xC4 "LUT_ENTRY_177,Palette Entry 177"
|
|
line.long 0xC8 "LUT_ENTRY_178,Palette Entry 178"
|
|
line.long 0xCC "LUT_ENTRY_179,Palette Entry 179"
|
|
line.long 0xD0 "LUT_ENTRY_180,Palette Entry 180"
|
|
line.long 0xD4 "LUT_ENTRY_181,Palette Entry 181"
|
|
line.long 0xD8 "LUT_ENTRY_182,Palette Entry 182"
|
|
line.long 0xDC "LUT_ENTRY_183,Palette Entry 183"
|
|
line.long 0xE0 "LUT_ENTRY_184,Palette Entry 184"
|
|
line.long 0xE4 "LUT_ENTRY_185,Palette Entry 185"
|
|
line.long 0xE8 "LUT_ENTRY_186,Palette Entry 186"
|
|
line.long 0xEC "LUT_ENTRY_187,Palette Entry 187"
|
|
line.long 0xF0 "LUT_ENTRY_188,Palette Entry 188"
|
|
line.long 0xF4 "LUT_ENTRY_189,Palette Entry 189"
|
|
line.long 0xF8 "LUT_ENTRY_190,Palette Entry 190"
|
|
line.long 0xFC "LUT_ENTRY_191,Palette Entry 191"
|
|
tree.end
|
|
tree "192-255"
|
|
group.long 0xf00++0xff
|
|
line.long 0x0 "LUT_ENTRY_192,Palette Entry 192"
|
|
line.long 0x4 "LUT_ENTRY_193,Palette Entry 193"
|
|
line.long 0x8 "LUT_ENTRY_194,Palette Entry 194"
|
|
line.long 0xC "LUT_ENTRY_195,Palette Entry 195"
|
|
line.long 0x10 "LUT_ENTRY_196,Palette Entry 196"
|
|
line.long 0x14 "LUT_ENTRY_197,Palette Entry 197"
|
|
line.long 0x18 "LUT_ENTRY_198,Palette Entry 198"
|
|
line.long 0x1C "LUT_ENTRY_199,Palette Entry 199"
|
|
line.long 0x20 "LUT_ENTRY_200,Palette Entry 200"
|
|
line.long 0x24 "LUT_ENTRY_201,Palette Entry 201"
|
|
line.long 0x28 "LUT_ENTRY_202,Palette Entry 202"
|
|
line.long 0x2C "LUT_ENTRY_203,Palette Entry 203"
|
|
line.long 0x30 "LUT_ENTRY_204,Palette Entry 204"
|
|
line.long 0x34 "LUT_ENTRY_205,Palette Entry 205"
|
|
line.long 0x38 "LUT_ENTRY_206,Palette Entry 206"
|
|
line.long 0x3C "LUT_ENTRY_207,Palette Entry 207"
|
|
line.long 0x40 "LUT_ENTRY_208,Palette Entry 208"
|
|
line.long 0x44 "LUT_ENTRY_209,Palette Entry 209"
|
|
line.long 0x48 "LUT_ENTRY_210,Palette Entry 210"
|
|
line.long 0x4C "LUT_ENTRY_211,Palette Entry 211"
|
|
line.long 0x50 "LUT_ENTRY_212,Palette Entry 212"
|
|
line.long 0x54 "LUT_ENTRY_213,Palette Entry 213"
|
|
line.long 0x58 "LUT_ENTRY_214,Palette Entry 214"
|
|
line.long 0x5C "LUT_ENTRY_215,Palette Entry 215"
|
|
line.long 0x60 "LUT_ENTRY_216,Palette Entry 216"
|
|
line.long 0x64 "LUT_ENTRY_217,Palette Entry 217"
|
|
line.long 0x68 "LUT_ENTRY_218,Palette Entry 218"
|
|
line.long 0x6C "LUT_ENTRY_219,Palette Entry 219"
|
|
line.long 0x70 "LUT_ENTRY_220,Palette Entry 220"
|
|
line.long 0x74 "LUT_ENTRY_221,Palette Entry 221"
|
|
line.long 0x78 "LUT_ENTRY_222,Palette Entry 222"
|
|
line.long 0x7C "LUT_ENTRY_223,Palette Entry 223"
|
|
line.long 0x80 "LUT_ENTRY_224,Palette Entry 224"
|
|
line.long 0x84 "LUT_ENTRY_225,Palette Entry 225"
|
|
line.long 0x88 "LUT_ENTRY_226,Palette Entry 226"
|
|
line.long 0x8C "LUT_ENTRY_227,Palette Entry 227"
|
|
line.long 0x90 "LUT_ENTRY_228,Palette Entry 228"
|
|
line.long 0x94 "LUT_ENTRY_229,Palette Entry 229"
|
|
line.long 0x98 "LUT_ENTRY_230,Palette Entry 230"
|
|
line.long 0x9C "LUT_ENTRY_231,Palette Entry 231"
|
|
line.long 0xA0 "LUT_ENTRY_232,Palette Entry 232"
|
|
line.long 0xA4 "LUT_ENTRY_233,Palette Entry 233"
|
|
line.long 0xA8 "LUT_ENTRY_234,Palette Entry 234"
|
|
line.long 0xAC "LUT_ENTRY_235,Palette Entry 235"
|
|
line.long 0xB0 "LUT_ENTRY_236,Palette Entry 236"
|
|
line.long 0xB4 "LUT_ENTRY_237,Palette Entry 237"
|
|
line.long 0xB8 "LUT_ENTRY_238,Palette Entry 238"
|
|
line.long 0xBC "LUT_ENTRY_239,Palette Entry 239"
|
|
line.long 0xC0 "LUT_ENTRY_240,Palette Entry 240"
|
|
line.long 0xC4 "LUT_ENTRY_241,Palette Entry 241"
|
|
line.long 0xC8 "LUT_ENTRY_242,Palette Entry 242"
|
|
line.long 0xCC "LUT_ENTRY_243,Palette Entry 243"
|
|
line.long 0xD0 "LUT_ENTRY_244,Palette Entry 244"
|
|
line.long 0xD4 "LUT_ENTRY_245,Palette Entry 245"
|
|
line.long 0xD8 "LUT_ENTRY_246,Palette Entry 246"
|
|
line.long 0xDC "LUT_ENTRY_247,Palette Entry 247"
|
|
line.long 0xE0 "LUT_ENTRY_248,Palette Entry 248"
|
|
line.long 0xE4 "LUT_ENTRY_249,Palette Entry 249"
|
|
line.long 0xE8 "LUT_ENTRY_250,Palette Entry 250"
|
|
line.long 0xEC "LUT_ENTRY_251,Palette Entry 251"
|
|
line.long 0xF0 "LUT_ENTRY_252,Palette Entry 252"
|
|
line.long 0xF4 "LUT_ENTRY_253,Palette Entry 253"
|
|
line.long 0xF8 "LUT_ENTRY_254,Palette Entry 254"
|
|
line.long 0xFC "LUT_ENTRY_255,Palette Entry 255"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9G46")
|
|
base ad:0x00500000
|
|
width 14.
|
|
group.long 0x00++0x7
|
|
sif (cpuis("AT91CAP9*")||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
hexmask.long 0x00 2.--31. 0x4 " BADDR-U ,Base Address for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
else
|
|
line.long 0x00 "DMABADDR1,DMA Base Address Register 1"
|
|
endif
|
|
line.long 0x04 "DMABADDR2,DMA Base Address Register 2"
|
|
rgroup.long 0x08++0xf
|
|
line.long 0x00 "DMAFRMPT1,DMA Frame Pointer Register 1"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMPT-U ,Current value of frame pointer for the upper panel in dual scan mode/complete frame in single scan mode"
|
|
line.long 0x04 "DMAFRMPT2,DMA Frame Pointer Register 2"
|
|
hexmask.long.tbyte 0x04 0.--22. 1. " FRMPT-L ,Current value of frame pointer for the Lower panel in dual scan mode"
|
|
line.long 0x8 "DMAFRMADD1,DMA Frame Address Register 1"
|
|
line.long 0xC "DMAFRMADD2,DMA Frame Address Register 2"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DMAFRMCFG,DMA Frame Configuration Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BRSTLN ,Burst Length"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. " FRMSIZE ,Frame Size"
|
|
line.long 0x4 "DMACON,DMA Control Register"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x4 4. " DMA2DEN ,DMA 2D Adressing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " DMAUPDT ,DMA Configuration Update" "No effect,Updated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 2. " DMABUSY ,DMA Busy" "Idle,Busy"
|
|
bitfld.long 0x4 1. " DMARST ,DMA Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x20++0x03
|
|
line.long 0x0 "DMA2DCFG,DMA 2D Adressing Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " PIXELOFF ,DAM2D Addressing Pixel Offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRINC ,DMA 2D Addressing Address increment"
|
|
endif
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LCDCON1,LCD Control Register 1"
|
|
hexmask.long.word 0x00 21.--31. 1. " LINECNT ,Line Counter"
|
|
hexmask.long.word 0x00 12.--20. 1. " CLKVAL ,Clock Divider"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass lcd_pclk Divider" "Not bypassed,Bypassed"
|
|
if ((d.l(ad:0x00500000+0x804)&0x3)==0x2)
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,24 bpp/unpacked,?..."
|
|
else
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp/packed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00500000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00500000+0x804)&0x4)==(0x4)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "Reserved,8-bit,16-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
elif (((d.l(ad:0x00500000+0x804)&0x3)==(0x0||0x1))&&((d.l(ad:0x00500000+0x804)&0x4)==(0x0)))
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IFWIDTH ,Interface Width" "4-bit,8-bit,?..."
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
else
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "LCDCON2,LCD Control Register 2"
|
|
bitfld.long 0x00 30.--31. " MEMOR ,Memory Ordering Format" "Big endian,Reserved,Little endian,WinCE"
|
|
bitfld.long 0x00 15. " CLKMOD ,lcd_pclk mode" "During display,Always"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVDVAL ,lcd_dval polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 11. " INVCLK ,lcd_pclk polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INVLINE ,lcd_hsync polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " INVFRAME ,lcd_vsync polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INVVD ,LCDD polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 5.--7. " PIXELSIZE ,Bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCANMOD ,Scan Mode" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DISTYPE ,Display Type" "STN mono,STN color,TFT,?..."
|
|
endif
|
|
group.long 0x808++0xf
|
|
line.long 0x0 "LCDTIM1,LCD Timing Configuration Register 1"
|
|
bitfld.long 0x0 24.--27. " VHDLY ,Vertical to horizontal delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0 16.--21. 1. 1. " VPW ,Vertical Synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VFP ,Vertical Front Porch"
|
|
line.long 0x4 "LCDTIM2,LCD Timing Configuration Register 2"
|
|
hexmask.long.word 0x4 21.--31. 1. 1. " HFP ,Horizontal Front Porch"
|
|
hexmask.long.byte 0x4 8.--13. 1. 1. " HPW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--7. 1. 1. " HBP ,Horizontal Back Porch"
|
|
line.long 0x8 "LCDFRMCFG,LCD Frame Configuration Register"
|
|
sif (cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpu()=="AT91SAM9263"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
hexmask.long.word 0x8 21.--31. 1. " LINESIZE ,Horizontal size of LCD module"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x8 21.--31. 1. " HOZVAL ,Horizontal size of LCD module"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x8 0.--10. 1. " LINEVAL ,Vertical size of LCD module"
|
|
line.long 0xC "LCDFIFO,LCD FIFO Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " FIFOTH ,FIFO Threshold"
|
|
sif (cpu()=="AT91SAM9261"||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0x818++0x3
|
|
line.long 0x0 "LCDMVAL,LCD_MODE Toggle Rate Value Register"
|
|
bitfld.long 0x0 31. " MMODE ,LCD_MODE toggle rate select" "Each frame,MVAL"
|
|
hexmask.long.byte 0x0 0.--7. 1. 1. " MVAL ,LCD_MODE toggle rate value"
|
|
endif
|
|
group.long 0x81c--0x847
|
|
line.long 0x00 "DP1_2,Dithering Pattern DP1_2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DP1_2 ,Pattern value for 1/2 duty cycle"
|
|
line.long 0x04 "DP4_7,Dithering Pattern DP4_7 Register"
|
|
hexmask.long 0x04 0.--27. 1. " DP4_7 ,Pattern value for 4/7 duty cycle"
|
|
line.long 0x8 "DP3_5,Dithering Pattern DP3_5 Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. " DP3_5 ,Pattern value for 3/5 duty cycle"
|
|
line.long 0xc "DP2_3,Dithering Pattern DP2_3 Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " DP2_3 ,Pattern value for 2/3 duty cycle"
|
|
line.long 0x10 "DP5_7,Dithering Pattern DP5_7 Register"
|
|
hexmask.long 0x10 0.--27. 1. " DP5_7 ,Pattern value for 5/7 duty cycle"
|
|
line.long 0x14 "DP3_4,Dithering Pattern DP3_4 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DP3_4 ,Pattern value for 3/4 duty cycle"
|
|
line.long 0x18 "DP4_5,Dithering Pattern DP4_5 Register"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " DP4_5 ,Pattern value for 4/5 duty cycle"
|
|
line.long 0x1c "DP6_7,Dithering Pattern DP6_7 Register"
|
|
hexmask.long 0x1c 0.--27. 1. " DP6_7 ,Pattern value for 6/7 duty cycle"
|
|
line.long 0x20 "PWRCON,Power Control Register"
|
|
bitfld.long 0x20 31. " LCD_BUSY ,LCD Busy" "Idle,Busy"
|
|
hexmask.long.byte 0x20 1.--7. 1. " GUARD_TIME ,Guard Time"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LCD_PWR ,LCD module power control" "Low,High"
|
|
line.long 0x24 "CONTRAST_CTR,Contrast Control Register"
|
|
bitfld.long 0x24 3. " ENA ,PWM Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " POL ,Output polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Prescaler" "fLCDC_CLOCK,fLCDC_CLOCK/2,fLCDC_CLOCK/4,fLCDC_CLOCK/8"
|
|
line.long 0x28 "CONTRAST_VAL,Contrast Value Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " CVAL ,PWM compare value"
|
|
group.long 0x850++0x3
|
|
line.long 0x0 "LCD_IMR,LCD Interrupt Mask Register"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " MERIM_set/clr ,DMA Memory error Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " OWRIM_set/clr ,FIFO overwrite Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " UFLWIM_set/clr ,FIFO underflow Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EOFIM_set/clr ,DMA End of frame Interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " LSTLNIM_set/clr ,Last line Interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " LNIM_set/clr ,Line Interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x3
|
|
line.long 0x0 "LCD_ISR,LCD Interrupt Status Register"
|
|
bitfld.long 0x0 6. " MERIS ,DMA Memory error Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 5. " OWRIS ,FIFO overwrite Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UFLWIS ,FIFO underflow Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 2. " EOFIS ,DMA End of frame Interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LSTLNIS ,Last line Interrupt status" "Not active,Active"
|
|
bitfld.long 0x0 0. " LNIS ,Line Interrupt status" "Not active,Active"
|
|
wgroup.long 0x858++0x3
|
|
line.long 0x00 "LCD_ICR,LCD Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MERIC ,DMA Memory error Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OWRIC ,FIFO overwrite Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIC ,FIFO underflow Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " EOFIC ,DMA End of frame Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIC ,Last line Interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " LNIC ,Line Interrupt clear" "No effect,Clear"
|
|
sif (cpu()=="AT91SAM9263"||cpu()=="AT91SAM9R64"||cpu()=="AT91SAM9RL64"||cpuis("AT91CAP9*")||cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x860++03
|
|
line.long 0x00 "LCD_ITR,LCD Interrupt Test Register"
|
|
bitfld.long 0x00 6. " MERIT ,DMA Memory error interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 5. " OWRIT ,FIFO overwrite interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIT ,FIFO underflow interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 2. " EOFIT ,DMA End of frame interrupt test" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIT ,Last line interrupt test" "No effect,Set"
|
|
bitfld.long 0x00 0. " LNIT ,Line interrupt test" "No effect,Set"
|
|
sif (cpu()=="AT91SAM9M11")
|
|
wgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
else
|
|
rgroup.long 0x864++3
|
|
line.long 0x00 "LCD_IRR,LCD Interrupt Raw Status Register"
|
|
bitfld.long 0x00 6. " MERIR ,DMA Memory error interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " OWRIR ,FIFO overwrite interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFLWIR ,FIFO underflow interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 2. " EOFIR ,DMA End of frame interrupt test" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSTLNIR ,Last line interrupt test" "No effect,Interrupt"
|
|
bitfld.long 0x00 0. " LNIR ,Line interrupt test" "No effect,Interrupt"
|
|
endif
|
|
endif
|
|
sif (cpu()=="AT91SAM9G45"||cpu()=="AT91SAM9M10"||cpu()=="AT91SAM9G46"||cpu()=="AT91SAM9M11")
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "LCD_WPMR,TSADCC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "LCD_WPSR,LCD Write Protect Status Register"
|
|
in
|
|
endif
|
|
tree "Palette Entry Registers"
|
|
tree "0-63"
|
|
group.long 0xc00++0xff
|
|
line.long 0x0 "LUT_ENTRY_0 ,Palette Entry 0 "
|
|
line.long 0x4 "LUT_ENTRY_1 ,Palette Entry 1 "
|
|
line.long 0x8 "LUT_ENTRY_2 ,Palette Entry 2 "
|
|
line.long 0xC "LUT_ENTRY_3 ,Palette Entry 3 "
|
|
line.long 0x10 "LUT_ENTRY_4 ,Palette Entry 4 "
|
|
line.long 0x14 "LUT_ENTRY_5 ,Palette Entry 5 "
|
|
line.long 0x18 "LUT_ENTRY_6 ,Palette Entry 6 "
|
|
line.long 0x1C "LUT_ENTRY_7 ,Palette Entry 7 "
|
|
line.long 0x20 "LUT_ENTRY_8 ,Palette Entry 8 "
|
|
line.long 0x24 "LUT_ENTRY_9 ,Palette Entry 9 "
|
|
line.long 0x28 "LUT_ENTRY_10 ,Palette Entry 10 "
|
|
line.long 0x2C "LUT_ENTRY_11 ,Palette Entry 11 "
|
|
line.long 0x30 "LUT_ENTRY_12 ,Palette Entry 12 "
|
|
line.long 0x34 "LUT_ENTRY_13 ,Palette Entry 13 "
|
|
line.long 0x38 "LUT_ENTRY_14 ,Palette Entry 14 "
|
|
line.long 0x3C "LUT_ENTRY_15 ,Palette Entry 15 "
|
|
line.long 0x40 "LUT_ENTRY_16 ,Palette Entry 16 "
|
|
line.long 0x44 "LUT_ENTRY_17 ,Palette Entry 17 "
|
|
line.long 0x48 "LUT_ENTRY_18 ,Palette Entry 18 "
|
|
line.long 0x4C "LUT_ENTRY_19 ,Palette Entry 19 "
|
|
line.long 0x50 "LUT_ENTRY_20 ,Palette Entry 20 "
|
|
line.long 0x54 "LUT_ENTRY_21 ,Palette Entry 21 "
|
|
line.long 0x58 "LUT_ENTRY_22 ,Palette Entry 22 "
|
|
line.long 0x5C "LUT_ENTRY_23 ,Palette Entry 23 "
|
|
line.long 0x60 "LUT_ENTRY_24 ,Palette Entry 24 "
|
|
line.long 0x64 "LUT_ENTRY_25 ,Palette Entry 25 "
|
|
line.long 0x68 "LUT_ENTRY_26 ,Palette Entry 26 "
|
|
line.long 0x6C "LUT_ENTRY_27 ,Palette Entry 27 "
|
|
line.long 0x70 "LUT_ENTRY_28 ,Palette Entry 28 "
|
|
line.long 0x74 "LUT_ENTRY_29 ,Palette Entry 29 "
|
|
line.long 0x78 "LUT_ENTRY_30 ,Palette Entry 30 "
|
|
line.long 0x7C "LUT_ENTRY_31 ,Palette Entry 31 "
|
|
line.long 0x80 "LUT_ENTRY_32 ,Palette Entry 32 "
|
|
line.long 0x84 "LUT_ENTRY_33 ,Palette Entry 33 "
|
|
line.long 0x88 "LUT_ENTRY_34 ,Palette Entry 34 "
|
|
line.long 0x8C "LUT_ENTRY_35 ,Palette Entry 35 "
|
|
line.long 0x90 "LUT_ENTRY_36 ,Palette Entry 36 "
|
|
line.long 0x94 "LUT_ENTRY_37 ,Palette Entry 37 "
|
|
line.long 0x98 "LUT_ENTRY_38 ,Palette Entry 38 "
|
|
line.long 0x9C "LUT_ENTRY_39 ,Palette Entry 39 "
|
|
line.long 0xA0 "LUT_ENTRY_40 ,Palette Entry 40 "
|
|
line.long 0xA4 "LUT_ENTRY_41 ,Palette Entry 41 "
|
|
line.long 0xA8 "LUT_ENTRY_42 ,Palette Entry 42 "
|
|
line.long 0xAC "LUT_ENTRY_43 ,Palette Entry 43 "
|
|
line.long 0xB0 "LUT_ENTRY_44 ,Palette Entry 44 "
|
|
line.long 0xB4 "LUT_ENTRY_45 ,Palette Entry 45 "
|
|
line.long 0xB8 "LUT_ENTRY_46 ,Palette Entry 46 "
|
|
line.long 0xBC "LUT_ENTRY_47 ,Palette Entry 47 "
|
|
line.long 0xC0 "LUT_ENTRY_48 ,Palette Entry 48 "
|
|
line.long 0xC4 "LUT_ENTRY_49 ,Palette Entry 49 "
|
|
line.long 0xC8 "LUT_ENTRY_50 ,Palette Entry 50 "
|
|
line.long 0xCC "LUT_ENTRY_51 ,Palette Entry 51 "
|
|
line.long 0xD0 "LUT_ENTRY_52 ,Palette Entry 52 "
|
|
line.long 0xD4 "LUT_ENTRY_53 ,Palette Entry 53 "
|
|
line.long 0xD8 "LUT_ENTRY_54 ,Palette Entry 54 "
|
|
line.long 0xDC "LUT_ENTRY_55 ,Palette Entry 55 "
|
|
line.long 0xE0 "LUT_ENTRY_56 ,Palette Entry 56 "
|
|
line.long 0xE4 "LUT_ENTRY_57 ,Palette Entry 57 "
|
|
line.long 0xE8 "LUT_ENTRY_58 ,Palette Entry 58 "
|
|
line.long 0xEC "LUT_ENTRY_59 ,Palette Entry 59 "
|
|
line.long 0xF0 "LUT_ENTRY_60 ,Palette Entry 60 "
|
|
line.long 0xF4 "LUT_ENTRY_61 ,Palette Entry 61 "
|
|
line.long 0xF8 "LUT_ENTRY_62 ,Palette Entry 62 "
|
|
line.long 0xFC "LUT_ENTRY_63 ,Palette Entry 63 "
|
|
tree.end
|
|
tree "64-127"
|
|
group.long 0xd00++0xff
|
|
line.long 0x0 "LUT_ENTRY_64 ,Palette Entry 64 "
|
|
line.long 0x4 "LUT_ENTRY_65 ,Palette Entry 65 "
|
|
line.long 0x8 "LUT_ENTRY_66 ,Palette Entry 66 "
|
|
line.long 0xC "LUT_ENTRY_67 ,Palette Entry 67 "
|
|
line.long 0x10 "LUT_ENTRY_68 ,Palette Entry 68 "
|
|
line.long 0x14 "LUT_ENTRY_69 ,Palette Entry 69 "
|
|
line.long 0x18 "LUT_ENTRY_70 ,Palette Entry 70 "
|
|
line.long 0x1C "LUT_ENTRY_71 ,Palette Entry 71 "
|
|
line.long 0x20 "LUT_ENTRY_72 ,Palette Entry 72 "
|
|
line.long 0x24 "LUT_ENTRY_73 ,Palette Entry 73 "
|
|
line.long 0x28 "LUT_ENTRY_74 ,Palette Entry 74 "
|
|
line.long 0x2C "LUT_ENTRY_75 ,Palette Entry 75 "
|
|
line.long 0x30 "LUT_ENTRY_76 ,Palette Entry 76 "
|
|
line.long 0x34 "LUT_ENTRY_77 ,Palette Entry 77 "
|
|
line.long 0x38 "LUT_ENTRY_78 ,Palette Entry 78 "
|
|
line.long 0x3C "LUT_ENTRY_79 ,Palette Entry 79 "
|
|
line.long 0x40 "LUT_ENTRY_80 ,Palette Entry 80 "
|
|
line.long 0x44 "LUT_ENTRY_81 ,Palette Entry 81 "
|
|
line.long 0x48 "LUT_ENTRY_82 ,Palette Entry 82 "
|
|
line.long 0x4C "LUT_ENTRY_83 ,Palette Entry 83 "
|
|
line.long 0x50 "LUT_ENTRY_84 ,Palette Entry 84 "
|
|
line.long 0x54 "LUT_ENTRY_85 ,Palette Entry 85 "
|
|
line.long 0x58 "LUT_ENTRY_86 ,Palette Entry 86 "
|
|
line.long 0x5C "LUT_ENTRY_87 ,Palette Entry 87 "
|
|
line.long 0x60 "LUT_ENTRY_88 ,Palette Entry 88 "
|
|
line.long 0x64 "LUT_ENTRY_89 ,Palette Entry 89 "
|
|
line.long 0x68 "LUT_ENTRY_90 ,Palette Entry 90 "
|
|
line.long 0x6C "LUT_ENTRY_91 ,Palette Entry 91 "
|
|
line.long 0x70 "LUT_ENTRY_92 ,Palette Entry 92 "
|
|
line.long 0x74 "LUT_ENTRY_93 ,Palette Entry 93 "
|
|
line.long 0x78 "LUT_ENTRY_94 ,Palette Entry 94 "
|
|
line.long 0x7C "LUT_ENTRY_95 ,Palette Entry 95 "
|
|
line.long 0x80 "LUT_ENTRY_96 ,Palette Entry 96 "
|
|
line.long 0x84 "LUT_ENTRY_97 ,Palette Entry 97 "
|
|
line.long 0x88 "LUT_ENTRY_98 ,Palette Entry 98 "
|
|
line.long 0x8C "LUT_ENTRY_99 ,Palette Entry 99 "
|
|
line.long 0x90 "LUT_ENTRY_100,Palette Entry 100"
|
|
line.long 0x94 "LUT_ENTRY_101,Palette Entry 101"
|
|
line.long 0x98 "LUT_ENTRY_102,Palette Entry 102"
|
|
line.long 0x9C "LUT_ENTRY_103,Palette Entry 103"
|
|
line.long 0xA0 "LUT_ENTRY_104,Palette Entry 104"
|
|
line.long 0xA4 "LUT_ENTRY_105,Palette Entry 105"
|
|
line.long 0xA8 "LUT_ENTRY_106,Palette Entry 106"
|
|
line.long 0xAC "LUT_ENTRY_107,Palette Entry 107"
|
|
line.long 0xB0 "LUT_ENTRY_108,Palette Entry 108"
|
|
line.long 0xB4 "LUT_ENTRY_109,Palette Entry 109"
|
|
line.long 0xB8 "LUT_ENTRY_110,Palette Entry 110"
|
|
line.long 0xBC "LUT_ENTRY_111,Palette Entry 111"
|
|
line.long 0xC0 "LUT_ENTRY_112,Palette Entry 112"
|
|
line.long 0xC4 "LUT_ENTRY_113,Palette Entry 113"
|
|
line.long 0xC8 "LUT_ENTRY_114,Palette Entry 114"
|
|
line.long 0xCC "LUT_ENTRY_115,Palette Entry 115"
|
|
line.long 0xD0 "LUT_ENTRY_116,Palette Entry 116"
|
|
line.long 0xD4 "LUT_ENTRY_117,Palette Entry 117"
|
|
line.long 0xD8 "LUT_ENTRY_118,Palette Entry 118"
|
|
line.long 0xDC "LUT_ENTRY_119,Palette Entry 119"
|
|
line.long 0xE0 "LUT_ENTRY_120,Palette Entry 120"
|
|
line.long 0xE4 "LUT_ENTRY_121,Palette Entry 121"
|
|
line.long 0xE8 "LUT_ENTRY_122,Palette Entry 122"
|
|
line.long 0xEC "LUT_ENTRY_123,Palette Entry 123"
|
|
line.long 0xF0 "LUT_ENTRY_124,Palette Entry 124"
|
|
line.long 0xF4 "LUT_ENTRY_125,Palette Entry 125"
|
|
line.long 0xF8 "LUT_ENTRY_126,Palette Entry 126"
|
|
line.long 0xFC "LUT_ENTRY_127,Palette Entry 127"
|
|
tree.end
|
|
tree "128-191"
|
|
group.long 0xe00++0xff
|
|
line.long 0x0 "LUT_ENTRY_128,Palette Entry 128"
|
|
line.long 0x4 "LUT_ENTRY_129,Palette Entry 129"
|
|
line.long 0x8 "LUT_ENTRY_130,Palette Entry 130"
|
|
line.long 0xC "LUT_ENTRY_131,Palette Entry 131"
|
|
line.long 0x10 "LUT_ENTRY_132,Palette Entry 132"
|
|
line.long 0x14 "LUT_ENTRY_133,Palette Entry 133"
|
|
line.long 0x18 "LUT_ENTRY_134,Palette Entry 134"
|
|
line.long 0x1C "LUT_ENTRY_135,Palette Entry 135"
|
|
line.long 0x20 "LUT_ENTRY_136,Palette Entry 136"
|
|
line.long 0x24 "LUT_ENTRY_137,Palette Entry 137"
|
|
line.long 0x28 "LUT_ENTRY_138,Palette Entry 138"
|
|
line.long 0x2C "LUT_ENTRY_139,Palette Entry 139"
|
|
line.long 0x30 "LUT_ENTRY_140,Palette Entry 140"
|
|
line.long 0x34 "LUT_ENTRY_141,Palette Entry 141"
|
|
line.long 0x38 "LUT_ENTRY_142,Palette Entry 142"
|
|
line.long 0x3C "LUT_ENTRY_143,Palette Entry 143"
|
|
line.long 0x40 "LUT_ENTRY_144,Palette Entry 144"
|
|
line.long 0x44 "LUT_ENTRY_145,Palette Entry 145"
|
|
line.long 0x48 "LUT_ENTRY_146,Palette Entry 146"
|
|
line.long 0x4C "LUT_ENTRY_147,Palette Entry 147"
|
|
line.long 0x50 "LUT_ENTRY_148,Palette Entry 148"
|
|
line.long 0x54 "LUT_ENTRY_149,Palette Entry 149"
|
|
line.long 0x58 "LUT_ENTRY_150,Palette Entry 150"
|
|
line.long 0x5C "LUT_ENTRY_151,Palette Entry 151"
|
|
line.long 0x60 "LUT_ENTRY_152,Palette Entry 152"
|
|
line.long 0x64 "LUT_ENTRY_153,Palette Entry 153"
|
|
line.long 0x68 "LUT_ENTRY_154,Palette Entry 154"
|
|
line.long 0x6C "LUT_ENTRY_155,Palette Entry 155"
|
|
line.long 0x70 "LUT_ENTRY_156,Palette Entry 156"
|
|
line.long 0x74 "LUT_ENTRY_157,Palette Entry 157"
|
|
line.long 0x78 "LUT_ENTRY_158,Palette Entry 158"
|
|
line.long 0x7C "LUT_ENTRY_159,Palette Entry 159"
|
|
line.long 0x80 "LUT_ENTRY_160,Palette Entry 160"
|
|
line.long 0x84 "LUT_ENTRY_161,Palette Entry 161"
|
|
line.long 0x88 "LUT_ENTRY_162,Palette Entry 162"
|
|
line.long 0x8C "LUT_ENTRY_163,Palette Entry 163"
|
|
line.long 0x90 "LUT_ENTRY_164,Palette Entry 164"
|
|
line.long 0x94 "LUT_ENTRY_165,Palette Entry 165"
|
|
line.long 0x98 "LUT_ENTRY_166,Palette Entry 166"
|
|
line.long 0x9C "LUT_ENTRY_167,Palette Entry 167"
|
|
line.long 0xA0 "LUT_ENTRY_168,Palette Entry 168"
|
|
line.long 0xA4 "LUT_ENTRY_169,Palette Entry 169"
|
|
line.long 0xA8 "LUT_ENTRY_170,Palette Entry 170"
|
|
line.long 0xAC "LUT_ENTRY_171,Palette Entry 171"
|
|
line.long 0xB0 "LUT_ENTRY_172,Palette Entry 172"
|
|
line.long 0xB4 "LUT_ENTRY_173,Palette Entry 173"
|
|
line.long 0xB8 "LUT_ENTRY_174,Palette Entry 174"
|
|
line.long 0xBC "LUT_ENTRY_175,Palette Entry 175"
|
|
line.long 0xC0 "LUT_ENTRY_176,Palette Entry 176"
|
|
line.long 0xC4 "LUT_ENTRY_177,Palette Entry 177"
|
|
line.long 0xC8 "LUT_ENTRY_178,Palette Entry 178"
|
|
line.long 0xCC "LUT_ENTRY_179,Palette Entry 179"
|
|
line.long 0xD0 "LUT_ENTRY_180,Palette Entry 180"
|
|
line.long 0xD4 "LUT_ENTRY_181,Palette Entry 181"
|
|
line.long 0xD8 "LUT_ENTRY_182,Palette Entry 182"
|
|
line.long 0xDC "LUT_ENTRY_183,Palette Entry 183"
|
|
line.long 0xE0 "LUT_ENTRY_184,Palette Entry 184"
|
|
line.long 0xE4 "LUT_ENTRY_185,Palette Entry 185"
|
|
line.long 0xE8 "LUT_ENTRY_186,Palette Entry 186"
|
|
line.long 0xEC "LUT_ENTRY_187,Palette Entry 187"
|
|
line.long 0xF0 "LUT_ENTRY_188,Palette Entry 188"
|
|
line.long 0xF4 "LUT_ENTRY_189,Palette Entry 189"
|
|
line.long 0xF8 "LUT_ENTRY_190,Palette Entry 190"
|
|
line.long 0xFC "LUT_ENTRY_191,Palette Entry 191"
|
|
tree.end
|
|
tree "192-255"
|
|
group.long 0xf00++0xff
|
|
line.long 0x0 "LUT_ENTRY_192,Palette Entry 192"
|
|
line.long 0x4 "LUT_ENTRY_193,Palette Entry 193"
|
|
line.long 0x8 "LUT_ENTRY_194,Palette Entry 194"
|
|
line.long 0xC "LUT_ENTRY_195,Palette Entry 195"
|
|
line.long 0x10 "LUT_ENTRY_196,Palette Entry 196"
|
|
line.long 0x14 "LUT_ENTRY_197,Palette Entry 197"
|
|
line.long 0x18 "LUT_ENTRY_198,Palette Entry 198"
|
|
line.long 0x1C "LUT_ENTRY_199,Palette Entry 199"
|
|
line.long 0x20 "LUT_ENTRY_200,Palette Entry 200"
|
|
line.long 0x24 "LUT_ENTRY_201,Palette Entry 201"
|
|
line.long 0x28 "LUT_ENTRY_202,Palette Entry 202"
|
|
line.long 0x2C "LUT_ENTRY_203,Palette Entry 203"
|
|
line.long 0x30 "LUT_ENTRY_204,Palette Entry 204"
|
|
line.long 0x34 "LUT_ENTRY_205,Palette Entry 205"
|
|
line.long 0x38 "LUT_ENTRY_206,Palette Entry 206"
|
|
line.long 0x3C "LUT_ENTRY_207,Palette Entry 207"
|
|
line.long 0x40 "LUT_ENTRY_208,Palette Entry 208"
|
|
line.long 0x44 "LUT_ENTRY_209,Palette Entry 209"
|
|
line.long 0x48 "LUT_ENTRY_210,Palette Entry 210"
|
|
line.long 0x4C "LUT_ENTRY_211,Palette Entry 211"
|
|
line.long 0x50 "LUT_ENTRY_212,Palette Entry 212"
|
|
line.long 0x54 "LUT_ENTRY_213,Palette Entry 213"
|
|
line.long 0x58 "LUT_ENTRY_214,Palette Entry 214"
|
|
line.long 0x5C "LUT_ENTRY_215,Palette Entry 215"
|
|
line.long 0x60 "LUT_ENTRY_216,Palette Entry 216"
|
|
line.long 0x64 "LUT_ENTRY_217,Palette Entry 217"
|
|
line.long 0x68 "LUT_ENTRY_218,Palette Entry 218"
|
|
line.long 0x6C "LUT_ENTRY_219,Palette Entry 219"
|
|
line.long 0x70 "LUT_ENTRY_220,Palette Entry 220"
|
|
line.long 0x74 "LUT_ENTRY_221,Palette Entry 221"
|
|
line.long 0x78 "LUT_ENTRY_222,Palette Entry 222"
|
|
line.long 0x7C "LUT_ENTRY_223,Palette Entry 223"
|
|
line.long 0x80 "LUT_ENTRY_224,Palette Entry 224"
|
|
line.long 0x84 "LUT_ENTRY_225,Palette Entry 225"
|
|
line.long 0x88 "LUT_ENTRY_226,Palette Entry 226"
|
|
line.long 0x8C "LUT_ENTRY_227,Palette Entry 227"
|
|
line.long 0x90 "LUT_ENTRY_228,Palette Entry 228"
|
|
line.long 0x94 "LUT_ENTRY_229,Palette Entry 229"
|
|
line.long 0x98 "LUT_ENTRY_230,Palette Entry 230"
|
|
line.long 0x9C "LUT_ENTRY_231,Palette Entry 231"
|
|
line.long 0xA0 "LUT_ENTRY_232,Palette Entry 232"
|
|
line.long 0xA4 "LUT_ENTRY_233,Palette Entry 233"
|
|
line.long 0xA8 "LUT_ENTRY_234,Palette Entry 234"
|
|
line.long 0xAC "LUT_ENTRY_235,Palette Entry 235"
|
|
line.long 0xB0 "LUT_ENTRY_236,Palette Entry 236"
|
|
line.long 0xB4 "LUT_ENTRY_237,Palette Entry 237"
|
|
line.long 0xB8 "LUT_ENTRY_238,Palette Entry 238"
|
|
line.long 0xBC "LUT_ENTRY_239,Palette Entry 239"
|
|
line.long 0xC0 "LUT_ENTRY_240,Palette Entry 240"
|
|
line.long 0xC4 "LUT_ENTRY_241,Palette Entry 241"
|
|
line.long 0xC8 "LUT_ENTRY_242,Palette Entry 242"
|
|
line.long 0xCC "LUT_ENTRY_243,Palette Entry 243"
|
|
line.long 0xD0 "LUT_ENTRY_244,Palette Entry 244"
|
|
line.long 0xD4 "LUT_ENTRY_245,Palette Entry 245"
|
|
line.long 0xD8 "LUT_ENTRY_246,Palette Entry 246"
|
|
line.long 0xDC "LUT_ENTRY_247,Palette Entry 247"
|
|
line.long 0xE0 "LUT_ENTRY_248,Palette Entry 248"
|
|
line.long 0xE4 "LUT_ENTRY_249,Palette Entry 249"
|
|
line.long 0xE8 "LUT_ENTRY_250,Palette Entry 250"
|
|
line.long 0xEC "LUT_ENTRY_251,Palette Entry 251"
|
|
line.long 0xF0 "LUT_ENTRY_252,Palette Entry 252"
|
|
line.long 0xF4 "LUT_ENTRY_253,Palette Entry 253"
|
|
line.long 0xF8 "LUT_ENTRY_254,Palette Entry 254"
|
|
line.long 0xFC "LUT_ENTRY_255,Palette Entry 255"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
elif (cpu()=="AT91SAM9G15"||cpu()=="AT91SAM9G35")
|
|
base ad:0xF8038000
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "LCDC_LCDCFG0,LCD Controller Configuration Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLKDIV ,LCD Controller Clock Divider"
|
|
bitfld.long 0x00 12. " CGDISHCR ,Clock Gating Disable Control for the Hardware Cursor Layer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CGDISHEO ,Clock Gating Disable Control for the High End Overlay" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " CGDISOVR1 ,Clock Gating Disable Control for the Overlay 1 Layer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CGDISBASE ,Clock Gating Disable Control for the Base Layer" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " CLKPWMSEL ,LCD Controller PWM Clock Source Selection" "Slow clock,System clock"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CLKSEL ,LCD Controller Clock Source Selection" "MCK,2x MCK"
|
|
bitfld.long 0x00 0. " CLKPOL ,LCD Controller Clock Polarity" "Rising edge,Falling edge"
|
|
line.long 0x04 "LCDC_LCDCFG1,LCD Controller Configuration Register 1"
|
|
bitfld.long 0x04 16.--21. " VSPW ,Vertical Synchronization Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " HSPW ,Horizontal Synchronization Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "LCDC_LCDCFG2,LCD Controller Configuration Register 2"
|
|
bitfld.long 0x08 16.--21. " VBPW ,Vertical Back Porch Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " VFPW ,Vertical Front Porch Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "LCDC_LCDCFG3,LCD Controller Configuration Register 3"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HBPW ,Horizontal Back Porch Width"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " HFPW ,Horizontal Front Porch Width"
|
|
line.long 0x10 "LCDC_LCDCFG4,LCD Controller Configuration Register 4"
|
|
hexmask.long.word 0x10 16.--26. 1. " RPF ,Number of Active Rows Per Frame"
|
|
hexmask.long.word 0x10 0.--11. 1. " PPL ,Number of Pixels Per Line"
|
|
line.long 0x14 "LCDC_LCDCFG5,LCD Controller Configuration Register 5"
|
|
bitfld.long 0x14 16.--20. " GUARDTIME ,LCD DISPLAY Guard Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 13. " VSPHO ,LCD Controller Vertical Synchronization Pulse Hold Configuration" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 12. " VSPSU ,LCD Controller Vertical Synchronization Pulse Setup Configuration" "0,1"
|
|
bitfld.long 0x14 8.--9. " MODE ,LCD Controller Output Mode" "OUTPUT_12BPP,OUTPUT_16BPP,OUTPUT_18BPP,OUTPUT_24BPP"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DISPDLY ,LCD Controller Display Power Signal Synchronization" "Synchronously,Asynchronously"
|
|
bitfld.long 0x14 6. " DITHER ,LCD Controller Dithering" "Disabled,Activated"
|
|
textline " "
|
|
bitfld.long 0x14 4. " DISPPOL ,Display Signal Polarity" "Active High,Active Low"
|
|
bitfld.long 0x14 3. " VSPDLYE ,Vertical Synchronization Pulse End" "Second edge,First edge"
|
|
textline " "
|
|
bitfld.long 0x14 2. " VSPDLYS ,Vertical Synchronization Pulse Start" "Second edge,First edge"
|
|
bitfld.long 0x14 1. " VSPOL ,Vertical Synchronization Pulse Polarity" "Active High,Active Low"
|
|
textline " "
|
|
bitfld.long 0x14 0. " HSPOL ,Horizontal Synchronization Pulse Polarity" "Active High,Active Low"
|
|
line.long 0x18 "LCDC_LCDCFG6,LCD Controller Configuration Register 6"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PWMCVAL ,LCD Controller PWM Compare Value"
|
|
bitfld.long 0x18 4. " PWMPOL ,LCD Controller PWM Signal Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " PWMPS ,PWM Clock Prescaler" "fPWM_SELECTED_CLOCK,fPWM_SELECTED_CLOCK/2,fPWM_SELECTED_CLOCK/4,fPWM_SELECTED_CLOCK/8,fPWM_SELECTED_CLOCK/16,fPWM_SELECTED_CLOCK/32,fPWM_SELECTED_CLOCK/64,?..."
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "LCDC_LCDDIS,LCD Controller Disable Register"
|
|
bitfld.long 0x00 11. " PWMRST ,LCD Controller PWM Reset" "No effect,Reset"
|
|
bitfld.long 0x00 10. " DISPRST ,LCD Controller DISP Signal Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SYNCRST ,LCD Controller Horizontal and Vertical Synchronization Reset" "No effect,Reset"
|
|
bitfld.long 0x00 8. " CLKRST ,LCD Controller Clock Reset" "No effect,Reset"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "LCDC_LCDSR,LCD Controller Status Register"
|
|
bitfld.long 0x00 4. " SIPSTS ,Synchronization In Progress" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " PWMSTS_set/clr ,LCD Controller PWM Signal Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DISPSTS_set/clr ,LCD Controller DISP Signal Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LCDSTS_set/clr ,LCD Controller Synchronization status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CLKSTS_set/clr ,Clock Status" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "LCDC_LCDIMR,LCD Controller Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " HCRIM_set/clr ,Hardware Cursor Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " HEOIM_set/clr ,High End Overlay Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " OVR1IM_set/clr ,Overlay 1 Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " BASEIM_set/clr ,Base Layer Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " FIFOERRIM_set/clr ,Output FIFO Error Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DISPIM_set/clr ,Power UP/Down Sequence Terminated Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DISIM_set/clr ,LCD Disable Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " SOFIM_set/clr ,Start of Frame Interrupt Mask Register" "Disabled,Enabled"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "LCDC_LCDISR,LCD Controller Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x40++0x07
|
|
line.long 0x00 "LCDC_BASECHER,Base Layer Channel Enable Register"
|
|
bitfld.long 0x00 2. " A2QEN ,Add Head Pointer Enable Register" "Disabled,Enable"
|
|
bitfld.long 0x00 1. " UPDATEEN ,Update Overlay Attributes Enable Register" "No effect,Enable"
|
|
line.long 0x04 "LCDC_BASECHDR,Base Layer Channel Disable Register"
|
|
bitfld.long 0x04 8. " CHRST ,Channel Reset Register" "No effect,Reset"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LCDC_BASECHSR,Base Layer Channel Status Register"
|
|
bitfld.long 0x00 2. " A2QSR ,Add To Queue Pending Register" "Not added,Added"
|
|
bitfld.long 0x00 1. " UPDATESR ,Update Overlay Attributes In Progress" "No effect,In progress"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHSR_set/clr ,Channel Status Register" "Enabled,Disabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LCDC_BASEIMR,Base Layer Interrupt Mask Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVR_set/clr ,Overflow Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " DONE_set/clr ,End of List Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ADD_set/clr ,Head Descriptor Loaded Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " DSCR_set/clr ,Descriptor Loaded Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DMA_set/clr ,End of DMA Transfer Interrupt Mask Register" "Disabled,Enabled"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "LCDC_BASEISR,Base Layer Interrupt Status Register"
|
|
in
|
|
group.long 0x5C++0x23
|
|
line.long 0x00 "LCDC_BASEHEAD,Base Layer Head Register"
|
|
hexmask.long 0x00 2.--31. 1. " HEAD ,DMA Head Pointer"
|
|
line.long 0x04 "LCDC_BASEADDR,Base Layer Address Register"
|
|
line.long 0x08 "LCDC_BASECTRL,Base Layer Control Register"
|
|
bitfld.long 0x08 5. " DONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LFETCH ,Lookup Table Fetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x0C "LCDC_BASENEXT,Base Layer Next Register"
|
|
line.long 0x10 "LCDC_BASECFG0,Base Layer Configuration 0 Register"
|
|
bitfld.long 0x10 8. " DLBO ,Defined Length Burst Only For Channel Bus Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " BLEN ,AHB Burst Length" "AHB_SINGLE,AHB_INCR4,AHB_INCR8,AHB_INCR16"
|
|
line.long 0x14 "LCDC_BASECFG1,Base Layer Configuration 1 Register"
|
|
bitfld.long 0x14 8.--9. " CLUTMODE ,Color Lookup Table Input Mode Selection" "1BPP,2BPP,4BPP,8BPP"
|
|
bitfld.long 0x14 4.--7. " RGBMODE ,RGB Input Mode Selection" "12 bpp RGB 444,16 bpp ARGB 4444,16 bpp RGBA 4444,16 bpp RGB 565,16 bpp TRGB 1555,18 bpp RGB 666,18 bpp RGB 666 PACKED,19 bpp TRGB 1666,19 bpp TRGB 1666 PACKED,24 bpp RGB 888,24 bpp RGB 888 PACKED,25 bpp TRGB 1888,32 bpp ARGB 8888,32 bpp RGBA 8888,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0. " CLUTEN ,Color Lookup Table Enable" "RGB mode,Color lookup table"
|
|
line.long 0x18 "LCDC_BASECFG2,Base Layer Configuration 2 Register"
|
|
line.long 0x1C "LCDC_BASECFG3,Base Layer Configuration 3 Register"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " RDEF ,Red Default"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " GDEF ,Green Default"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BDEF ,Blue Default"
|
|
line.long 0x20 "LCDC_BASECFG4,Base Layer Configuration 4 Register"
|
|
bitfld.long 0x20 9. " REP ,Use Replication logic to expand RGB color to 24 bits" "Not used,Used"
|
|
bitfld.long 0x20 8. " DMA ,Use DMA Data Path" "Not used,Used"
|
|
wgroup.long 0x100++0x07
|
|
line.long 0x00 "LCDC_OVRCHER1,Overlay 1 Layer Channel Enable Register"
|
|
bitfld.long 0x00 2. " A2QEN ,Add Head Pointer Enable Register" "No effect,Add"
|
|
bitfld.long 0x00 1. " UPDATEEN ,Update Overlay Attributes Enable Register" "No effect,Update"
|
|
line.long 0x04 "LCDC_OVRCHDR1,Overlay 1 Layer Channel Disable Register"
|
|
bitfld.long 0x04 8. " CHRST ,Channel Reset Register" "No effect,Reset"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "LCDC_OVRCHSR1,Overlay 1 Layer Channel Status Register"
|
|
bitfld.long 0x00 2. " A2QSR ,Add to Queue Pending Register" "Not added,Added"
|
|
bitfld.long 0x00 1. " UPDATESR ,Update Overlay Attributes In Progress" "No effect,In progress"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHSR_set/clr ,Channel Status Register" "Enabled,Disabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "LCDC_OVRIMR1,Overlay 1 Layer Interrupt Mask Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVR_set/clr ,Overflow Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " DONE_set/clr ,End of List Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ADD_set/clr ,Head Descriptor Loaded Interrupt Mask Register" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " DSCR_set/clr ,Descriptor Loaded Interrupt Mask Register" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DMA_set/clr ,End of DMA Transfer Interrupt Mask Register" "Disabled,Enabled"
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "LCDC_OVRISR1,Overlay 1 Layer Interrupt Status Register"
|
|
in
|
|
group.long 0x11C++0x37
|
|
line.long 0x00 "LCDC_OVRHEAD1,Overlay 1 Layer Head Register"
|
|
hexmask.long 0x00 2.--31. 1. " HEAD ,DMA Head Pointer"
|
|
line.long 0x04 "LCDC_OVRADDR1,Overlay 1 Layer Address Register"
|
|
line.long 0x08 "LCDC_OVRCTRL1,Overlay 1 Layer Control Register"
|
|
bitfld.long 0x08 5. " DONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LFETCH ,Lookup Table Fetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x0C "LCDC_OVRNEXT1,Overlay 1 Layer Next Register"
|
|
line.long 0x10 "LCDC_OVR1CFG0,Overlay 1 Layer Configuration 0 Register"
|
|
bitfld.long 0x10 13. " LOCKDIS ,Hardware Rotation Lock Disable" "No,Yes"
|
|
bitfld.long 0x10 12. " ROTDIS ,Hardware Rotation Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 8. " DLBO ,Defined Length Burst Only for Channel Bus Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x10 4.--5. " BLEN ,AHB Burst Length" "AHB_SINGLE,AHB_INCR4,AHB_INCR8,AHB_INCR16"
|
|
line.long 0x14 "LCDC_BASECFG1,Base Layer Configuration 1 Register"
|
|
bitfld.long 0x14 8.--9. " CLUTMODE ,Color Lookup Table Input Mode Selection" "1BPP,2BPP,4BPP,8BPP"
|
|
bitfld.long 0x14 4.--7. " RGBMODE ,RGB Input Mode Selection" "12 bpp RGB 444,16 bpp ARGB 4444,16 bpp RGBA 4444,16 bpp RGB 565,16 bpp TRGB 1555,18 bpp RGB 666,18 bpp RGB 666 PACKED,19 bpp TRGB 1666,19 bpp TRGB 1666 PACKED,24 bpp RGB 888,24 bpp RGB 888 PACKED,25 bpp TRGB 1888,32 bpp ARGB 8888,32 bpp RGBA 8888,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0. " CLUTEN ,Color Lookup Table Enable" "RGB mode,Color lookup table"
|
|
line.long 0x18 "LCDC_OVR1CFG2,Overlay 1 Layer Configuration 2 Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " YPOS ,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. " XPOS ,Horizontal Window Position"
|
|
line.long 0x1C "LCDC_OVR1CFG3,Overlay 1 Layer Configuration 3 Register"
|
|
hexmask.long.word 0x1C 16.--26. 1. " YSIZE ,Vertical Window Size"
|
|
hexmask.long.word 0x1C 0.--10. 1. " XSIZE ,Horizontal Window Size"
|
|
line.long 0x20 "LCDC_OVR1CFG4,Overlay 1 Layer Configuration 4 Register"
|
|
line.long 0x24 "LCDC_OVR1CFG5,Overlay 1 Layer Configuration 5 Register"
|
|
line.long 0x28 "LCDC_OVR1CFG6,Overlay 1 Layer Configuration 6 Register"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RDEF ,Red Default"
|
|
textline " "
|
|
hexmask.long.byte 0x28 8.--15. 1. " GDEF ,Green Default"
|
|
textline " "
|
|
hexmask.long.byte 0x28 0.--7. 1. " BDEF ,Blue Default"
|
|
line.long 0x2C "LCDC_OVR1CFG7,Overlay 1 Layer Configuration 7 Register"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " RKEY ,Red Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " GKEY ,Green Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BKEY ,Blue Color Component Chroma Key"
|
|
line.long 0x30 "LCDC_OVR1CFG8,Overlay 1 Layer Configuration 8 Register"
|
|
hexmask.long.byte 0x30 16.--23. 1. " RMASK ,Red Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x30 8.--15. 1. " GMASK ,Green Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x30 0.--7. 1. " BMASK ,Blue Color Component Chroma Key Mask"
|
|
line.long 0x34 "LCDC_OVR1CFG9,Overlay1 Layer Configuration 9 Register"
|
|
hexmask.long.byte 0x34 16.--23. 1. " GA ,Blender Global Alpha"
|
|
bitfld.long 0x34 10. " DSTKEY ,Destination Chroma Keying" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 9. " REP ,Use Replication logic to expand RGB color to 24 bits" "Not used,Used"
|
|
bitfld.long 0x34 8. " DMA ,Blender DMA Layer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 7. " OVR ,Blender Overlay Layer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " LAEN ,Blender Local Alpha Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 5. " GAEN ,Blender Global Alpha Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 4. " REVALPHA ,Blender Reverse Alpha" "Not reversed,Reversed"
|
|
textline " "
|
|
bitfld.long 0x34 3. " ITER ,Blender Use Iterated Color" "Not used,Used"
|
|
bitfld.long 0x34 2. " ITER2BL ,Blender Iterated Color Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 1. " INV ,Blender Inverted Blender Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " CRKEY ,Blender Chroma Key Enable" "Disabled,Enabled"
|
|
wgroup.long 0x280++0x07
|
|
line.long 0x00 "LCDC_HEOCHER,High End Overlay Layer Channel Enable Register"
|
|
bitfld.long 0x00 2. " A2QEN ,Add Head Pointer Enable Register" "No effect,Add"
|
|
bitfld.long 0x00 1. " UPDATEEN ,Update Overlay Attributes Enable Register" "No effect,Update"
|
|
line.long 0x04 "LCDC_HEOCHDR,High End Overlay Layer Channel Disable Register"
|
|
bitfld.long 0x04 8. " CHRST ,Channel Reset Register" "No effect,Reset"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "LCDC_HEOCHSR,High End Overlay Layer Channel Status Register"
|
|
bitfld.long 0x00 2. " A2QSR ,Add to Queue Pending Register" "Not added,Added"
|
|
bitfld.long 0x00 1. " UPDATESR ,Update Overlay Attributes In Progress" "No effect,In progress"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHSR_set/clr ,Channel Status Register" "Enabled,Disabled"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "LCDC_HEOIMR,High End Overlay Layer Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " VOVR_set/clr ,Overflow for V Chrominance Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " VDONE_set/clr ,End of List for V Chrominance Component Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " VADD_set/clr ,Head Descriptor Loaded for V Chrominance Component Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " VDSCR_set/clr ,Descriptor Loaded for V Chrominance Component Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " VDMA_set/clr ,End of DMA Transfer for V Chrominance Component Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UOVR_set/clr ,Overflow for U Chrominance Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " UDONE_set/clr ,End of List for U or UV Chrominance Component Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " UADD_set/clr ,Head Descriptor Loaded for U or UV Chrominance Component Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " UDSCR_set/clr ,Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UDMA_set/clr ,End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVR_set/clr ,Overflow Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " DONE_set/clr ,End of List Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ADD_set/clr ,Head Descriptor Loaded Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " DSCR_set/clr ,Descriptor Loaded Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DMA_set/clr ,End of DMA Transfer Interrupt Mask Register" "Enabled,Disabled"
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "LCDC_HEOISR,High End Overlay Layer Interrupt Status Register"
|
|
in
|
|
group.long 0x29C++0x73
|
|
line.long 0x00 "LCDC_HEOHEAD,High End Overlay Layer Head Register"
|
|
hexmask.long 0x00 2.--31. 1. " HEAD ,DMA Head Pointer"
|
|
line.long 0x04 "LCDC_HEOADDR,High End Overlay Layer Address Register"
|
|
line.long 0x08 "LCDC_HEOCTRL,High End Overlay Layer Control Register"
|
|
bitfld.long 0x08 5. " DONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LFETCH ,Lookup Table Fetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x0C "LCDC_HEONEXT,High End Overlay Layer Next Register"
|
|
line.long 0x10 "LCDC_HEOUHEAD,High End Overlay Layer U-UV Head Register"
|
|
line.long 0x14 "LCDC_HEOUADDR,High End Overlay Layer U-UV Address Register"
|
|
line.long 0x18 "LCDC_HEOUCTRL,High End Overlay Layer U-UV Control Register"
|
|
bitfld.long 0x18 5. " UDONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " UADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " UDSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " UDMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " UDFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x1C "LCDC_HEOUNEXT,High End Overlay Layer U-UV Next Register"
|
|
line.long 0x20 "LCDC_HEOVHEAD,High End Overlay Layer V Head Register"
|
|
line.long 0x24 "LCDC_HEOVADDR,High End Overlay Layer V Address Register"
|
|
line.long 0x28 "LCDC_HEOVCTRL,High End Overlay Layer V Control Register"
|
|
bitfld.long 0x28 5. " VDONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 4. " VADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 3. " VDSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " VDMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0. " VDFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x2C "LCDC_HEOVNEXT,High End Overlay Layer V Next Register"
|
|
line.long 0x30 "LCDC_HEOCFG0,High End Overlay Layer Configuration 0 Register"
|
|
bitfld.long 0x30 13. " LOCKDIS ,Hardware Rotation Lock Disable" "No,Yes"
|
|
bitfld.long 0x30 12. " ROTDIS ,Hardware Rotation Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x30 8. " DLBO ,Defined Length Burst Only For Channel Bus Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x30 6.--7. " BLENUV ,Length for U-V Channel" "AHB_SINGLE,AHB_INCR4,AHB_INCR8,AHB_INCR16"
|
|
textline " "
|
|
bitfld.long 0x30 4.--5. " BLEN ,AHB Burst Length" "AHB_SINGLE,AHB_INCR4,AHB_INCR8,AHB_INCR16"
|
|
line.long 0x34 "LCDC_HEOCFG1,High End Overlay Layer Configuration 1 Register"
|
|
bitfld.long 0x34 17. " YUV422SWP ,YUV 4:2:2 SWAP" "Not swapped,Swapped"
|
|
bitfld.long 0x34 16. " YUV422ROT ,YUV 4:2:2 Rotation" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " YUVMODE ,YUV input mode selection" "32BPP_AYCBCR,16BPP_YCBCR_MODE0,16BPP_YCBCR_MODE1,16BPP_YCBCR_MODE2,16BPP_YCBCR_MODE3,16BPP_YCBCR_SEMIPLANAR,16BPP_YCBCR_PLANAR,12BPP_YCBCR_SEMIPLANAR,12BPP_YCBCR_PLANAR,?..."
|
|
bitfld.long 0x34 8.--9. " CLUTMODE ,Color Lookup table input mode selection" "1BPP,2BPP,4BPP,8BPP"
|
|
textline " "
|
|
bitfld.long 0x34 4.--7. " RGBMODE ,RGB input mode selection" "12 bpp RGB 444,16 bpp ARGB 4444,16 bpp RGBA 4444,16 bpp RGB 565,16 bpp TRGB 1555,18 bpp RGB 666,18 bpp RGB 666 PACKED,19 bpp TRGB 1666,19 bpp TRGB 1666 PACKED,24 bpp RGB 888,24 bpp RGB 888 PACKED,25 bpp TRGB 1888,32 bpp ARGB 8888,32 bpp RGBA 8888,?..."
|
|
bitfld.long 0x34 1. " YUVEN ,YUV Color Space Enable" "RGB,YUV"
|
|
textline " "
|
|
bitfld.long 0x34 0. " CLUTEN ,Color Lookup Table Enable" "RGB mode,Color Lookup table"
|
|
line.long 0x38 "LCDC_HEOCFG2,High End Overlay Layer Configuration 2 Register"
|
|
hexmask.long.word 0x38 16.--26. 1. " YPOS ,Vertical Window Position"
|
|
hexmask.long.word 0x38 0.--10. 1. " XPOS ,Horizontal Window Position"
|
|
line.long 0x3C "LCDC_HEOCFG3,High End Overlay Layer Configuration 3 Register"
|
|
hexmask.long.word 0x3C 16.--26. 1. " YSIZE ,Vertical Window Size"
|
|
hexmask.long.word 0x3C 0.--10. 1. " XSIZE ,Horizontal Window Size"
|
|
line.long 0x40 "LCDC_HEOCFG4,High End Overlay Layer Configuration 4 Register"
|
|
hexmask.long.word 0x40 16.--26. 1. " YMEM_SIZE ,Horizontal image Size sin Memory"
|
|
hexmask.long.word 0x40 0.--10. 1. " XMEM_SIZE ,Vertical image Size in Memory"
|
|
line.long 0x44 "LCDC_HEOCFG5,High End Overlay Layer Configuration 5 Register"
|
|
line.long 0x48 "LCDC_HEOCFG6,High End Overlay Layer Configuration 6 Register"
|
|
line.long 0x4C "LCDC_HEOCFG7,High End Overlay Layer Configuration 7 Register"
|
|
line.long 0x50 "LCDC_HEOCFG8,High End Overlay Layer Configuration 8 Register"
|
|
line.long 0x54 "LCDC_HEOCFG9,High End Overlay Layer Configuration 9 Register"
|
|
hexmask.long.byte 0x54 16.--23. 1. " RDEF ,Red Default"
|
|
textline " "
|
|
hexmask.long.byte 0x54 8.--15. 1. " GDEF ,Green Default"
|
|
textline " "
|
|
hexmask.long.byte 0x54 0.--7. 1. " BDEF ,Blue Default"
|
|
line.long 0x58 "LCDC_HEOCFG10,High End Overlay Layer Configuration 10 Register"
|
|
hexmask.long.byte 0x58 16.--23. 1. " RKEY ,Red Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x58 8.--15. 1. " GKEY ,Green Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x58 0.--7. 1. " BKEY ,Blue Color Component Chroma Key"
|
|
line.long 0x5C "LCDC_HEOCFG11,High End Overlay Layer Configuration 11 Register"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " RMASK ,Red Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 8.--15. 1. " GMASK ,Green Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BMASK ,Blue Color Component Chroma Key Mask"
|
|
line.long 0x60 "LCDC_HEOCFG12,High End Overlay Layer Configuration 12 Register"
|
|
hexmask.long.byte 0x60 16.--23. 1. " GA ,Blender Global Alpha"
|
|
textline " "
|
|
bitfld.long 0x60 12. " VIDPRI ,Video Priority" "Below Overlay 1,Above Overlay 1"
|
|
bitfld.long 0x60 10. " DSTKEY ,Destination Chroma Keying" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 9. " REP ,Use Replication logic to expand RGB color to 24 bits" "Not used,Used"
|
|
bitfld.long 0x60 8. " DMA ,Blender DMA Layer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 7. " OVR ,Blender Overlay Layer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 6. " LAEN ,Blender Local Alpha Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 5. " GAEN ,Blender Global Alpha Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 4. " REVALPHA ,Blender Reverse Alpha" "Not reversed,Reversed"
|
|
textline " "
|
|
bitfld.long 0x60 3. " ITER ,Blender Use Iterated Color" "Not used,Used"
|
|
bitfld.long 0x60 2. " ITER2BL ,Blender Iterated Color Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 1. " INV ,Blender Inverted Blender Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 0. " CRKEY ,Blender Chroma Key Enable" "Disabled,Enabled"
|
|
line.long 0x64 "LCDC_HEOCFG13,High End Overlay Layer Configuration 13 Register"
|
|
bitfld.long 0x64 31. " SCALEN ,Hardware Scaler Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x64 16.--28. 1. " YFACTOR ,Vertical Scaling Factor"
|
|
hexmask.long.word 0x64 0.--12. 1. " XFACTOR ,Horizontal Scaling Factor"
|
|
line.long 0x68 "LCDC_HEOCFG14,High End Overlay Layer Configuration 14 Register"
|
|
bitfld.long 0x68 30. " CSCYOFF ,Color Space Conversion Offset" "0,16"
|
|
hexmask.long.word 0x68 20.--29. 1. " CSCRV ,Color Space Conversion V coefficient for Red Component 1:2:7 format"
|
|
textline " "
|
|
hexmask.long.word 0x68 10.--19. 1. " CSCRU ,Color Space Conversion U coefficient for Red Component 1:2:7 format"
|
|
hexmask.long.word 0x68 0.--9. 1. " CSCRY ,Color Space Conversion Y coefficient for Red Component 1:2:7 format"
|
|
line.long 0x6C "LCDC_HEOCFG15,High End Overlay Layer Configuration 15 Register"
|
|
bitfld.long 0x6c 30. " CSCUOFF ,Color Space Conversion Offset" "0,128"
|
|
hexmask.long.word 0x6c 20.--29. 1. " CSCGV ,Color Space Conversion V coefficient for Green Component 1:2:7 format"
|
|
textline " "
|
|
hexmask.long.word 0x6c 10.--19. 1. " CSCGU ,Color Space Conversion U coefficient for Green Component 1:2:7 format"
|
|
hexmask.long.word 0x6c 0.--9. 1. " CSCGY ,Color Space Conversion Y coefficient for Green Component 1:2:7 format"
|
|
line.long 0x70 "LCDC_HEOCFG16,High End Overlay Layer Configuration 16 Register"
|
|
bitfld.long 0x70 30. " CSCVOFF ,Color Space Conversion Offset" "0,128"
|
|
hexmask.long.word 0x70 20.--29. 1. " CSCBV ,Color Space Conversion V coefficient for Blue Component 1:2:7 format"
|
|
textline " "
|
|
hexmask.long.word 0x70 10.--19. 1. " CSCBU ,Color Space Conversion U coefficient for Blue Component 1:2:7 format"
|
|
hexmask.long.word 0x70 0.--9. 1. " CSCBY ,Color Space Conversion Y coefficient for Blue Component 1:2:7 format"
|
|
wgroup.long 0x340++0x07
|
|
line.long 0x00 "LCDC_HCRCHER,Hardware Cursor Layer Channel Enable Register"
|
|
bitfld.long 0x00 2. " A2QEN ,Add Head Pointer Enable Register" "No effect,Add"
|
|
bitfld.long 0x00 1. " UPDATEEN ,Update Overlay Attributes Enable Register" "No effect,Update"
|
|
line.long 0x04 "LCDC_HCRCHDR,Hardware Cursor Layer Channel Disable Register"
|
|
bitfld.long 0x04 8. " CHRST ,Channel Reset Register" "No effect,Reset"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "LCDC_HCRCHSR,Hardware Cursor Layer Channel Status Register"
|
|
bitfld.long 0x00 2. " A2QSR ,Add to Queue Pending Register" "Not added,Added"
|
|
bitfld.long 0x00 1. " UPDATESR ,Update Overlay Attributes In Progress" "No effect,In progress"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHSR_set/clr ,Channel Status Register" "Enabled,Disabled"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "LCDC_HCRIMR,Hardware Cursor Layer Interrupt Mask Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVR_set/clr ,Overflow Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " DONE_set/clr ,End of List Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ADD_set/clr ,Head Descriptor Loaded Interrupt Mask Register" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " DSCR_set/clr ,Descriptor Loaded Interrupt Mask Register" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DMA_set/clr ,End of DMA Transfer Interrupt Mask Register" "Enabled,Disabled"
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "LCDC_HCRISR,Hardware Cursor Layer Interrupt Status Register"
|
|
in
|
|
group.long 0x35C++0x23
|
|
line.long 0x00 "LCDC_HEOHEAD,High End Overlay Layer Head Register"
|
|
hexmask.long 0x00 2.--31. 1. " HEAD ,DMA Head Pointer"
|
|
line.long 0x04 "LCDC_HCRADDR,Hardware Cursor Layer Address Register"
|
|
line.long 0x08 "LCDC_HCRCTRL,Hardware Cursor Layer Control Register"
|
|
bitfld.long 0x08 5. " DONEIEN ,End of List Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ADDIEN ,Add Head Descriptor to Queue Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSCRIEN ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAIEN ,End of DMA Transfer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LFETCH ,Lookup Table Fetch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DFETCH ,Transfer Descriptor Fetch Enable" "Disabled,Enabled"
|
|
line.long 0x0C "LCDC_HCRNEXT,Hardware Cursor Layer Next Register"
|
|
line.long 0x10 "LCDC_HCRCFG0,Hardware Cursor Layer Configuration 0 Register"
|
|
bitfld.long 0x10 8. " DLBO ,Defined Length Burst Only for Channel Bus Transaction" "Undefinded,Definded"
|
|
bitfld.long 0x10 4.--5. " BLEN ,AHB Burst Length" "AHB_SINGLE,AHB_INCR4,AHB_INCR8,AHB_INCR16"
|
|
line.long 0x14 "LCDC_HCRCFG1,Hardware Cursor Layer Configuration 1 Register"
|
|
bitfld.long 0x14 8.--9. " CLUTMODE ,Color Lookup table input mode selection" "1BPP,2BPP,4BPP,8BPP"
|
|
bitfld.long 0x14 4.--7. " RGBMODE ,RGB input mode selection" "12 bpp RGB 444,16 bpp ARGB 4444,16 bpp RGBA 4444,16 bpp RGB 565,16 bpp TRGB 1555,18 bpp RGB 666,18 bpp RGB 666 PACKED,19 bpp TRGB 1666,19 bpp TRGB 1666 PACKED,24 bpp RGB 888,24 bpp RGB 888 PACKED,25 bpp TRGB 1888,32 bpp ARGB 8888,32 bpp RGBA 8888,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0. " CLUTEN ,Color Lookup Table Enable" "RGB mode,Color Lookup"
|
|
line.long 0x18 "LCDC_HCRCFG2,Hardware Cursor Layer Configuration 2 Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " YPOS ,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. " XPOS ,Horizontal Window Position"
|
|
line.long 0x1C "LCDC_HCRCFG3,Hardware Cursor Layer Configuration 3 Register"
|
|
hexmask.long.byte 0x1C 16.--22. 1. " YSIZE ,Vertical Window Size"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " XSIZE ,Horizontal Window Size"
|
|
line.long 0x20 "LCDC_HCRCFG4,Hardware Cursor Layer Configuration 4 Register"
|
|
group.long 0x384++0x0F
|
|
line.long 0x00 "LCDC_HCRCFG6,Hardware Cursor Layer Configuration 6 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RDEF ,Red Default"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GDEF ,Green Default"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BDEF ,Blue Default"
|
|
line.long 0x04 "LCDC_HCRCFG7,Hardware Cursor Layer Configuration 7 Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RKEY ,Red Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " GKEY ,Green Color Component Chroma Key"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " BKEY ,Blue Color Component Chroma Key"
|
|
line.long 0x08 "LCDC_HCRCFG8,Hardware Cursor Layer Configuration 8 Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RMASK ,Red Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " GMASK ,Green Color Component Chroma Key Mask"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " BMASK ,Blue Color Component Chroma Key Mask"
|
|
line.long 0x0C "LCDC_HCRCFG9,Hardware Cursor Layer Configuration 9 Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. " GA ,Blender Global Alpha"
|
|
bitfld.long 0x0C 10. " DSTKEY ,Destination Chroma Keying" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " REP ,Use Replication logic to expand RGB color to 24 bits" "Not used,Used"
|
|
bitfld.long 0x0C 8. " DMA ,Blender DMA Layer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " OVR ,Blender Overlay Layer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " LAEN ,Blender Local Alpha Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " GAEN ,Blender Global Alpha Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " REVALPHA ,Blender Reverse Alpha" "Not reversed,Reversed"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ITER ,Blender Use Iterated Color" "Not used,Used"
|
|
bitfld.long 0x0C 2. " ITER2BL ,Blender Iterated Color Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INV ,Blender Inverted Blender Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " CRKEY ,Blender Chroma Key Enable" "Disabled,Enabled"
|
|
width 17.
|
|
tree "Base CLUT Registers"
|
|
group.long 0x400++0x3ff
|
|
line.long 0x0 "LCDC_BASECLUT0,Base CLUT Register 0 Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4 "LCDC_BASECLUT1,Base CLUT Register 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8 "LCDC_BASECLUT2,Base CLUT Register 2 Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC "LCDC_BASECLUT3,Base CLUT Register 3 Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10 "LCDC_BASECLUT4,Base CLUT Register 4 Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14 "LCDC_BASECLUT5,Base CLUT Register 5 Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18 "LCDC_BASECLUT6,Base CLUT Register 6 Register"
|
|
hexmask.long.byte 0x18 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C "LCDC_BASECLUT7,Base CLUT Register 7 Register"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20 "LCDC_BASECLUT8,Base CLUT Register 8 Register"
|
|
hexmask.long.byte 0x20 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24 "LCDC_BASECLUT9,Base CLUT Register 9 Register"
|
|
hexmask.long.byte 0x24 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28 "LCDC_BASECLUT10,Base CLUT Register 10 Register"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C "LCDC_BASECLUT11,Base CLUT Register 11 Register"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30 "LCDC_BASECLUT12,Base CLUT Register 12 Register"
|
|
hexmask.long.byte 0x30 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34 "LCDC_BASECLUT13,Base CLUT Register 13 Register"
|
|
hexmask.long.byte 0x34 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38 "LCDC_BASECLUT14,Base CLUT Register 14 Register"
|
|
hexmask.long.byte 0x38 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C "LCDC_BASECLUT15,Base CLUT Register 15 Register"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x40 "LCDC_BASECLUT16,Base CLUT Register 16 Register"
|
|
hexmask.long.byte 0x40 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x40 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x40 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x44 "LCDC_BASECLUT17,Base CLUT Register 17 Register"
|
|
hexmask.long.byte 0x44 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x44 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x44 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x48 "LCDC_BASECLUT18,Base CLUT Register 18 Register"
|
|
hexmask.long.byte 0x48 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x48 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x48 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4C "LCDC_BASECLUT19,Base CLUT Register 19 Register"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x50 "LCDC_BASECLUT20,Base CLUT Register 20 Register"
|
|
hexmask.long.byte 0x50 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x50 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x50 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x54 "LCDC_BASECLUT21,Base CLUT Register 21 Register"
|
|
hexmask.long.byte 0x54 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x54 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x54 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x58 "LCDC_BASECLUT22,Base CLUT Register 22 Register"
|
|
hexmask.long.byte 0x58 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x58 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x58 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x5C "LCDC_BASECLUT23,Base CLUT Register 23 Register"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x60 "LCDC_BASECLUT24,Base CLUT Register 24 Register"
|
|
hexmask.long.byte 0x60 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x60 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x60 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x64 "LCDC_BASECLUT25,Base CLUT Register 25 Register"
|
|
hexmask.long.byte 0x64 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x64 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x64 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x68 "LCDC_BASECLUT26,Base CLUT Register 26 Register"
|
|
hexmask.long.byte 0x68 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x68 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x68 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x6C "LCDC_BASECLUT27,Base CLUT Register 27 Register"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x70 "LCDC_BASECLUT28,Base CLUT Register 28 Register"
|
|
hexmask.long.byte 0x70 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x70 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x70 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x74 "LCDC_BASECLUT29,Base CLUT Register 29 Register"
|
|
hexmask.long.byte 0x74 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x74 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x74 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x78 "LCDC_BASECLUT30,Base CLUT Register 30 Register"
|
|
hexmask.long.byte 0x78 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x78 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x78 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x7C "LCDC_BASECLUT31,Base CLUT Register 31 Register"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x80 "LCDC_BASECLUT32,Base CLUT Register 32 Register"
|
|
hexmask.long.byte 0x80 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x80 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x80 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x84 "LCDC_BASECLUT33,Base CLUT Register 33 Register"
|
|
hexmask.long.byte 0x84 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x84 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x84 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x88 "LCDC_BASECLUT34,Base CLUT Register 34 Register"
|
|
hexmask.long.byte 0x88 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x88 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x88 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8C "LCDC_BASECLUT35,Base CLUT Register 35 Register"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x90 "LCDC_BASECLUT36,Base CLUT Register 36 Register"
|
|
hexmask.long.byte 0x90 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x90 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x90 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x94 "LCDC_BASECLUT37,Base CLUT Register 37 Register"
|
|
hexmask.long.byte 0x94 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x94 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x94 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x98 "LCDC_BASECLUT38,Base CLUT Register 38 Register"
|
|
hexmask.long.byte 0x98 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x98 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x98 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x9C "LCDC_BASECLUT39,Base CLUT Register 39 Register"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA0 "LCDC_BASECLUT40,Base CLUT Register 40 Register"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA4 "LCDC_BASECLUT41,Base CLUT Register 41 Register"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA8 "LCDC_BASECLUT42,Base CLUT Register 42 Register"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xAC "LCDC_BASECLUT43,Base CLUT Register 43 Register"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB0 "LCDC_BASECLUT44,Base CLUT Register 44 Register"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB4 "LCDC_BASECLUT45,Base CLUT Register 45 Register"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB8 "LCDC_BASECLUT46,Base CLUT Register 46 Register"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xBC "LCDC_BASECLUT47,Base CLUT Register 47 Register"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC0 "LCDC_BASECLUT48,Base CLUT Register 48 Register"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC4 "LCDC_BASECLUT49,Base CLUT Register 49 Register"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC8 "LCDC_BASECLUT50,Base CLUT Register 50 Register"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xCC "LCDC_BASECLUT51,Base CLUT Register 51 Register"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD0 "LCDC_BASECLUT52,Base CLUT Register 52 Register"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD4 "LCDC_BASECLUT53,Base CLUT Register 53 Register"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD8 "LCDC_BASECLUT54,Base CLUT Register 54 Register"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xDC "LCDC_BASECLUT55,Base CLUT Register 55 Register"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE0 "LCDC_BASECLUT56,Base CLUT Register 56 Register"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE4 "LCDC_BASECLUT57,Base CLUT Register 57 Register"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE8 "LCDC_BASECLUT58,Base CLUT Register 58 Register"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xEC "LCDC_BASECLUT59,Base CLUT Register 59 Register"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF0 "LCDC_BASECLUT60,Base CLUT Register 60 Register"
|
|
hexmask.long.byte 0xF0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF4 "LCDC_BASECLUT61,Base CLUT Register 61 Register"
|
|
hexmask.long.byte 0xF4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF8 "LCDC_BASECLUT62,Base CLUT Register 62 Register"
|
|
hexmask.long.byte 0xF8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xFC "LCDC_BASECLUT63,Base CLUT Register 63 Register"
|
|
hexmask.long.byte 0xFC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xFC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x100 "LCDC_BASECLUT64,Base CLUT Register 64 Register"
|
|
hexmask.long.byte 0x100 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x100 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x100 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x104 "LCDC_BASECLUT65,Base CLUT Register 65 Register"
|
|
hexmask.long.byte 0x104 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x104 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x104 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x108 "LCDC_BASECLUT66,Base CLUT Register 66 Register"
|
|
hexmask.long.byte 0x108 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x108 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x108 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10C "LCDC_BASECLUT67,Base CLUT Register 67 Register"
|
|
hexmask.long.byte 0x10C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x110 "LCDC_BASECLUT68,Base CLUT Register 68 Register"
|
|
hexmask.long.byte 0x110 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x110 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x110 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x114 "LCDC_BASECLUT69,Base CLUT Register 69 Register"
|
|
hexmask.long.byte 0x114 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x114 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x114 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x118 "LCDC_BASECLUT70,Base CLUT Register 70 Register"
|
|
hexmask.long.byte 0x118 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x118 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x118 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x11C "LCDC_BASECLUT71,Base CLUT Register 71 Register"
|
|
hexmask.long.byte 0x11C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x11C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x11C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x120 "LCDC_BASECLUT72,Base CLUT Register 72 Register"
|
|
hexmask.long.byte 0x120 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x120 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x120 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x124 "LCDC_BASECLUT73,Base CLUT Register 73 Register"
|
|
hexmask.long.byte 0x124 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x124 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x124 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x128 "LCDC_BASECLUT74,Base CLUT Register 74 Register"
|
|
hexmask.long.byte 0x128 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x128 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x128 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x12C "LCDC_BASECLUT75,Base CLUT Register 75 Register"
|
|
hexmask.long.byte 0x12C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x12C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x12C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x130 "LCDC_BASECLUT76,Base CLUT Register 76 Register"
|
|
hexmask.long.byte 0x130 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x130 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x130 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x134 "LCDC_BASECLUT77,Base CLUT Register 77 Register"
|
|
hexmask.long.byte 0x134 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x134 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x134 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x138 "LCDC_BASECLUT78,Base CLUT Register 78 Register"
|
|
hexmask.long.byte 0x138 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x138 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x138 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x13C "LCDC_BASECLUT79,Base CLUT Register 79 Register"
|
|
hexmask.long.byte 0x13C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x13C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x13C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x140 "LCDC_BASECLUT80,Base CLUT Register 80 Register"
|
|
hexmask.long.byte 0x140 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x140 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x140 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x144 "LCDC_BASECLUT81,Base CLUT Register 81 Register"
|
|
hexmask.long.byte 0x144 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x144 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x144 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x148 "LCDC_BASECLUT82,Base CLUT Register 82 Register"
|
|
hexmask.long.byte 0x148 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x148 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x148 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14C "LCDC_BASECLUT83,Base CLUT Register 83 Register"
|
|
hexmask.long.byte 0x14C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x150 "LCDC_BASECLUT84,Base CLUT Register 84 Register"
|
|
hexmask.long.byte 0x150 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x150 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x150 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x154 "LCDC_BASECLUT85,Base CLUT Register 85 Register"
|
|
hexmask.long.byte 0x154 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x154 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x154 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x158 "LCDC_BASECLUT86,Base CLUT Register 86 Register"
|
|
hexmask.long.byte 0x158 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x158 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x158 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x15C "LCDC_BASECLUT87,Base CLUT Register 87 Register"
|
|
hexmask.long.byte 0x15C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x15C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x15C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x160 "LCDC_BASECLUT88,Base CLUT Register 88 Register"
|
|
hexmask.long.byte 0x160 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x160 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x160 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x164 "LCDC_BASECLUT89,Base CLUT Register 89 Register"
|
|
hexmask.long.byte 0x164 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x164 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x164 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x168 "LCDC_BASECLUT90,Base CLUT Register 90 Register"
|
|
hexmask.long.byte 0x168 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x168 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x168 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x16C "LCDC_BASECLUT91,Base CLUT Register 91 Register"
|
|
hexmask.long.byte 0x16C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x16C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x16C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x170 "LCDC_BASECLUT92,Base CLUT Register 92 Register"
|
|
hexmask.long.byte 0x170 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x170 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x170 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x174 "LCDC_BASECLUT93,Base CLUT Register 93 Register"
|
|
hexmask.long.byte 0x174 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x174 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x174 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x178 "LCDC_BASECLUT94,Base CLUT Register 94 Register"
|
|
hexmask.long.byte 0x178 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x178 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x178 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x17C "LCDC_BASECLUT95,Base CLUT Register 95 Register"
|
|
hexmask.long.byte 0x17C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x17C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x17C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x180 "LCDC_BASECLUT96,Base CLUT Register 96 Register"
|
|
hexmask.long.byte 0x180 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x180 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x180 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x184 "LCDC_BASECLUT97,Base CLUT Register 97 Register"
|
|
hexmask.long.byte 0x184 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x184 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x184 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x188 "LCDC_BASECLUT98,Base CLUT Register 98 Register"
|
|
hexmask.long.byte 0x188 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x188 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x188 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18C "LCDC_BASECLUT99,Base CLUT Register 99 Register"
|
|
hexmask.long.byte 0x18C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x190 "LCDC_BASECLUT100,Base CLUT Register 100 Register"
|
|
hexmask.long.byte 0x190 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x190 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x190 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x194 "LCDC_BASECLUT101,Base CLUT Register 101 Register"
|
|
hexmask.long.byte 0x194 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x194 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x194 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x198 "LCDC_BASECLUT102,Base CLUT Register 102 Register"
|
|
hexmask.long.byte 0x198 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x198 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x198 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x19C "LCDC_BASECLUT103,Base CLUT Register 103 Register"
|
|
hexmask.long.byte 0x19C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x19C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x19C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A0 "LCDC_BASECLUT104,Base CLUT Register 104 Register"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A4 "LCDC_BASECLUT105,Base CLUT Register 105 Register"
|
|
hexmask.long.byte 0x1A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A8 "LCDC_BASECLUT106,Base CLUT Register 106 Register"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1AC "LCDC_BASECLUT107,Base CLUT Register 107 Register"
|
|
hexmask.long.byte 0x1AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B0 "LCDC_BASECLUT108,Base CLUT Register 108 Register"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B4 "LCDC_BASECLUT109,Base CLUT Register 109 Register"
|
|
hexmask.long.byte 0x1B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B8 "LCDC_BASECLUT110,Base CLUT Register 110 Register"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1BC "LCDC_BASECLUT111,Base CLUT Register 111 Register"
|
|
hexmask.long.byte 0x1BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C0 "LCDC_BASECLUT112,Base CLUT Register 112 Register"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C4 "LCDC_BASECLUT113,Base CLUT Register 113 Register"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C8 "LCDC_BASECLUT114,Base CLUT Register 114 Register"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1CC "LCDC_BASECLUT115,Base CLUT Register 115 Register"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D0 "LCDC_BASECLUT116,Base CLUT Register 116 Register"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D4 "LCDC_BASECLUT117,Base CLUT Register 117 Register"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D8 "LCDC_BASECLUT118,Base CLUT Register 118 Register"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1DC "LCDC_BASECLUT119,Base CLUT Register 119 Register"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E0 "LCDC_BASECLUT120,Base CLUT Register 120 Register"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E4 "LCDC_BASECLUT121,Base CLUT Register 121 Register"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E8 "LCDC_BASECLUT122,Base CLUT Register 122 Register"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1EC "LCDC_BASECLUT123,Base CLUT Register 123 Register"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F0 "LCDC_BASECLUT124,Base CLUT Register 124 Register"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F4 "LCDC_BASECLUT125,Base CLUT Register 125 Register"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F8 "LCDC_BASECLUT126,Base CLUT Register 126 Register"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1FC "LCDC_BASECLUT127,Base CLUT Register 127 Register"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x200 "LCDC_BASECLUT128,Base CLUT Register 128 Register"
|
|
hexmask.long.byte 0x200 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x200 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x200 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x204 "LCDC_BASECLUT129,Base CLUT Register 129 Register"
|
|
hexmask.long.byte 0x204 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x204 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x204 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x208 "LCDC_BASECLUT130,Base CLUT Register 130 Register"
|
|
hexmask.long.byte 0x208 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x208 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x208 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20C "LCDC_BASECLUT131,Base CLUT Register 131 Register"
|
|
hexmask.long.byte 0x20C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x210 "LCDC_BASECLUT132,Base CLUT Register 132 Register"
|
|
hexmask.long.byte 0x210 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x210 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x210 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x214 "LCDC_BASECLUT133,Base CLUT Register 133 Register"
|
|
hexmask.long.byte 0x214 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x214 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x214 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x218 "LCDC_BASECLUT134,Base CLUT Register 134 Register"
|
|
hexmask.long.byte 0x218 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x218 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x218 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x21C "LCDC_BASECLUT135,Base CLUT Register 135 Register"
|
|
hexmask.long.byte 0x21C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x21C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x21C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x220 "LCDC_BASECLUT136,Base CLUT Register 136 Register"
|
|
hexmask.long.byte 0x220 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x220 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x220 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x224 "LCDC_BASECLUT137,Base CLUT Register 137 Register"
|
|
hexmask.long.byte 0x224 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x224 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x224 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x228 "LCDC_BASECLUT138,Base CLUT Register 138 Register"
|
|
hexmask.long.byte 0x228 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x228 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x228 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x22C "LCDC_BASECLUT139,Base CLUT Register 139 Register"
|
|
hexmask.long.byte 0x22C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x22C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x22C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x230 "LCDC_BASECLUT140,Base CLUT Register 140 Register"
|
|
hexmask.long.byte 0x230 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x230 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x230 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x234 "LCDC_BASECLUT141,Base CLUT Register 141 Register"
|
|
hexmask.long.byte 0x234 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x234 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x234 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x238 "LCDC_BASECLUT142,Base CLUT Register 142 Register"
|
|
hexmask.long.byte 0x238 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x238 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x238 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x23C "LCDC_BASECLUT143,Base CLUT Register 143 Register"
|
|
hexmask.long.byte 0x23C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x23C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x23C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x240 "LCDC_BASECLUT144,Base CLUT Register 144 Register"
|
|
hexmask.long.byte 0x240 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x240 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x240 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x244 "LCDC_BASECLUT145,Base CLUT Register 145 Register"
|
|
hexmask.long.byte 0x244 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x244 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x244 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x248 "LCDC_BASECLUT146,Base CLUT Register 146 Register"
|
|
hexmask.long.byte 0x248 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x248 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x248 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24C "LCDC_BASECLUT147,Base CLUT Register 147 Register"
|
|
hexmask.long.byte 0x24C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x250 "LCDC_BASECLUT148,Base CLUT Register 148 Register"
|
|
hexmask.long.byte 0x250 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x250 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x250 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x254 "LCDC_BASECLUT149,Base CLUT Register 149 Register"
|
|
hexmask.long.byte 0x254 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x254 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x254 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x258 "LCDC_BASECLUT150,Base CLUT Register 150 Register"
|
|
hexmask.long.byte 0x258 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x258 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x258 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x25C "LCDC_BASECLUT151,Base CLUT Register 151 Register"
|
|
hexmask.long.byte 0x25C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x25C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x25C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x260 "LCDC_BASECLUT152,Base CLUT Register 152 Register"
|
|
hexmask.long.byte 0x260 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x260 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x260 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x264 "LCDC_BASECLUT153,Base CLUT Register 153 Register"
|
|
hexmask.long.byte 0x264 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x264 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x264 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x268 "LCDC_BASECLUT154,Base CLUT Register 154 Register"
|
|
hexmask.long.byte 0x268 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x268 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x268 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x26C "LCDC_BASECLUT155,Base CLUT Register 155 Register"
|
|
hexmask.long.byte 0x26C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x26C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x26C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x270 "LCDC_BASECLUT156,Base CLUT Register 156 Register"
|
|
hexmask.long.byte 0x270 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x270 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x270 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x274 "LCDC_BASECLUT157,Base CLUT Register 157 Register"
|
|
hexmask.long.byte 0x274 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x274 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x274 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x278 "LCDC_BASECLUT158,Base CLUT Register 158 Register"
|
|
hexmask.long.byte 0x278 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x278 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x278 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x27C "LCDC_BASECLUT159,Base CLUT Register 159 Register"
|
|
hexmask.long.byte 0x27C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x27C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x27C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x280 "LCDC_BASECLUT160,Base CLUT Register 160 Register"
|
|
hexmask.long.byte 0x280 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x280 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x280 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x284 "LCDC_BASECLUT161,Base CLUT Register 161 Register"
|
|
hexmask.long.byte 0x284 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x284 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x284 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x288 "LCDC_BASECLUT162,Base CLUT Register 162 Register"
|
|
hexmask.long.byte 0x288 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x288 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x288 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28C "LCDC_BASECLUT163,Base CLUT Register 163 Register"
|
|
hexmask.long.byte 0x28C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x290 "LCDC_BASECLUT164,Base CLUT Register 164 Register"
|
|
hexmask.long.byte 0x290 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x290 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x290 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x294 "LCDC_BASECLUT165,Base CLUT Register 165 Register"
|
|
hexmask.long.byte 0x294 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x294 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x294 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x298 "LCDC_BASECLUT166,Base CLUT Register 166 Register"
|
|
hexmask.long.byte 0x298 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x298 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x298 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x29C "LCDC_BASECLUT167,Base CLUT Register 167 Register"
|
|
hexmask.long.byte 0x29C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x29C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x29C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A0 "LCDC_BASECLUT168,Base CLUT Register 168 Register"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A4 "LCDC_BASECLUT169,Base CLUT Register 169 Register"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A8 "LCDC_BASECLUT170,Base CLUT Register 170 Register"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2AC "LCDC_BASECLUT171,Base CLUT Register 171 Register"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B0 "LCDC_BASECLUT172,Base CLUT Register 172 Register"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B4 "LCDC_BASECLUT173,Base CLUT Register 173 Register"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B8 "LCDC_BASECLUT174,Base CLUT Register 174 Register"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2BC "LCDC_BASECLUT175,Base CLUT Register 175 Register"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C0 "LCDC_BASECLUT176,Base CLUT Register 176 Register"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C4 "LCDC_BASECLUT177,Base CLUT Register 177 Register"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C8 "LCDC_BASECLUT178,Base CLUT Register 178 Register"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2CC "LCDC_BASECLUT179,Base CLUT Register 179 Register"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D0 "LCDC_BASECLUT180,Base CLUT Register 180 Register"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D4 "LCDC_BASECLUT181,Base CLUT Register 181 Register"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D8 "LCDC_BASECLUT182,Base CLUT Register 182 Register"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2DC "LCDC_BASECLUT183,Base CLUT Register 183 Register"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E0 "LCDC_BASECLUT184,Base CLUT Register 184 Register"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E4 "LCDC_BASECLUT185,Base CLUT Register 185 Register"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E8 "LCDC_BASECLUT186,Base CLUT Register 186 Register"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2EC "LCDC_BASECLUT187,Base CLUT Register 187 Register"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F0 "LCDC_BASECLUT188,Base CLUT Register 188 Register"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F4 "LCDC_BASECLUT189,Base CLUT Register 189 Register"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F8 "LCDC_BASECLUT190,Base CLUT Register 190 Register"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2FC "LCDC_BASECLUT191,Base CLUT Register 191 Register"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x300 "LCDC_BASECLUT192,Base CLUT Register 192 Register"
|
|
hexmask.long.byte 0x300 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x300 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x300 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x304 "LCDC_BASECLUT193,Base CLUT Register 193 Register"
|
|
hexmask.long.byte 0x304 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x304 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x304 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x308 "LCDC_BASECLUT194,Base CLUT Register 194 Register"
|
|
hexmask.long.byte 0x308 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x308 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x308 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30C "LCDC_BASECLUT195,Base CLUT Register 195 Register"
|
|
hexmask.long.byte 0x30C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x310 "LCDC_BASECLUT196,Base CLUT Register 196 Register"
|
|
hexmask.long.byte 0x310 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x310 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x310 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x314 "LCDC_BASECLUT197,Base CLUT Register 197 Register"
|
|
hexmask.long.byte 0x314 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x314 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x314 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x318 "LCDC_BASECLUT198,Base CLUT Register 198 Register"
|
|
hexmask.long.byte 0x318 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x318 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x318 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x31C "LCDC_BASECLUT199,Base CLUT Register 199 Register"
|
|
hexmask.long.byte 0x31C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x31C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x31C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x320 "LCDC_BASECLUT200,Base CLUT Register 200 Register"
|
|
hexmask.long.byte 0x320 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x320 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x320 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x324 "LCDC_BASECLUT201,Base CLUT Register 201 Register"
|
|
hexmask.long.byte 0x324 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x324 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x324 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x328 "LCDC_BASECLUT202,Base CLUT Register 202 Register"
|
|
hexmask.long.byte 0x328 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x328 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x328 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x32C "LCDC_BASECLUT203,Base CLUT Register 203 Register"
|
|
hexmask.long.byte 0x32C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x32C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x32C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x330 "LCDC_BASECLUT204,Base CLUT Register 204 Register"
|
|
hexmask.long.byte 0x330 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x330 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x330 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x334 "LCDC_BASECLUT205,Base CLUT Register 205 Register"
|
|
hexmask.long.byte 0x334 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x334 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x334 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x338 "LCDC_BASECLUT206,Base CLUT Register 206 Register"
|
|
hexmask.long.byte 0x338 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x338 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x338 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x33C "LCDC_BASECLUT207,Base CLUT Register 207 Register"
|
|
hexmask.long.byte 0x33C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x33C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x33C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x340 "LCDC_BASECLUT208,Base CLUT Register 208 Register"
|
|
hexmask.long.byte 0x340 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x340 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x340 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x344 "LCDC_BASECLUT209,Base CLUT Register 209 Register"
|
|
hexmask.long.byte 0x344 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x344 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x344 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x348 "LCDC_BASECLUT210,Base CLUT Register 210 Register"
|
|
hexmask.long.byte 0x348 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x348 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x348 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34C "LCDC_BASECLUT211,Base CLUT Register 211 Register"
|
|
hexmask.long.byte 0x34C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x350 "LCDC_BASECLUT212,Base CLUT Register 212 Register"
|
|
hexmask.long.byte 0x350 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x350 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x350 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x354 "LCDC_BASECLUT213,Base CLUT Register 213 Register"
|
|
hexmask.long.byte 0x354 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x354 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x354 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x358 "LCDC_BASECLUT214,Base CLUT Register 214 Register"
|
|
hexmask.long.byte 0x358 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x358 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x358 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x35C "LCDC_BASECLUT215,Base CLUT Register 215 Register"
|
|
hexmask.long.byte 0x35C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x35C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x35C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x360 "LCDC_BASECLUT216,Base CLUT Register 216 Register"
|
|
hexmask.long.byte 0x360 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x360 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x360 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x364 "LCDC_BASECLUT217,Base CLUT Register 217 Register"
|
|
hexmask.long.byte 0x364 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x364 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x364 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x368 "LCDC_BASECLUT218,Base CLUT Register 218 Register"
|
|
hexmask.long.byte 0x368 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x368 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x368 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x36C "LCDC_BASECLUT219,Base CLUT Register 219 Register"
|
|
hexmask.long.byte 0x36C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x36C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x36C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x370 "LCDC_BASECLUT220,Base CLUT Register 220 Register"
|
|
hexmask.long.byte 0x370 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x370 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x370 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x374 "LCDC_BASECLUT221,Base CLUT Register 221 Register"
|
|
hexmask.long.byte 0x374 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x374 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x374 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x378 "LCDC_BASECLUT222,Base CLUT Register 222 Register"
|
|
hexmask.long.byte 0x378 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x378 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x378 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x37C "LCDC_BASECLUT223,Base CLUT Register 223 Register"
|
|
hexmask.long.byte 0x37C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x37C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x37C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x380 "LCDC_BASECLUT224,Base CLUT Register 224 Register"
|
|
hexmask.long.byte 0x380 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x380 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x380 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x384 "LCDC_BASECLUT225,Base CLUT Register 225 Register"
|
|
hexmask.long.byte 0x384 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x384 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x384 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x388 "LCDC_BASECLUT226,Base CLUT Register 226 Register"
|
|
hexmask.long.byte 0x388 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x388 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x388 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38C "LCDC_BASECLUT227,Base CLUT Register 227 Register"
|
|
hexmask.long.byte 0x38C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x390 "LCDC_BASECLUT228,Base CLUT Register 228 Register"
|
|
hexmask.long.byte 0x390 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x390 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x390 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x394 "LCDC_BASECLUT229,Base CLUT Register 229 Register"
|
|
hexmask.long.byte 0x394 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x394 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x394 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x398 "LCDC_BASECLUT230,Base CLUT Register 230 Register"
|
|
hexmask.long.byte 0x398 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x398 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x398 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x39C "LCDC_BASECLUT231,Base CLUT Register 231 Register"
|
|
hexmask.long.byte 0x39C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x39C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x39C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A0 "LCDC_BASECLUT232,Base CLUT Register 232 Register"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A4 "LCDC_BASECLUT233,Base CLUT Register 233 Register"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A8 "LCDC_BASECLUT234,Base CLUT Register 234 Register"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3AC "LCDC_BASECLUT235,Base CLUT Register 235 Register"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B0 "LCDC_BASECLUT236,Base CLUT Register 236 Register"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B4 "LCDC_BASECLUT237,Base CLUT Register 237 Register"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B8 "LCDC_BASECLUT238,Base CLUT Register 238 Register"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3BC "LCDC_BASECLUT239,Base CLUT Register 239 Register"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C0 "LCDC_BASECLUT240,Base CLUT Register 240 Register"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C4 "LCDC_BASECLUT241,Base CLUT Register 241 Register"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C8 "LCDC_BASECLUT242,Base CLUT Register 242 Register"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3CC "LCDC_BASECLUT243,Base CLUT Register 243 Register"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D0 "LCDC_BASECLUT244,Base CLUT Register 244 Register"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D4 "LCDC_BASECLUT245,Base CLUT Register 245 Register"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D8 "LCDC_BASECLUT246,Base CLUT Register 246 Register"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3DC "LCDC_BASECLUT247,Base CLUT Register 247 Register"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E0 "LCDC_BASECLUT248,Base CLUT Register 248 Register"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E4 "LCDC_BASECLUT249,Base CLUT Register 249 Register"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E8 "LCDC_BASECLUT250,Base CLUT Register 250 Register"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3EC "LCDC_BASECLUT251,Base CLUT Register 251 Register"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F0 "LCDC_BASECLUT252,Base CLUT Register 252 Register"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F4 "LCDC_BASECLUT253,Base CLUT Register 253 Register"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F8 "LCDC_BASECLUT254,Base CLUT Register 254 Register"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3FC "LCDC_BASECLUT255,Base CLUT Register 255 Register"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
tree.end
|
|
tree "Overlay 1 CLUT Registers"
|
|
group.long 0x800++0x3ff
|
|
line.long 0x0 "LCDC_OVR1CLUT0,Overlay 1 CLUT Register 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4 "LCDC_OVR1CLUT1,Overlay 1 CLUT Register 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8 "LCDC_OVR1CLUT2,Overlay 1 CLUT Register 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC "LCDC_OVR1CLUT3,Overlay 1 CLUT Register 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10 "LCDC_OVR1CLUT4,Overlay 1 CLUT Register 4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14 "LCDC_OVR1CLUT5,Overlay 1 CLUT Register 5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18 "LCDC_OVR1CLUT6,Overlay 1 CLUT Register 6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C "LCDC_OVR1CLUT7,Overlay 1 CLUT Register 7 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20 "LCDC_OVR1CLUT8,Overlay 1 CLUT Register 8 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24 "LCDC_OVR1CLUT9,Overlay 1 CLUT Register 9 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28 "LCDC_OVR1CLUT10,Overlay 1 CLUT Register 10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C "LCDC_OVR1CLUT11,Overlay 1 CLUT Register 11 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30 "LCDC_OVR1CLUT12,Overlay 1 CLUT Register 12 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34 "LCDC_OVR1CLUT13,Overlay 1 CLUT Register 13 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38 "LCDC_OVR1CLUT14,Overlay 1 CLUT Register 14 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C "LCDC_OVR1CLUT15,Overlay 1 CLUT Register 15 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x40 "LCDC_OVR1CLUT16,Overlay 1 CLUT Register 16 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x40 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x40 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x40 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x44 "LCDC_OVR1CLUT17,Overlay 1 CLUT Register 17 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x44 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x44 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x44 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x48 "LCDC_OVR1CLUT18,Overlay 1 CLUT Register 18 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x48 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x48 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x48 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4C "LCDC_OVR1CLUT19,Overlay 1 CLUT Register 19 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x50 "LCDC_OVR1CLUT20,Overlay 1 CLUT Register 20 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x50 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x50 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x50 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x54 "LCDC_OVR1CLUT21,Overlay 1 CLUT Register 21 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x54 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x54 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x54 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x58 "LCDC_OVR1CLUT22,Overlay 1 CLUT Register 22 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x58 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x58 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x58 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x5C "LCDC_OVR1CLUT23,Overlay 1 CLUT Register 23 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x60 "LCDC_OVR1CLUT24,Overlay 1 CLUT Register 24 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x60 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x60 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x60 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x64 "LCDC_OVR1CLUT25,Overlay 1 CLUT Register 25 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x64 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x64 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x64 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x68 "LCDC_OVR1CLUT26,Overlay 1 CLUT Register 26 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x68 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x68 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x68 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x6C "LCDC_OVR1CLUT27,Overlay 1 CLUT Register 27 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x70 "LCDC_OVR1CLUT28,Overlay 1 CLUT Register 28 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x70 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x70 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x70 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x74 "LCDC_OVR1CLUT29,Overlay 1 CLUT Register 29 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x74 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x74 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x74 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x78 "LCDC_OVR1CLUT30,Overlay 1 CLUT Register 30 Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x78 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x78 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x78 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x7C "LCDC_OVR1CLUT31,Overlay 1 CLUT Register 31 Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x80 "LCDC_OVR1CLUT32,Overlay 1 CLUT Register 32 Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x80 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x80 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x80 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x84 "LCDC_OVR1CLUT33,Overlay 1 CLUT Register 33 Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x84 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x84 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x84 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x88 "LCDC_OVR1CLUT34,Overlay 1 CLUT Register 34 Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x88 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x88 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x88 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8C "LCDC_OVR1CLUT35,Overlay 1 CLUT Register 35 Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x90 "LCDC_OVR1CLUT36,Overlay 1 CLUT Register 36 Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x90 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x90 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x90 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x94 "LCDC_OVR1CLUT37,Overlay 1 CLUT Register 37 Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x94 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x94 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x94 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x98 "LCDC_OVR1CLUT38,Overlay 1 CLUT Register 38 Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x98 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x98 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x98 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x9C "LCDC_OVR1CLUT39,Overlay 1 CLUT Register 39 Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA0 "LCDC_OVR1CLUT40,Overlay 1 CLUT Register 40 Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA4 "LCDC_OVR1CLUT41,Overlay 1 CLUT Register 41 Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA8 "LCDC_OVR1CLUT42,Overlay 1 CLUT Register 42 Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xAC "LCDC_OVR1CLUT43,Overlay 1 CLUT Register 43 Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB0 "LCDC_OVR1CLUT44,Overlay 1 CLUT Register 44 Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB4 "LCDC_OVR1CLUT45,Overlay 1 CLUT Register 45 Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB8 "LCDC_OVR1CLUT46,Overlay 1 CLUT Register 46 Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xBC "LCDC_OVR1CLUT47,Overlay 1 CLUT Register 47 Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC0 "LCDC_OVR1CLUT48,Overlay 1 CLUT Register 48 Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC4 "LCDC_OVR1CLUT49,Overlay 1 CLUT Register 49 Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC8 "LCDC_OVR1CLUT50,Overlay 1 CLUT Register 50 Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xCC "LCDC_OVR1CLUT51,Overlay 1 CLUT Register 51 Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD0 "LCDC_OVR1CLUT52,Overlay 1 CLUT Register 52 Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD4 "LCDC_OVR1CLUT53,Overlay 1 CLUT Register 53 Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD8 "LCDC_OVR1CLUT54,Overlay 1 CLUT Register 54 Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xDC "LCDC_OVR1CLUT55,Overlay 1 CLUT Register 55 Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE0 "LCDC_OVR1CLUT56,Overlay 1 CLUT Register 56 Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE4 "LCDC_OVR1CLUT57,Overlay 1 CLUT Register 57 Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE8 "LCDC_OVR1CLUT58,Overlay 1 CLUT Register 58 Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xEC "LCDC_OVR1CLUT59,Overlay 1 CLUT Register 59 Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF0 "LCDC_OVR1CLUT60,Overlay 1 CLUT Register 60 Register"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF4 "LCDC_OVR1CLUT61,Overlay 1 CLUT Register 61 Register"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF8 "LCDC_OVR1CLUT62,Overlay 1 CLUT Register 62 Register"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xFC "LCDC_OVR1CLUT63,Overlay 1 CLUT Register 63 Register"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xFC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xFC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x100 "LCDC_OVR1CLUT64,Overlay 1 CLUT Register 64 Register"
|
|
hexmask.long.byte 0x100 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x100 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x100 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x100 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x104 "LCDC_OVR1CLUT65,Overlay 1 CLUT Register 65 Register"
|
|
hexmask.long.byte 0x104 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x104 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x104 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x104 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x108 "LCDC_OVR1CLUT66,Overlay 1 CLUT Register 66 Register"
|
|
hexmask.long.byte 0x108 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x108 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x108 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x108 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10C "LCDC_OVR1CLUT67,Overlay 1 CLUT Register 67 Register"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x110 "LCDC_OVR1CLUT68,Overlay 1 CLUT Register 68 Register"
|
|
hexmask.long.byte 0x110 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x110 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x110 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x110 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x114 "LCDC_OVR1CLUT69,Overlay 1 CLUT Register 69 Register"
|
|
hexmask.long.byte 0x114 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x114 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x114 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x114 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x118 "LCDC_OVR1CLUT70,Overlay 1 CLUT Register 70 Register"
|
|
hexmask.long.byte 0x118 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x118 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x118 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x118 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x11C "LCDC_OVR1CLUT71,Overlay 1 CLUT Register 71 Register"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x11C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x11C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x11C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x120 "LCDC_OVR1CLUT72,Overlay 1 CLUT Register 72 Register"
|
|
hexmask.long.byte 0x120 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x120 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x120 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x120 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x124 "LCDC_OVR1CLUT73,Overlay 1 CLUT Register 73 Register"
|
|
hexmask.long.byte 0x124 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x124 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x124 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x124 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x128 "LCDC_OVR1CLUT74,Overlay 1 CLUT Register 74 Register"
|
|
hexmask.long.byte 0x128 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x128 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x128 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x128 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x12C "LCDC_OVR1CLUT75,Overlay 1 CLUT Register 75 Register"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x12C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x12C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x12C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x130 "LCDC_OVR1CLUT76,Overlay 1 CLUT Register 76 Register"
|
|
hexmask.long.byte 0x130 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x130 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x130 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x130 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x134 "LCDC_OVR1CLUT77,Overlay 1 CLUT Register 77 Register"
|
|
hexmask.long.byte 0x134 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x134 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x134 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x134 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x138 "LCDC_OVR1CLUT78,Overlay 1 CLUT Register 78 Register"
|
|
hexmask.long.byte 0x138 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x138 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x138 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x138 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x13C "LCDC_OVR1CLUT79,Overlay 1 CLUT Register 79 Register"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x13C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x13C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x13C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x140 "LCDC_OVR1CLUT80,Overlay 1 CLUT Register 80 Register"
|
|
hexmask.long.byte 0x140 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x140 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x140 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x140 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x144 "LCDC_OVR1CLUT81,Overlay 1 CLUT Register 81 Register"
|
|
hexmask.long.byte 0x144 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x144 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x144 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x144 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x148 "LCDC_OVR1CLUT82,Overlay 1 CLUT Register 82 Register"
|
|
hexmask.long.byte 0x148 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x148 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x148 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x148 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14C "LCDC_OVR1CLUT83,Overlay 1 CLUT Register 83 Register"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x150 "LCDC_OVR1CLUT84,Overlay 1 CLUT Register 84 Register"
|
|
hexmask.long.byte 0x150 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x150 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x150 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x150 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x154 "LCDC_OVR1CLUT85,Overlay 1 CLUT Register 85 Register"
|
|
hexmask.long.byte 0x154 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x154 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x154 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x154 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x158 "LCDC_OVR1CLUT86,Overlay 1 CLUT Register 86 Register"
|
|
hexmask.long.byte 0x158 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x158 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x158 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x158 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x15C "LCDC_OVR1CLUT87,Overlay 1 CLUT Register 87 Register"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x15C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x15C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x15C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x160 "LCDC_OVR1CLUT88,Overlay 1 CLUT Register 88 Register"
|
|
hexmask.long.byte 0x160 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x160 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x160 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x160 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x164 "LCDC_OVR1CLUT89,Overlay 1 CLUT Register 89 Register"
|
|
hexmask.long.byte 0x164 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x164 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x164 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x164 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x168 "LCDC_OVR1CLUT90,Overlay 1 CLUT Register 90 Register"
|
|
hexmask.long.byte 0x168 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x168 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x168 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x168 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x16C "LCDC_OVR1CLUT91,Overlay 1 CLUT Register 91 Register"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x16C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x16C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x16C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x170 "LCDC_OVR1CLUT92,Overlay 1 CLUT Register 92 Register"
|
|
hexmask.long.byte 0x170 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x170 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x170 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x170 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x174 "LCDC_OVR1CLUT93,Overlay 1 CLUT Register 93 Register"
|
|
hexmask.long.byte 0x174 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x174 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x174 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x174 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x178 "LCDC_OVR1CLUT94,Overlay 1 CLUT Register 94 Register"
|
|
hexmask.long.byte 0x178 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x178 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x178 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x178 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x17C "LCDC_OVR1CLUT95,Overlay 1 CLUT Register 95 Register"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x17C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x17C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x17C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x180 "LCDC_OVR1CLUT96,Overlay 1 CLUT Register 96 Register"
|
|
hexmask.long.byte 0x180 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x180 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x180 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x180 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x184 "LCDC_OVR1CLUT97,Overlay 1 CLUT Register 97 Register"
|
|
hexmask.long.byte 0x184 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x184 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x184 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x184 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x188 "LCDC_OVR1CLUT98,Overlay 1 CLUT Register 98 Register"
|
|
hexmask.long.byte 0x188 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x188 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x188 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x188 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18C "LCDC_OVR1CLUT99,Overlay 1 CLUT Register 99 Register"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x190 "LCDC_OVR1CLUT100,Overlay 1 CLUT Register 100 Register"
|
|
hexmask.long.byte 0x190 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x190 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x190 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x190 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x194 "LCDC_OVR1CLUT101,Overlay 1 CLUT Register 101 Register"
|
|
hexmask.long.byte 0x194 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x194 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x194 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x194 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x198 "LCDC_OVR1CLUT102,Overlay 1 CLUT Register 102 Register"
|
|
hexmask.long.byte 0x198 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x198 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x198 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x198 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x19C "LCDC_OVR1CLUT103,Overlay 1 CLUT Register 103 Register"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x19C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x19C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x19C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A0 "LCDC_OVR1CLUT104,Overlay 1 CLUT Register 104 Register"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A4 "LCDC_OVR1CLUT105,Overlay 1 CLUT Register 105 Register"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A8 "LCDC_OVR1CLUT106,Overlay 1 CLUT Register 106 Register"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1AC "LCDC_OVR1CLUT107,Overlay 1 CLUT Register 107 Register"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B0 "LCDC_OVR1CLUT108,Overlay 1 CLUT Register 108 Register"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B4 "LCDC_OVR1CLUT109,Overlay 1 CLUT Register 109 Register"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B8 "LCDC_OVR1CLUT110,Overlay 1 CLUT Register 110 Register"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1BC "LCDC_OVR1CLUT111,Overlay 1 CLUT Register 111 Register"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C0 "LCDC_OVR1CLUT112,Overlay 1 CLUT Register 112 Register"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C4 "LCDC_OVR1CLUT113,Overlay 1 CLUT Register 113 Register"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C8 "LCDC_OVR1CLUT114,Overlay 1 CLUT Register 114 Register"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1CC "LCDC_OVR1CLUT115,Overlay 1 CLUT Register 115 Register"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D0 "LCDC_OVR1CLUT116,Overlay 1 CLUT Register 116 Register"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D4 "LCDC_OVR1CLUT117,Overlay 1 CLUT Register 117 Register"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D8 "LCDC_OVR1CLUT118,Overlay 1 CLUT Register 118 Register"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1DC "LCDC_OVR1CLUT119,Overlay 1 CLUT Register 119 Register"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E0 "LCDC_OVR1CLUT120,Overlay 1 CLUT Register 120 Register"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E4 "LCDC_OVR1CLUT121,Overlay 1 CLUT Register 121 Register"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E8 "LCDC_OVR1CLUT122,Overlay 1 CLUT Register 122 Register"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1EC "LCDC_OVR1CLUT123,Overlay 1 CLUT Register 123 Register"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F0 "LCDC_OVR1CLUT124,Overlay 1 CLUT Register 124 Register"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F4 "LCDC_OVR1CLUT125,Overlay 1 CLUT Register 125 Register"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F8 "LCDC_OVR1CLUT126,Overlay 1 CLUT Register 126 Register"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1FC "LCDC_OVR1CLUT127,Overlay 1 CLUT Register 127 Register"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x200 "LCDC_OVR1CLUT128,Overlay 1 CLUT Register 128 Register"
|
|
hexmask.long.byte 0x200 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x200 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x200 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x200 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x204 "LCDC_OVR1CLUT129,Overlay 1 CLUT Register 129 Register"
|
|
hexmask.long.byte 0x204 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x204 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x204 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x204 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x208 "LCDC_OVR1CLUT130,Overlay 1 CLUT Register 130 Register"
|
|
hexmask.long.byte 0x208 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x208 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x208 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x208 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20C "LCDC_OVR1CLUT131,Overlay 1 CLUT Register 131 Register"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x210 "LCDC_OVR1CLUT132,Overlay 1 CLUT Register 132 Register"
|
|
hexmask.long.byte 0x210 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x210 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x210 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x210 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x214 "LCDC_OVR1CLUT133,Overlay 1 CLUT Register 133 Register"
|
|
hexmask.long.byte 0x214 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x214 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x214 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x214 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x218 "LCDC_OVR1CLUT134,Overlay 1 CLUT Register 134 Register"
|
|
hexmask.long.byte 0x218 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x218 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x218 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x218 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x21C "LCDC_OVR1CLUT135,Overlay 1 CLUT Register 135 Register"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x21C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x21C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x21C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x220 "LCDC_OVR1CLUT136,Overlay 1 CLUT Register 136 Register"
|
|
hexmask.long.byte 0x220 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x220 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x220 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x220 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x224 "LCDC_OVR1CLUT137,Overlay 1 CLUT Register 137 Register"
|
|
hexmask.long.byte 0x224 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x224 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x224 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x224 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x228 "LCDC_OVR1CLUT138,Overlay 1 CLUT Register 138 Register"
|
|
hexmask.long.byte 0x228 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x228 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x228 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x228 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x22C "LCDC_OVR1CLUT139,Overlay 1 CLUT Register 139 Register"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x22C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x22C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x22C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x230 "LCDC_OVR1CLUT140,Overlay 1 CLUT Register 140 Register"
|
|
hexmask.long.byte 0x230 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x230 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x230 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x230 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x234 "LCDC_OVR1CLUT141,Overlay 1 CLUT Register 141 Register"
|
|
hexmask.long.byte 0x234 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x234 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x234 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x234 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x238 "LCDC_OVR1CLUT142,Overlay 1 CLUT Register 142 Register"
|
|
hexmask.long.byte 0x238 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x238 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x238 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x238 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x23C "LCDC_OVR1CLUT143,Overlay 1 CLUT Register 143 Register"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x23C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x23C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x23C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x240 "LCDC_OVR1CLUT144,Overlay 1 CLUT Register 144 Register"
|
|
hexmask.long.byte 0x240 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x240 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x240 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x240 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x244 "LCDC_OVR1CLUT145,Overlay 1 CLUT Register 145 Register"
|
|
hexmask.long.byte 0x244 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x244 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x244 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x244 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x248 "LCDC_OVR1CLUT146,Overlay 1 CLUT Register 146 Register"
|
|
hexmask.long.byte 0x248 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x248 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x248 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x248 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24C "LCDC_OVR1CLUT147,Overlay 1 CLUT Register 147 Register"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x250 "LCDC_OVR1CLUT148,Overlay 1 CLUT Register 148 Register"
|
|
hexmask.long.byte 0x250 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x250 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x250 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x250 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x254 "LCDC_OVR1CLUT149,Overlay 1 CLUT Register 149 Register"
|
|
hexmask.long.byte 0x254 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x254 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x254 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x254 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x258 "LCDC_OVR1CLUT150,Overlay 1 CLUT Register 150 Register"
|
|
hexmask.long.byte 0x258 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x258 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x258 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x258 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x25C "LCDC_OVR1CLUT151,Overlay 1 CLUT Register 151 Register"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x25C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x25C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x25C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x260 "LCDC_OVR1CLUT152,Overlay 1 CLUT Register 152 Register"
|
|
hexmask.long.byte 0x260 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x260 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x260 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x260 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x264 "LCDC_OVR1CLUT153,Overlay 1 CLUT Register 153 Register"
|
|
hexmask.long.byte 0x264 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x264 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x264 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x264 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x268 "LCDC_OVR1CLUT154,Overlay 1 CLUT Register 154 Register"
|
|
hexmask.long.byte 0x268 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x268 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x268 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x268 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x26C "LCDC_OVR1CLUT155,Overlay 1 CLUT Register 155 Register"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x26C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x26C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x26C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x270 "LCDC_OVR1CLUT156,Overlay 1 CLUT Register 156 Register"
|
|
hexmask.long.byte 0x270 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x270 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x270 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x270 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x274 "LCDC_OVR1CLUT157,Overlay 1 CLUT Register 157 Register"
|
|
hexmask.long.byte 0x274 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x274 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x274 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x274 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x278 "LCDC_OVR1CLUT158,Overlay 1 CLUT Register 158 Register"
|
|
hexmask.long.byte 0x278 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x278 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x278 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x278 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x27C "LCDC_OVR1CLUT159,Overlay 1 CLUT Register 159 Register"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x27C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x27C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x27C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x280 "LCDC_OVR1CLUT160,Overlay 1 CLUT Register 160 Register"
|
|
hexmask.long.byte 0x280 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x280 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x280 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x280 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x284 "LCDC_OVR1CLUT161,Overlay 1 CLUT Register 161 Register"
|
|
hexmask.long.byte 0x284 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x284 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x284 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x284 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x288 "LCDC_OVR1CLUT162,Overlay 1 CLUT Register 162 Register"
|
|
hexmask.long.byte 0x288 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x288 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x288 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x288 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28C "LCDC_OVR1CLUT163,Overlay 1 CLUT Register 163 Register"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x290 "LCDC_OVR1CLUT164,Overlay 1 CLUT Register 164 Register"
|
|
hexmask.long.byte 0x290 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x290 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x290 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x290 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x294 "LCDC_OVR1CLUT165,Overlay 1 CLUT Register 165 Register"
|
|
hexmask.long.byte 0x294 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x294 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x294 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x294 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x298 "LCDC_OVR1CLUT166,Overlay 1 CLUT Register 166 Register"
|
|
hexmask.long.byte 0x298 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x298 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x298 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x298 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x29C "LCDC_OVR1CLUT167,Overlay 1 CLUT Register 167 Register"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x29C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x29C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x29C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A0 "LCDC_OVR1CLUT168,Overlay 1 CLUT Register 168 Register"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A4 "LCDC_OVR1CLUT169,Overlay 1 CLUT Register 169 Register"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A8 "LCDC_OVR1CLUT170,Overlay 1 CLUT Register 170 Register"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2AC "LCDC_OVR1CLUT171,Overlay 1 CLUT Register 171 Register"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B0 "LCDC_OVR1CLUT172,Overlay 1 CLUT Register 172 Register"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B4 "LCDC_OVR1CLUT173,Overlay 1 CLUT Register 173 Register"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B8 "LCDC_OVR1CLUT174,Overlay 1 CLUT Register 174 Register"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2BC "LCDC_OVR1CLUT175,Overlay 1 CLUT Register 175 Register"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C0 "LCDC_OVR1CLUT176,Overlay 1 CLUT Register 176 Register"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C4 "LCDC_OVR1CLUT177,Overlay 1 CLUT Register 177 Register"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C8 "LCDC_OVR1CLUT178,Overlay 1 CLUT Register 178 Register"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2CC "LCDC_OVR1CLUT179,Overlay 1 CLUT Register 179 Register"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D0 "LCDC_OVR1CLUT180,Overlay 1 CLUT Register 180 Register"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D4 "LCDC_OVR1CLUT181,Overlay 1 CLUT Register 181 Register"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D8 "LCDC_OVR1CLUT182,Overlay 1 CLUT Register 182 Register"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2DC "LCDC_OVR1CLUT183,Overlay 1 CLUT Register 183 Register"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E0 "LCDC_OVR1CLUT184,Overlay 1 CLUT Register 184 Register"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E4 "LCDC_OVR1CLUT185,Overlay 1 CLUT Register 185 Register"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E8 "LCDC_OVR1CLUT186,Overlay 1 CLUT Register 186 Register"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2EC "LCDC_OVR1CLUT187,Overlay 1 CLUT Register 187 Register"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F0 "LCDC_OVR1CLUT188,Overlay 1 CLUT Register 188 Register"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F4 "LCDC_OVR1CLUT189,Overlay 1 CLUT Register 189 Register"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F8 "LCDC_OVR1CLUT190,Overlay 1 CLUT Register 190 Register"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2FC "LCDC_OVR1CLUT191,Overlay 1 CLUT Register 191 Register"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x300 "LCDC_OVR1CLUT192,Overlay 1 CLUT Register 192 Register"
|
|
hexmask.long.byte 0x300 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x300 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x300 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x300 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x304 "LCDC_OVR1CLUT193,Overlay 1 CLUT Register 193 Register"
|
|
hexmask.long.byte 0x304 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x304 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x304 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x304 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x308 "LCDC_OVR1CLUT194,Overlay 1 CLUT Register 194 Register"
|
|
hexmask.long.byte 0x308 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x308 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x308 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x308 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30C "LCDC_OVR1CLUT195,Overlay 1 CLUT Register 195 Register"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x310 "LCDC_OVR1CLUT196,Overlay 1 CLUT Register 196 Register"
|
|
hexmask.long.byte 0x310 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x310 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x310 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x310 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x314 "LCDC_OVR1CLUT197,Overlay 1 CLUT Register 197 Register"
|
|
hexmask.long.byte 0x314 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x314 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x314 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x314 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x318 "LCDC_OVR1CLUT198,Overlay 1 CLUT Register 198 Register"
|
|
hexmask.long.byte 0x318 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x318 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x318 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x318 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x31C "LCDC_OVR1CLUT199,Overlay 1 CLUT Register 199 Register"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x31C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x31C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x31C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x320 "LCDC_OVR1CLUT200,Overlay 1 CLUT Register 200 Register"
|
|
hexmask.long.byte 0x320 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x320 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x320 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x320 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x324 "LCDC_OVR1CLUT201,Overlay 1 CLUT Register 201 Register"
|
|
hexmask.long.byte 0x324 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x324 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x324 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x324 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x328 "LCDC_OVR1CLUT202,Overlay 1 CLUT Register 202 Register"
|
|
hexmask.long.byte 0x328 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x328 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x328 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x328 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x32C "LCDC_OVR1CLUT203,Overlay 1 CLUT Register 203 Register"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x32C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x32C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x32C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x330 "LCDC_OVR1CLUT204,Overlay 1 CLUT Register 204 Register"
|
|
hexmask.long.byte 0x330 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x330 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x330 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x330 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x334 "LCDC_OVR1CLUT205,Overlay 1 CLUT Register 205 Register"
|
|
hexmask.long.byte 0x334 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x334 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x334 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x334 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x338 "LCDC_OVR1CLUT206,Overlay 1 CLUT Register 206 Register"
|
|
hexmask.long.byte 0x338 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x338 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x338 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x338 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x33C "LCDC_OVR1CLUT207,Overlay 1 CLUT Register 207 Register"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x33C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x33C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x33C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x340 "LCDC_OVR1CLUT208,Overlay 1 CLUT Register 208 Register"
|
|
hexmask.long.byte 0x340 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x340 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x340 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x340 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x344 "LCDC_OVR1CLUT209,Overlay 1 CLUT Register 209 Register"
|
|
hexmask.long.byte 0x344 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x344 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x344 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x344 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x348 "LCDC_OVR1CLUT210,Overlay 1 CLUT Register 210 Register"
|
|
hexmask.long.byte 0x348 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x348 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x348 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x348 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34C "LCDC_OVR1CLUT211,Overlay 1 CLUT Register 211 Register"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x350 "LCDC_OVR1CLUT212,Overlay 1 CLUT Register 212 Register"
|
|
hexmask.long.byte 0x350 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x350 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x350 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x350 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x354 "LCDC_OVR1CLUT213,Overlay 1 CLUT Register 213 Register"
|
|
hexmask.long.byte 0x354 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x354 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x354 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x354 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x358 "LCDC_OVR1CLUT214,Overlay 1 CLUT Register 214 Register"
|
|
hexmask.long.byte 0x358 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x358 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x358 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x358 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x35C "LCDC_OVR1CLUT215,Overlay 1 CLUT Register 215 Register"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x35C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x35C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x35C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x360 "LCDC_OVR1CLUT216,Overlay 1 CLUT Register 216 Register"
|
|
hexmask.long.byte 0x360 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x360 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x360 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x360 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x364 "LCDC_OVR1CLUT217,Overlay 1 CLUT Register 217 Register"
|
|
hexmask.long.byte 0x364 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x364 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x364 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x364 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x368 "LCDC_OVR1CLUT218,Overlay 1 CLUT Register 218 Register"
|
|
hexmask.long.byte 0x368 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x368 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x368 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x368 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x36C "LCDC_OVR1CLUT219,Overlay 1 CLUT Register 219 Register"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x36C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x36C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x36C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x370 "LCDC_OVR1CLUT220,Overlay 1 CLUT Register 220 Register"
|
|
hexmask.long.byte 0x370 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x370 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x370 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x370 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x374 "LCDC_OVR1CLUT221,Overlay 1 CLUT Register 221 Register"
|
|
hexmask.long.byte 0x374 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x374 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x374 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x374 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x378 "LCDC_OVR1CLUT222,Overlay 1 CLUT Register 222 Register"
|
|
hexmask.long.byte 0x378 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x378 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x378 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x378 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x37C "LCDC_OVR1CLUT223,Overlay 1 CLUT Register 223 Register"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x37C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x37C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x37C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x380 "LCDC_OVR1CLUT224,Overlay 1 CLUT Register 224 Register"
|
|
hexmask.long.byte 0x380 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x380 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x380 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x380 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x384 "LCDC_OVR1CLUT225,Overlay 1 CLUT Register 225 Register"
|
|
hexmask.long.byte 0x384 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x384 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x384 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x384 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x388 "LCDC_OVR1CLUT226,Overlay 1 CLUT Register 226 Register"
|
|
hexmask.long.byte 0x388 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x388 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x388 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x388 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38C "LCDC_OVR1CLUT227,Overlay 1 CLUT Register 227 Register"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x390 "LCDC_OVR1CLUT228,Overlay 1 CLUT Register 228 Register"
|
|
hexmask.long.byte 0x390 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x390 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x390 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x390 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x394 "LCDC_OVR1CLUT229,Overlay 1 CLUT Register 229 Register"
|
|
hexmask.long.byte 0x394 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x394 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x394 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x394 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x398 "LCDC_OVR1CLUT230,Overlay 1 CLUT Register 230 Register"
|
|
hexmask.long.byte 0x398 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x398 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x398 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x398 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x39C "LCDC_OVR1CLUT231,Overlay 1 CLUT Register 231 Register"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x39C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x39C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x39C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A0 "LCDC_OVR1CLUT232,Overlay 1 CLUT Register 232 Register"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A4 "LCDC_OVR1CLUT233,Overlay 1 CLUT Register 233 Register"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A8 "LCDC_OVR1CLUT234,Overlay 1 CLUT Register 234 Register"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3AC "LCDC_OVR1CLUT235,Overlay 1 CLUT Register 235 Register"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B0 "LCDC_OVR1CLUT236,Overlay 1 CLUT Register 236 Register"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B4 "LCDC_OVR1CLUT237,Overlay 1 CLUT Register 237 Register"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B8 "LCDC_OVR1CLUT238,Overlay 1 CLUT Register 238 Register"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3BC "LCDC_OVR1CLUT239,Overlay 1 CLUT Register 239 Register"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C0 "LCDC_OVR1CLUT240,Overlay 1 CLUT Register 240 Register"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C4 "LCDC_OVR1CLUT241,Overlay 1 CLUT Register 241 Register"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C8 "LCDC_OVR1CLUT242,Overlay 1 CLUT Register 242 Register"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3CC "LCDC_OVR1CLUT243,Overlay 1 CLUT Register 243 Register"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D0 "LCDC_OVR1CLUT244,Overlay 1 CLUT Register 244 Register"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D4 "LCDC_OVR1CLUT245,Overlay 1 CLUT Register 245 Register"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D8 "LCDC_OVR1CLUT246,Overlay 1 CLUT Register 246 Register"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3DC "LCDC_OVR1CLUT247,Overlay 1 CLUT Register 247 Register"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E0 "LCDC_OVR1CLUT248,Overlay 1 CLUT Register 248 Register"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E4 "LCDC_OVR1CLUT249,Overlay 1 CLUT Register 249 Register"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E8 "LCDC_OVR1CLUT250,Overlay 1 CLUT Register 250 Register"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3EC "LCDC_OVR1CLUT251,Overlay 1 CLUT Register 251 Register"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F0 "LCDC_OVR1CLUT252,Overlay 1 CLUT Register 252 Register"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F4 "LCDC_OVR1CLUT253,Overlay 1 CLUT Register 253 Register"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F8 "LCDC_OVR1CLUT254,Overlay 1 CLUT Register 254 Register"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3FC "LCDC_OVR1CLUT255,Overlay 1 CLUT Register 255 Register"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
tree.end
|
|
tree "High End Overlay CLUT Registers"
|
|
group.long 0x1000++0x3ff
|
|
line.long 0x0 "LCDC_HEOCLUT0,High End Overlay CLUT Register 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4 "LCDC_HEOCLUT1,High End Overlay CLUT Register 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8 "LCDC_HEOCLUT2,High End Overlay CLUT Register 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC "LCDC_HEOCLUT3,High End Overlay CLUT Register 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10 "LCDC_HEOCLUT4,High End Overlay CLUT Register 4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14 "LCDC_HEOCLUT5,High End Overlay CLUT Register 5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18 "LCDC_HEOCLUT6,High End Overlay CLUT Register 6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C "LCDC_HEOCLUT7,High End Overlay CLUT Register 7 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20 "LCDC_HEOCLUT8,High End Overlay CLUT Register 8 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24 "LCDC_HEOCLUT9,High End Overlay CLUT Register 9 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28 "LCDC_HEOCLUT10,High End Overlay CLUT Register 10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C "LCDC_HEOCLUT11,High End Overlay CLUT Register 11 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30 "LCDC_HEOCLUT12,High End Overlay CLUT Register 12 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34 "LCDC_HEOCLUT13,High End Overlay CLUT Register 13 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38 "LCDC_HEOCLUT14,High End Overlay CLUT Register 14 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C "LCDC_HEOCLUT15,High End Overlay CLUT Register 15 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x40 "LCDC_HEOCLUT16,High End Overlay CLUT Register 16 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x40 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x40 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x40 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x44 "LCDC_HEOCLUT17,High End Overlay CLUT Register 17 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x44 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x44 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x44 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x48 "LCDC_HEOCLUT18,High End Overlay CLUT Register 18 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x48 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x48 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x48 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4C "LCDC_HEOCLUT19,High End Overlay CLUT Register 19 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x50 "LCDC_HEOCLUT20,High End Overlay CLUT Register 20 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x50 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x50 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x50 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x54 "LCDC_HEOCLUT21,High End Overlay CLUT Register 21 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x54 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x54 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x54 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x58 "LCDC_HEOCLUT22,High End Overlay CLUT Register 22 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x58 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x58 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x58 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x5C "LCDC_HEOCLUT23,High End Overlay CLUT Register 23 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x60 "LCDC_HEOCLUT24,High End Overlay CLUT Register 24 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x60 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x60 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x60 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x64 "LCDC_HEOCLUT25,High End Overlay CLUT Register 25 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x64 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x64 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x64 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x68 "LCDC_HEOCLUT26,High End Overlay CLUT Register 26 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x68 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x68 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x68 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x6C "LCDC_HEOCLUT27,High End Overlay CLUT Register 27 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x70 "LCDC_HEOCLUT28,High End Overlay CLUT Register 28 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x70 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x70 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x70 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x74 "LCDC_HEOCLUT29,High End Overlay CLUT Register 29 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x74 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x74 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x74 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x78 "LCDC_HEOCLUT30,High End Overlay CLUT Register 30 Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x78 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x78 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x78 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x7C "LCDC_HEOCLUT31,High End Overlay CLUT Register 31 Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x80 "LCDC_HEOCLUT32,High End Overlay CLUT Register 32 Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x80 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x80 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x80 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x84 "LCDC_HEOCLUT33,High End Overlay CLUT Register 33 Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x84 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x84 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x84 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x88 "LCDC_HEOCLUT34,High End Overlay CLUT Register 34 Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x88 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x88 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x88 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8C "LCDC_HEOCLUT35,High End Overlay CLUT Register 35 Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x90 "LCDC_HEOCLUT36,High End Overlay CLUT Register 36 Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x90 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x90 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x90 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x94 "LCDC_HEOCLUT37,High End Overlay CLUT Register 37 Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x94 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x94 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x94 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x98 "LCDC_HEOCLUT38,High End Overlay CLUT Register 38 Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x98 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x98 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x98 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x9C "LCDC_HEOCLUT39,High End Overlay CLUT Register 39 Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA0 "LCDC_HEOCLUT40,High End Overlay CLUT Register 40 Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA4 "LCDC_HEOCLUT41,High End Overlay CLUT Register 41 Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA8 "LCDC_HEOCLUT42,High End Overlay CLUT Register 42 Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xAC "LCDC_HEOCLUT43,High End Overlay CLUT Register 43 Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB0 "LCDC_HEOCLUT44,High End Overlay CLUT Register 44 Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB4 "LCDC_HEOCLUT45,High End Overlay CLUT Register 45 Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB8 "LCDC_HEOCLUT46,High End Overlay CLUT Register 46 Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xBC "LCDC_HEOCLUT47,High End Overlay CLUT Register 47 Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC0 "LCDC_HEOCLUT48,High End Overlay CLUT Register 48 Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC4 "LCDC_HEOCLUT49,High End Overlay CLUT Register 49 Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC8 "LCDC_HEOCLUT50,High End Overlay CLUT Register 50 Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xCC "LCDC_HEOCLUT51,High End Overlay CLUT Register 51 Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD0 "LCDC_HEOCLUT52,High End Overlay CLUT Register 52 Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD4 "LCDC_HEOCLUT53,High End Overlay CLUT Register 53 Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD8 "LCDC_HEOCLUT54,High End Overlay CLUT Register 54 Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xDC "LCDC_HEOCLUT55,High End Overlay CLUT Register 55 Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE0 "LCDC_HEOCLUT56,High End Overlay CLUT Register 56 Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE4 "LCDC_HEOCLUT57,High End Overlay CLUT Register 57 Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE8 "LCDC_HEOCLUT58,High End Overlay CLUT Register 58 Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xEC "LCDC_HEOCLUT59,High End Overlay CLUT Register 59 Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF0 "LCDC_HEOCLUT60,High End Overlay CLUT Register 60 Register"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF4 "LCDC_HEOCLUT61,High End Overlay CLUT Register 61 Register"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF8 "LCDC_HEOCLUT62,High End Overlay CLUT Register 62 Register"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xFC "LCDC_HEOCLUT63,High End Overlay CLUT Register 63 Register"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xFC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xFC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x100 "LCDC_HEOCLUT64,High End Overlay CLUT Register 64 Register"
|
|
hexmask.long.byte 0x100 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x100 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x100 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x100 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x104 "LCDC_HEOCLUT65,High End Overlay CLUT Register 65 Register"
|
|
hexmask.long.byte 0x104 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x104 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x104 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x104 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x108 "LCDC_HEOCLUT66,High End Overlay CLUT Register 66 Register"
|
|
hexmask.long.byte 0x108 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x108 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x108 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x108 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10C "LCDC_HEOCLUT67,High End Overlay CLUT Register 67 Register"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x110 "LCDC_HEOCLUT68,High End Overlay CLUT Register 68 Register"
|
|
hexmask.long.byte 0x110 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x110 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x110 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x110 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x114 "LCDC_HEOCLUT69,High End Overlay CLUT Register 69 Register"
|
|
hexmask.long.byte 0x114 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x114 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x114 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x114 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x118 "LCDC_HEOCLUT70,High End Overlay CLUT Register 70 Register"
|
|
hexmask.long.byte 0x118 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x118 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x118 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x118 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x11C "LCDC_HEOCLUT71,High End Overlay CLUT Register 71 Register"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x11C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x11C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x11C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x120 "LCDC_HEOCLUT72,High End Overlay CLUT Register 72 Register"
|
|
hexmask.long.byte 0x120 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x120 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x120 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x120 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x124 "LCDC_HEOCLUT73,High End Overlay CLUT Register 73 Register"
|
|
hexmask.long.byte 0x124 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x124 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x124 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x124 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x128 "LCDC_HEOCLUT74,High End Overlay CLUT Register 74 Register"
|
|
hexmask.long.byte 0x128 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x128 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x128 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x128 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x12C "LCDC_HEOCLUT75,High End Overlay CLUT Register 75 Register"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x12C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x12C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x12C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x130 "LCDC_HEOCLUT76,High End Overlay CLUT Register 76 Register"
|
|
hexmask.long.byte 0x130 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x130 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x130 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x130 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x134 "LCDC_HEOCLUT77,High End Overlay CLUT Register 77 Register"
|
|
hexmask.long.byte 0x134 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x134 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x134 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x134 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x138 "LCDC_HEOCLUT78,High End Overlay CLUT Register 78 Register"
|
|
hexmask.long.byte 0x138 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x138 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x138 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x138 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x13C "LCDC_HEOCLUT79,High End Overlay CLUT Register 79 Register"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x13C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x13C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x13C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x140 "LCDC_HEOCLUT80,High End Overlay CLUT Register 80 Register"
|
|
hexmask.long.byte 0x140 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x140 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x140 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x140 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x144 "LCDC_HEOCLUT81,High End Overlay CLUT Register 81 Register"
|
|
hexmask.long.byte 0x144 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x144 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x144 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x144 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x148 "LCDC_HEOCLUT82,High End Overlay CLUT Register 82 Register"
|
|
hexmask.long.byte 0x148 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x148 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x148 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x148 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14C "LCDC_HEOCLUT83,High End Overlay CLUT Register 83 Register"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x150 "LCDC_HEOCLUT84,High End Overlay CLUT Register 84 Register"
|
|
hexmask.long.byte 0x150 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x150 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x150 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x150 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x154 "LCDC_HEOCLUT85,High End Overlay CLUT Register 85 Register"
|
|
hexmask.long.byte 0x154 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x154 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x154 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x154 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x158 "LCDC_HEOCLUT86,High End Overlay CLUT Register 86 Register"
|
|
hexmask.long.byte 0x158 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x158 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x158 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x158 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x15C "LCDC_HEOCLUT87,High End Overlay CLUT Register 87 Register"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x15C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x15C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x15C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x160 "LCDC_HEOCLUT88,High End Overlay CLUT Register 88 Register"
|
|
hexmask.long.byte 0x160 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x160 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x160 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x160 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x164 "LCDC_HEOCLUT89,High End Overlay CLUT Register 89 Register"
|
|
hexmask.long.byte 0x164 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x164 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x164 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x164 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x168 "LCDC_HEOCLUT90,High End Overlay CLUT Register 90 Register"
|
|
hexmask.long.byte 0x168 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x168 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x168 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x168 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x16C "LCDC_HEOCLUT91,High End Overlay CLUT Register 91 Register"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x16C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x16C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x16C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x170 "LCDC_HEOCLUT92,High End Overlay CLUT Register 92 Register"
|
|
hexmask.long.byte 0x170 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x170 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x170 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x170 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x174 "LCDC_HEOCLUT93,High End Overlay CLUT Register 93 Register"
|
|
hexmask.long.byte 0x174 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x174 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x174 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x174 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x178 "LCDC_HEOCLUT94,High End Overlay CLUT Register 94 Register"
|
|
hexmask.long.byte 0x178 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x178 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x178 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x178 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x17C "LCDC_HEOCLUT95,High End Overlay CLUT Register 95 Register"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x17C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x17C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x17C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x180 "LCDC_HEOCLUT96,High End Overlay CLUT Register 96 Register"
|
|
hexmask.long.byte 0x180 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x180 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x180 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x180 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x184 "LCDC_HEOCLUT97,High End Overlay CLUT Register 97 Register"
|
|
hexmask.long.byte 0x184 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x184 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x184 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x184 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x188 "LCDC_HEOCLUT98,High End Overlay CLUT Register 98 Register"
|
|
hexmask.long.byte 0x188 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x188 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x188 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x188 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18C "LCDC_HEOCLUT99,High End Overlay CLUT Register 99 Register"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x190 "LCDC_HEOCLUT100,High End Overlay CLUT Register 100 Register"
|
|
hexmask.long.byte 0x190 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x190 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x190 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x190 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x194 "LCDC_HEOCLUT101,High End Overlay CLUT Register 101 Register"
|
|
hexmask.long.byte 0x194 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x194 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x194 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x194 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x198 "LCDC_HEOCLUT102,High End Overlay CLUT Register 102 Register"
|
|
hexmask.long.byte 0x198 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x198 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x198 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x198 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x19C "LCDC_HEOCLUT103,High End Overlay CLUT Register 103 Register"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x19C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x19C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x19C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A0 "LCDC_HEOCLUT104,High End Overlay CLUT Register 104 Register"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A4 "LCDC_HEOCLUT105,High End Overlay CLUT Register 105 Register"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A8 "LCDC_HEOCLUT106,High End Overlay CLUT Register 106 Register"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1AC "LCDC_HEOCLUT107,High End Overlay CLUT Register 107 Register"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B0 "LCDC_HEOCLUT108,High End Overlay CLUT Register 108 Register"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B4 "LCDC_HEOCLUT109,High End Overlay CLUT Register 109 Register"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B8 "LCDC_HEOCLUT110,High End Overlay CLUT Register 110 Register"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1BC "LCDC_HEOCLUT111,High End Overlay CLUT Register 111 Register"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C0 "LCDC_HEOCLUT112,High End Overlay CLUT Register 112 Register"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C4 "LCDC_HEOCLUT113,High End Overlay CLUT Register 113 Register"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C8 "LCDC_HEOCLUT114,High End Overlay CLUT Register 114 Register"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1CC "LCDC_HEOCLUT115,High End Overlay CLUT Register 115 Register"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D0 "LCDC_HEOCLUT116,High End Overlay CLUT Register 116 Register"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D4 "LCDC_HEOCLUT117,High End Overlay CLUT Register 117 Register"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D8 "LCDC_HEOCLUT118,High End Overlay CLUT Register 118 Register"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1DC "LCDC_HEOCLUT119,High End Overlay CLUT Register 119 Register"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E0 "LCDC_HEOCLUT120,High End Overlay CLUT Register 120 Register"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E4 "LCDC_HEOCLUT121,High End Overlay CLUT Register 121 Register"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E8 "LCDC_HEOCLUT122,High End Overlay CLUT Register 122 Register"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1EC "LCDC_HEOCLUT123,High End Overlay CLUT Register 123 Register"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F0 "LCDC_HEOCLUT124,High End Overlay CLUT Register 124 Register"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F4 "LCDC_HEOCLUT125,High End Overlay CLUT Register 125 Register"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F8 "LCDC_HEOCLUT126,High End Overlay CLUT Register 126 Register"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1FC "LCDC_HEOCLUT127,High End Overlay CLUT Register 127 Register"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x200 "LCDC_HEOCLUT128,High End Overlay CLUT Register 128 Register"
|
|
hexmask.long.byte 0x200 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x200 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x200 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x200 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x204 "LCDC_HEOCLUT129,High End Overlay CLUT Register 129 Register"
|
|
hexmask.long.byte 0x204 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x204 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x204 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x204 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x208 "LCDC_HEOCLUT130,High End Overlay CLUT Register 130 Register"
|
|
hexmask.long.byte 0x208 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x208 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x208 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x208 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20C "LCDC_HEOCLUT131,High End Overlay CLUT Register 131 Register"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x210 "LCDC_HEOCLUT132,High End Overlay CLUT Register 132 Register"
|
|
hexmask.long.byte 0x210 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x210 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x210 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x210 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x214 "LCDC_HEOCLUT133,High End Overlay CLUT Register 133 Register"
|
|
hexmask.long.byte 0x214 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x214 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x214 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x214 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x218 "LCDC_HEOCLUT134,High End Overlay CLUT Register 134 Register"
|
|
hexmask.long.byte 0x218 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x218 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x218 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x218 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x21C "LCDC_HEOCLUT135,High End Overlay CLUT Register 135 Register"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x21C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x21C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x21C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x220 "LCDC_HEOCLUT136,High End Overlay CLUT Register 136 Register"
|
|
hexmask.long.byte 0x220 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x220 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x220 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x220 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x224 "LCDC_HEOCLUT137,High End Overlay CLUT Register 137 Register"
|
|
hexmask.long.byte 0x224 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x224 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x224 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x224 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x228 "LCDC_HEOCLUT138,High End Overlay CLUT Register 138 Register"
|
|
hexmask.long.byte 0x228 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x228 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x228 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x228 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x22C "LCDC_HEOCLUT139,High End Overlay CLUT Register 139 Register"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x22C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x22C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x22C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x230 "LCDC_HEOCLUT140,High End Overlay CLUT Register 140 Register"
|
|
hexmask.long.byte 0x230 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x230 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x230 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x230 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x234 "LCDC_HEOCLUT141,High End Overlay CLUT Register 141 Register"
|
|
hexmask.long.byte 0x234 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x234 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x234 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x234 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x238 "LCDC_HEOCLUT142,High End Overlay CLUT Register 142 Register"
|
|
hexmask.long.byte 0x238 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x238 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x238 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x238 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x23C "LCDC_HEOCLUT143,High End Overlay CLUT Register 143 Register"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x23C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x23C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x23C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x240 "LCDC_HEOCLUT144,High End Overlay CLUT Register 144 Register"
|
|
hexmask.long.byte 0x240 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x240 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x240 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x240 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x244 "LCDC_HEOCLUT145,High End Overlay CLUT Register 145 Register"
|
|
hexmask.long.byte 0x244 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x244 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x244 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x244 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x248 "LCDC_HEOCLUT146,High End Overlay CLUT Register 146 Register"
|
|
hexmask.long.byte 0x248 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x248 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x248 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x248 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24C "LCDC_HEOCLUT147,High End Overlay CLUT Register 147 Register"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x250 "LCDC_HEOCLUT148,High End Overlay CLUT Register 148 Register"
|
|
hexmask.long.byte 0x250 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x250 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x250 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x250 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x254 "LCDC_HEOCLUT149,High End Overlay CLUT Register 149 Register"
|
|
hexmask.long.byte 0x254 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x254 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x254 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x254 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x258 "LCDC_HEOCLUT150,High End Overlay CLUT Register 150 Register"
|
|
hexmask.long.byte 0x258 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x258 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x258 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x258 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x25C "LCDC_HEOCLUT151,High End Overlay CLUT Register 151 Register"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x25C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x25C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x25C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x260 "LCDC_HEOCLUT152,High End Overlay CLUT Register 152 Register"
|
|
hexmask.long.byte 0x260 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x260 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x260 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x260 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x264 "LCDC_HEOCLUT153,High End Overlay CLUT Register 153 Register"
|
|
hexmask.long.byte 0x264 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x264 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x264 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x264 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x268 "LCDC_HEOCLUT154,High End Overlay CLUT Register 154 Register"
|
|
hexmask.long.byte 0x268 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x268 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x268 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x268 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x26C "LCDC_HEOCLUT155,High End Overlay CLUT Register 155 Register"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x26C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x26C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x26C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x270 "LCDC_HEOCLUT156,High End Overlay CLUT Register 156 Register"
|
|
hexmask.long.byte 0x270 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x270 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x270 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x270 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x274 "LCDC_HEOCLUT157,High End Overlay CLUT Register 157 Register"
|
|
hexmask.long.byte 0x274 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x274 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x274 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x274 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x278 "LCDC_HEOCLUT158,High End Overlay CLUT Register 158 Register"
|
|
hexmask.long.byte 0x278 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x278 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x278 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x278 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x27C "LCDC_HEOCLUT159,High End Overlay CLUT Register 159 Register"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x27C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x27C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x27C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x280 "LCDC_HEOCLUT160,High End Overlay CLUT Register 160 Register"
|
|
hexmask.long.byte 0x280 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x280 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x280 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x280 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x284 "LCDC_HEOCLUT161,High End Overlay CLUT Register 161 Register"
|
|
hexmask.long.byte 0x284 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x284 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x284 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x284 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x288 "LCDC_HEOCLUT162,High End Overlay CLUT Register 162 Register"
|
|
hexmask.long.byte 0x288 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x288 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x288 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x288 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28C "LCDC_HEOCLUT163,High End Overlay CLUT Register 163 Register"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x290 "LCDC_HEOCLUT164,High End Overlay CLUT Register 164 Register"
|
|
hexmask.long.byte 0x290 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x290 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x290 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x290 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x294 "LCDC_HEOCLUT165,High End Overlay CLUT Register 165 Register"
|
|
hexmask.long.byte 0x294 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x294 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x294 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x294 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x298 "LCDC_HEOCLUT166,High End Overlay CLUT Register 166 Register"
|
|
hexmask.long.byte 0x298 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x298 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x298 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x298 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x29C "LCDC_HEOCLUT167,High End Overlay CLUT Register 167 Register"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x29C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x29C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x29C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A0 "LCDC_HEOCLUT168,High End Overlay CLUT Register 168 Register"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A4 "LCDC_HEOCLUT169,High End Overlay CLUT Register 169 Register"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A8 "LCDC_HEOCLUT170,High End Overlay CLUT Register 170 Register"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2AC "LCDC_HEOCLUT171,High End Overlay CLUT Register 171 Register"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B0 "LCDC_HEOCLUT172,High End Overlay CLUT Register 172 Register"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B4 "LCDC_HEOCLUT173,High End Overlay CLUT Register 173 Register"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B8 "LCDC_HEOCLUT174,High End Overlay CLUT Register 174 Register"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2BC "LCDC_HEOCLUT175,High End Overlay CLUT Register 175 Register"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C0 "LCDC_HEOCLUT176,High End Overlay CLUT Register 176 Register"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C4 "LCDC_HEOCLUT177,High End Overlay CLUT Register 177 Register"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C8 "LCDC_HEOCLUT178,High End Overlay CLUT Register 178 Register"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2CC "LCDC_HEOCLUT179,High End Overlay CLUT Register 179 Register"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D0 "LCDC_HEOCLUT180,High End Overlay CLUT Register 180 Register"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D4 "LCDC_HEOCLUT181,High End Overlay CLUT Register 181 Register"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D8 "LCDC_HEOCLUT182,High End Overlay CLUT Register 182 Register"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2DC "LCDC_HEOCLUT183,High End Overlay CLUT Register 183 Register"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E0 "LCDC_HEOCLUT184,High End Overlay CLUT Register 184 Register"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E4 "LCDC_HEOCLUT185,High End Overlay CLUT Register 185 Register"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E8 "LCDC_HEOCLUT186,High End Overlay CLUT Register 186 Register"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2EC "LCDC_HEOCLUT187,High End Overlay CLUT Register 187 Register"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F0 "LCDC_HEOCLUT188,High End Overlay CLUT Register 188 Register"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F4 "LCDC_HEOCLUT189,High End Overlay CLUT Register 189 Register"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F8 "LCDC_HEOCLUT190,High End Overlay CLUT Register 190 Register"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2FC "LCDC_HEOCLUT191,High End Overlay CLUT Register 191 Register"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x300 "LCDC_HEOCLUT192,High End Overlay CLUT Register 192 Register"
|
|
hexmask.long.byte 0x300 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x300 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x300 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x300 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x304 "LCDC_HEOCLUT193,High End Overlay CLUT Register 193 Register"
|
|
hexmask.long.byte 0x304 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x304 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x304 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x304 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x308 "LCDC_HEOCLUT194,High End Overlay CLUT Register 194 Register"
|
|
hexmask.long.byte 0x308 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x308 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x308 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x308 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30C "LCDC_HEOCLUT195,High End Overlay CLUT Register 195 Register"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x310 "LCDC_HEOCLUT196,High End Overlay CLUT Register 196 Register"
|
|
hexmask.long.byte 0x310 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x310 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x310 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x310 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x314 "LCDC_HEOCLUT197,High End Overlay CLUT Register 197 Register"
|
|
hexmask.long.byte 0x314 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x314 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x314 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x314 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x318 "LCDC_HEOCLUT198,High End Overlay CLUT Register 198 Register"
|
|
hexmask.long.byte 0x318 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x318 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x318 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x318 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x31C "LCDC_HEOCLUT199,High End Overlay CLUT Register 199 Register"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x31C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x31C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x31C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x320 "LCDC_HEOCLUT200,High End Overlay CLUT Register 200 Register"
|
|
hexmask.long.byte 0x320 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x320 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x320 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x320 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x324 "LCDC_HEOCLUT201,High End Overlay CLUT Register 201 Register"
|
|
hexmask.long.byte 0x324 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x324 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x324 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x324 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x328 "LCDC_HEOCLUT202,High End Overlay CLUT Register 202 Register"
|
|
hexmask.long.byte 0x328 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x328 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x328 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x328 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x32C "LCDC_HEOCLUT203,High End Overlay CLUT Register 203 Register"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x32C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x32C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x32C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x330 "LCDC_HEOCLUT204,High End Overlay CLUT Register 204 Register"
|
|
hexmask.long.byte 0x330 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x330 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x330 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x330 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x334 "LCDC_HEOCLUT205,High End Overlay CLUT Register 205 Register"
|
|
hexmask.long.byte 0x334 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x334 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x334 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x334 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x338 "LCDC_HEOCLUT206,High End Overlay CLUT Register 206 Register"
|
|
hexmask.long.byte 0x338 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x338 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x338 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x338 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x33C "LCDC_HEOCLUT207,High End Overlay CLUT Register 207 Register"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x33C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x33C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x33C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x340 "LCDC_HEOCLUT208,High End Overlay CLUT Register 208 Register"
|
|
hexmask.long.byte 0x340 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x340 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x340 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x340 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x344 "LCDC_HEOCLUT209,High End Overlay CLUT Register 209 Register"
|
|
hexmask.long.byte 0x344 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x344 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x344 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x344 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x348 "LCDC_HEOCLUT210,High End Overlay CLUT Register 210 Register"
|
|
hexmask.long.byte 0x348 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x348 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x348 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x348 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34C "LCDC_HEOCLUT211,High End Overlay CLUT Register 211 Register"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x350 "LCDC_HEOCLUT212,High End Overlay CLUT Register 212 Register"
|
|
hexmask.long.byte 0x350 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x350 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x350 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x350 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x354 "LCDC_HEOCLUT213,High End Overlay CLUT Register 213 Register"
|
|
hexmask.long.byte 0x354 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x354 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x354 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x354 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x358 "LCDC_HEOCLUT214,High End Overlay CLUT Register 214 Register"
|
|
hexmask.long.byte 0x358 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x358 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x358 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x358 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x35C "LCDC_HEOCLUT215,High End Overlay CLUT Register 215 Register"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x35C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x35C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x35C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x360 "LCDC_HEOCLUT216,High End Overlay CLUT Register 216 Register"
|
|
hexmask.long.byte 0x360 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x360 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x360 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x360 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x364 "LCDC_HEOCLUT217,High End Overlay CLUT Register 217 Register"
|
|
hexmask.long.byte 0x364 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x364 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x364 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x364 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x368 "LCDC_HEOCLUT218,High End Overlay CLUT Register 218 Register"
|
|
hexmask.long.byte 0x368 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x368 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x368 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x368 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x36C "LCDC_HEOCLUT219,High End Overlay CLUT Register 219 Register"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x36C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x36C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x36C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x370 "LCDC_HEOCLUT220,High End Overlay CLUT Register 220 Register"
|
|
hexmask.long.byte 0x370 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x370 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x370 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x370 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x374 "LCDC_HEOCLUT221,High End Overlay CLUT Register 221 Register"
|
|
hexmask.long.byte 0x374 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x374 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x374 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x374 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x378 "LCDC_HEOCLUT222,High End Overlay CLUT Register 222 Register"
|
|
hexmask.long.byte 0x378 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x378 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x378 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x378 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x37C "LCDC_HEOCLUT223,High End Overlay CLUT Register 223 Register"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x37C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x37C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x37C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x380 "LCDC_HEOCLUT224,High End Overlay CLUT Register 224 Register"
|
|
hexmask.long.byte 0x380 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x380 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x380 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x380 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x384 "LCDC_HEOCLUT225,High End Overlay CLUT Register 225 Register"
|
|
hexmask.long.byte 0x384 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x384 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x384 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x384 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x388 "LCDC_HEOCLUT226,High End Overlay CLUT Register 226 Register"
|
|
hexmask.long.byte 0x388 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x388 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x388 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x388 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38C "LCDC_HEOCLUT227,High End Overlay CLUT Register 227 Register"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x390 "LCDC_HEOCLUT228,High End Overlay CLUT Register 228 Register"
|
|
hexmask.long.byte 0x390 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x390 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x390 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x390 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x394 "LCDC_HEOCLUT229,High End Overlay CLUT Register 229 Register"
|
|
hexmask.long.byte 0x394 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x394 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x394 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x394 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x398 "LCDC_HEOCLUT230,High End Overlay CLUT Register 230 Register"
|
|
hexmask.long.byte 0x398 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x398 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x398 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x398 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x39C "LCDC_HEOCLUT231,High End Overlay CLUT Register 231 Register"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x39C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x39C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x39C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A0 "LCDC_HEOCLUT232,High End Overlay CLUT Register 232 Register"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A4 "LCDC_HEOCLUT233,High End Overlay CLUT Register 233 Register"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A8 "LCDC_HEOCLUT234,High End Overlay CLUT Register 234 Register"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3AC "LCDC_HEOCLUT235,High End Overlay CLUT Register 235 Register"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B0 "LCDC_HEOCLUT236,High End Overlay CLUT Register 236 Register"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B4 "LCDC_HEOCLUT237,High End Overlay CLUT Register 237 Register"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B8 "LCDC_HEOCLUT238,High End Overlay CLUT Register 238 Register"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3BC "LCDC_HEOCLUT239,High End Overlay CLUT Register 239 Register"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C0 "LCDC_HEOCLUT240,High End Overlay CLUT Register 240 Register"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C4 "LCDC_HEOCLUT241,High End Overlay CLUT Register 241 Register"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C8 "LCDC_HEOCLUT242,High End Overlay CLUT Register 242 Register"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3CC "LCDC_HEOCLUT243,High End Overlay CLUT Register 243 Register"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D0 "LCDC_HEOCLUT244,High End Overlay CLUT Register 244 Register"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D4 "LCDC_HEOCLUT245,High End Overlay CLUT Register 245 Register"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D8 "LCDC_HEOCLUT246,High End Overlay CLUT Register 246 Register"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3DC "LCDC_HEOCLUT247,High End Overlay CLUT Register 247 Register"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E0 "LCDC_HEOCLUT248,High End Overlay CLUT Register 248 Register"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E4 "LCDC_HEOCLUT249,High End Overlay CLUT Register 249 Register"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E8 "LCDC_HEOCLUT250,High End Overlay CLUT Register 250 Register"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3EC "LCDC_HEOCLUT251,High End Overlay CLUT Register 251 Register"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F0 "LCDC_HEOCLUT252,High End Overlay CLUT Register 252 Register"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F4 "LCDC_HEOCLUT253,High End Overlay CLUT Register 253 Register"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F8 "LCDC_HEOCLUT254,High End Overlay CLUT Register 254 Register"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3FC "LCDC_HEOCLUT255,High End Overlay CLUT Register 255 Register"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
tree.end
|
|
tree "Hardware Cursor CLUT Registers"
|
|
group.long 0x1400++0x3ff
|
|
line.long 0x0 "LCDC_HCRCLUT0,Hardware Cursor CLUT Register 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4 "LCDC_HCRCLUT1,Hardware Cursor CLUT Register 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8 "LCDC_HCRCLUT2,Hardware Cursor CLUT Register 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC "LCDC_HCRCLUT3,Hardware Cursor CLUT Register 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10 "LCDC_HCRCLUT4,Hardware Cursor CLUT Register 4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14 "LCDC_HCRCLUT5,Hardware Cursor CLUT Register 5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18 "LCDC_HCRCLUT6,Hardware Cursor CLUT Register 6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C "LCDC_HCRCLUT7,Hardware Cursor CLUT Register 7 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20 "LCDC_HCRCLUT8,Hardware Cursor CLUT Register 8 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24 "LCDC_HCRCLUT9,Hardware Cursor CLUT Register 9 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28 "LCDC_HCRCLUT10,Hardware Cursor CLUT Register 10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C "LCDC_HCRCLUT11,Hardware Cursor CLUT Register 11 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30 "LCDC_HCRCLUT12,Hardware Cursor CLUT Register 12 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34 "LCDC_HCRCLUT13,Hardware Cursor CLUT Register 13 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38 "LCDC_HCRCLUT14,Hardware Cursor CLUT Register 14 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C "LCDC_HCRCLUT15,Hardware Cursor CLUT Register 15 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x40 "LCDC_HCRCLUT16,Hardware Cursor CLUT Register 16 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x40 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x40 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x40 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x44 "LCDC_HCRCLUT17,Hardware Cursor CLUT Register 17 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x44 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x44 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x44 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x48 "LCDC_HCRCLUT18,Hardware Cursor CLUT Register 18 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x48 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x48 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x48 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x4C "LCDC_HCRCLUT19,Hardware Cursor CLUT Register 19 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x50 "LCDC_HCRCLUT20,Hardware Cursor CLUT Register 20 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x50 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x50 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x50 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x54 "LCDC_HCRCLUT21,Hardware Cursor CLUT Register 21 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x54 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x54 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x54 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x58 "LCDC_HCRCLUT22,Hardware Cursor CLUT Register 22 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x58 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x58 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x58 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x5C "LCDC_HCRCLUT23,Hardware Cursor CLUT Register 23 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x60 "LCDC_HCRCLUT24,Hardware Cursor CLUT Register 24 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x60 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x60 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x60 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x64 "LCDC_HCRCLUT25,Hardware Cursor CLUT Register 25 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x64 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x64 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x64 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x68 "LCDC_HCRCLUT26,Hardware Cursor CLUT Register 26 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x68 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x68 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x68 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x6C "LCDC_HCRCLUT27,Hardware Cursor CLUT Register 27 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x70 "LCDC_HCRCLUT28,Hardware Cursor CLUT Register 28 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x70 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x70 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x70 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x74 "LCDC_HCRCLUT29,Hardware Cursor CLUT Register 29 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x74 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x74 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x74 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x78 "LCDC_HCRCLUT30,Hardware Cursor CLUT Register 30 Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x78 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x78 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x78 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x7C "LCDC_HCRCLUT31,Hardware Cursor CLUT Register 31 Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x80 "LCDC_HCRCLUT32,Hardware Cursor CLUT Register 32 Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x80 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x80 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x80 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x84 "LCDC_HCRCLUT33,Hardware Cursor CLUT Register 33 Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x84 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x84 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x84 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x88 "LCDC_HCRCLUT34,Hardware Cursor CLUT Register 34 Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x88 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x88 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x88 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x8C "LCDC_HCRCLUT35,Hardware Cursor CLUT Register 35 Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x90 "LCDC_HCRCLUT36,Hardware Cursor CLUT Register 36 Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x90 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x90 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x90 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x94 "LCDC_HCRCLUT37,Hardware Cursor CLUT Register 37 Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x94 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x94 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x94 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x98 "LCDC_HCRCLUT38,Hardware Cursor CLUT Register 38 Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x98 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x98 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x98 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x9C "LCDC_HCRCLUT39,Hardware Cursor CLUT Register 39 Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA0 "LCDC_HCRCLUT40,Hardware Cursor CLUT Register 40 Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA4 "LCDC_HCRCLUT41,Hardware Cursor CLUT Register 41 Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xA8 "LCDC_HCRCLUT42,Hardware Cursor CLUT Register 42 Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xAC "LCDC_HCRCLUT43,Hardware Cursor CLUT Register 43 Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB0 "LCDC_HCRCLUT44,Hardware Cursor CLUT Register 44 Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB4 "LCDC_HCRCLUT45,Hardware Cursor CLUT Register 45 Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xB8 "LCDC_HCRCLUT46,Hardware Cursor CLUT Register 46 Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xBC "LCDC_HCRCLUT47,Hardware Cursor CLUT Register 47 Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC0 "LCDC_HCRCLUT48,Hardware Cursor CLUT Register 48 Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC4 "LCDC_HCRCLUT49,Hardware Cursor CLUT Register 49 Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xC8 "LCDC_HCRCLUT50,Hardware Cursor CLUT Register 50 Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xCC "LCDC_HCRCLUT51,Hardware Cursor CLUT Register 51 Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD0 "LCDC_HCRCLUT52,Hardware Cursor CLUT Register 52 Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD4 "LCDC_HCRCLUT53,Hardware Cursor CLUT Register 53 Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xD8 "LCDC_HCRCLUT54,Hardware Cursor CLUT Register 54 Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xDC "LCDC_HCRCLUT55,Hardware Cursor CLUT Register 55 Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE0 "LCDC_HCRCLUT56,Hardware Cursor CLUT Register 56 Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE4 "LCDC_HCRCLUT57,Hardware Cursor CLUT Register 57 Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xE8 "LCDC_HCRCLUT58,Hardware Cursor CLUT Register 58 Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xEC "LCDC_HCRCLUT59,Hardware Cursor CLUT Register 59 Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF0 "LCDC_HCRCLUT60,Hardware Cursor CLUT Register 60 Register"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF4 "LCDC_HCRCLUT61,Hardware Cursor CLUT Register 61 Register"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xF8 "LCDC_HCRCLUT62,Hardware Cursor CLUT Register 62 Register"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xF8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xF8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0xFC "LCDC_HCRCLUT63,Hardware Cursor CLUT Register 63 Register"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0xFC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0xFC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x100 "LCDC_HCRCLUT64,Hardware Cursor CLUT Register 64 Register"
|
|
hexmask.long.byte 0x100 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x100 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x100 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x100 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x104 "LCDC_HCRCLUT65,Hardware Cursor CLUT Register 65 Register"
|
|
hexmask.long.byte 0x104 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x104 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x104 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x104 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x108 "LCDC_HCRCLUT66,Hardware Cursor CLUT Register 66 Register"
|
|
hexmask.long.byte 0x108 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x108 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x108 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x108 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x10C "LCDC_HCRCLUT67,Hardware Cursor CLUT Register 67 Register"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x10C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x10C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x10C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x110 "LCDC_HCRCLUT68,Hardware Cursor CLUT Register 68 Register"
|
|
hexmask.long.byte 0x110 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x110 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x110 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x110 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x114 "LCDC_HCRCLUT69,Hardware Cursor CLUT Register 69 Register"
|
|
hexmask.long.byte 0x114 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x114 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x114 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x114 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x118 "LCDC_HCRCLUT70,Hardware Cursor CLUT Register 70 Register"
|
|
hexmask.long.byte 0x118 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x118 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x118 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x118 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x11C "LCDC_HCRCLUT71,Hardware Cursor CLUT Register 71 Register"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x11C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x11C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x11C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x120 "LCDC_HCRCLUT72,Hardware Cursor CLUT Register 72 Register"
|
|
hexmask.long.byte 0x120 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x120 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x120 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x120 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x124 "LCDC_HCRCLUT73,Hardware Cursor CLUT Register 73 Register"
|
|
hexmask.long.byte 0x124 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x124 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x124 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x124 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x128 "LCDC_HCRCLUT74,Hardware Cursor CLUT Register 74 Register"
|
|
hexmask.long.byte 0x128 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x128 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x128 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x128 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x12C "LCDC_HCRCLUT75,Hardware Cursor CLUT Register 75 Register"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x12C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x12C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x12C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x130 "LCDC_HCRCLUT76,Hardware Cursor CLUT Register 76 Register"
|
|
hexmask.long.byte 0x130 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x130 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x130 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x130 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x134 "LCDC_HCRCLUT77,Hardware Cursor CLUT Register 77 Register"
|
|
hexmask.long.byte 0x134 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x134 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x134 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x134 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x138 "LCDC_HCRCLUT78,Hardware Cursor CLUT Register 78 Register"
|
|
hexmask.long.byte 0x138 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x138 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x138 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x138 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x13C "LCDC_HCRCLUT79,Hardware Cursor CLUT Register 79 Register"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x13C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x13C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x13C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x140 "LCDC_HCRCLUT80,Hardware Cursor CLUT Register 80 Register"
|
|
hexmask.long.byte 0x140 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x140 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x140 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x140 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x144 "LCDC_HCRCLUT81,Hardware Cursor CLUT Register 81 Register"
|
|
hexmask.long.byte 0x144 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x144 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x144 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x144 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x148 "LCDC_HCRCLUT82,Hardware Cursor CLUT Register 82 Register"
|
|
hexmask.long.byte 0x148 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x148 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x148 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x148 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x14C "LCDC_HCRCLUT83,Hardware Cursor CLUT Register 83 Register"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x14C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x14C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x14C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x150 "LCDC_HCRCLUT84,Hardware Cursor CLUT Register 84 Register"
|
|
hexmask.long.byte 0x150 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x150 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x150 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x150 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x154 "LCDC_HCRCLUT85,Hardware Cursor CLUT Register 85 Register"
|
|
hexmask.long.byte 0x154 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x154 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x154 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x154 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x158 "LCDC_HCRCLUT86,Hardware Cursor CLUT Register 86 Register"
|
|
hexmask.long.byte 0x158 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x158 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x158 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x158 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x15C "LCDC_HCRCLUT87,Hardware Cursor CLUT Register 87 Register"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x15C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x15C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x15C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x160 "LCDC_HCRCLUT88,Hardware Cursor CLUT Register 88 Register"
|
|
hexmask.long.byte 0x160 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x160 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x160 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x160 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x164 "LCDC_HCRCLUT89,Hardware Cursor CLUT Register 89 Register"
|
|
hexmask.long.byte 0x164 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x164 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x164 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x164 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x168 "LCDC_HCRCLUT90,Hardware Cursor CLUT Register 90 Register"
|
|
hexmask.long.byte 0x168 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x168 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x168 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x168 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x16C "LCDC_HCRCLUT91,Hardware Cursor CLUT Register 91 Register"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x16C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x16C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x16C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x170 "LCDC_HCRCLUT92,Hardware Cursor CLUT Register 92 Register"
|
|
hexmask.long.byte 0x170 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x170 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x170 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x170 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x174 "LCDC_HCRCLUT93,Hardware Cursor CLUT Register 93 Register"
|
|
hexmask.long.byte 0x174 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x174 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x174 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x174 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x178 "LCDC_HCRCLUT94,Hardware Cursor CLUT Register 94 Register"
|
|
hexmask.long.byte 0x178 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x178 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x178 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x178 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x17C "LCDC_HCRCLUT95,Hardware Cursor CLUT Register 95 Register"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x17C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x17C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x17C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x180 "LCDC_HCRCLUT96,Hardware Cursor CLUT Register 96 Register"
|
|
hexmask.long.byte 0x180 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x180 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x180 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x180 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x184 "LCDC_HCRCLUT97,Hardware Cursor CLUT Register 97 Register"
|
|
hexmask.long.byte 0x184 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x184 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x184 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x184 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x188 "LCDC_HCRCLUT98,Hardware Cursor CLUT Register 98 Register"
|
|
hexmask.long.byte 0x188 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x188 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x188 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x188 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x18C "LCDC_HCRCLUT99,Hardware Cursor CLUT Register 99 Register"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x18C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x18C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x18C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x190 "LCDC_HCRCLUT100,Hardware Cursor CLUT Register 100 Register"
|
|
hexmask.long.byte 0x190 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x190 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x190 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x190 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x194 "LCDC_HCRCLUT101,Hardware Cursor CLUT Register 101 Register"
|
|
hexmask.long.byte 0x194 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x194 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x194 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x194 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x198 "LCDC_HCRCLUT102,Hardware Cursor CLUT Register 102 Register"
|
|
hexmask.long.byte 0x198 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x198 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x198 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x198 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x19C "LCDC_HCRCLUT103,Hardware Cursor CLUT Register 103 Register"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x19C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x19C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x19C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A0 "LCDC_HCRCLUT104,Hardware Cursor CLUT Register 104 Register"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A4 "LCDC_HCRCLUT105,Hardware Cursor CLUT Register 105 Register"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1A8 "LCDC_HCRCLUT106,Hardware Cursor CLUT Register 106 Register"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1AC "LCDC_HCRCLUT107,Hardware Cursor CLUT Register 107 Register"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B0 "LCDC_HCRCLUT108,Hardware Cursor CLUT Register 108 Register"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B4 "LCDC_HCRCLUT109,Hardware Cursor CLUT Register 109 Register"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1B8 "LCDC_HCRCLUT110,Hardware Cursor CLUT Register 110 Register"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1BC "LCDC_HCRCLUT111,Hardware Cursor CLUT Register 111 Register"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C0 "LCDC_HCRCLUT112,Hardware Cursor CLUT Register 112 Register"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C4 "LCDC_HCRCLUT113,Hardware Cursor CLUT Register 113 Register"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1C8 "LCDC_HCRCLUT114,Hardware Cursor CLUT Register 114 Register"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1CC "LCDC_HCRCLUT115,Hardware Cursor CLUT Register 115 Register"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D0 "LCDC_HCRCLUT116,Hardware Cursor CLUT Register 116 Register"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D4 "LCDC_HCRCLUT117,Hardware Cursor CLUT Register 117 Register"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1D8 "LCDC_HCRCLUT118,Hardware Cursor CLUT Register 118 Register"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1DC "LCDC_HCRCLUT119,Hardware Cursor CLUT Register 119 Register"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E0 "LCDC_HCRCLUT120,Hardware Cursor CLUT Register 120 Register"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E4 "LCDC_HCRCLUT121,Hardware Cursor CLUT Register 121 Register"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1E8 "LCDC_HCRCLUT122,Hardware Cursor CLUT Register 122 Register"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1EC "LCDC_HCRCLUT123,Hardware Cursor CLUT Register 123 Register"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F0 "LCDC_HCRCLUT124,Hardware Cursor CLUT Register 124 Register"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F4 "LCDC_HCRCLUT125,Hardware Cursor CLUT Register 125 Register"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1F8 "LCDC_HCRCLUT126,Hardware Cursor CLUT Register 126 Register"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x1FC "LCDC_HCRCLUT127,Hardware Cursor CLUT Register 127 Register"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x1FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x200 "LCDC_HCRCLUT128,Hardware Cursor CLUT Register 128 Register"
|
|
hexmask.long.byte 0x200 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x200 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x200 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x200 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x204 "LCDC_HCRCLUT129,Hardware Cursor CLUT Register 129 Register"
|
|
hexmask.long.byte 0x204 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x204 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x204 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x204 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x208 "LCDC_HCRCLUT130,Hardware Cursor CLUT Register 130 Register"
|
|
hexmask.long.byte 0x208 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x208 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x208 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x208 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x20C "LCDC_HCRCLUT131,Hardware Cursor CLUT Register 131 Register"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x20C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x20C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x20C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x210 "LCDC_HCRCLUT132,Hardware Cursor CLUT Register 132 Register"
|
|
hexmask.long.byte 0x210 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x210 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x210 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x210 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x214 "LCDC_HCRCLUT133,Hardware Cursor CLUT Register 133 Register"
|
|
hexmask.long.byte 0x214 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x214 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x214 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x214 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x218 "LCDC_HCRCLUT134,Hardware Cursor CLUT Register 134 Register"
|
|
hexmask.long.byte 0x218 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x218 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x218 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x218 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x21C "LCDC_HCRCLUT135,Hardware Cursor CLUT Register 135 Register"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x21C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x21C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x21C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x220 "LCDC_HCRCLUT136,Hardware Cursor CLUT Register 136 Register"
|
|
hexmask.long.byte 0x220 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x220 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x220 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x220 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x224 "LCDC_HCRCLUT137,Hardware Cursor CLUT Register 137 Register"
|
|
hexmask.long.byte 0x224 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x224 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x224 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x224 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x228 "LCDC_HCRCLUT138,Hardware Cursor CLUT Register 138 Register"
|
|
hexmask.long.byte 0x228 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x228 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x228 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x228 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x22C "LCDC_HCRCLUT139,Hardware Cursor CLUT Register 139 Register"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x22C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x22C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x22C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x230 "LCDC_HCRCLUT140,Hardware Cursor CLUT Register 140 Register"
|
|
hexmask.long.byte 0x230 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x230 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x230 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x230 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x234 "LCDC_HCRCLUT141,Hardware Cursor CLUT Register 141 Register"
|
|
hexmask.long.byte 0x234 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x234 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x234 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x234 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x238 "LCDC_HCRCLUT142,Hardware Cursor CLUT Register 142 Register"
|
|
hexmask.long.byte 0x238 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x238 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x238 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x238 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x23C "LCDC_HCRCLUT143,Hardware Cursor CLUT Register 143 Register"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x23C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x23C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x23C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x240 "LCDC_HCRCLUT144,Hardware Cursor CLUT Register 144 Register"
|
|
hexmask.long.byte 0x240 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x240 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x240 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x240 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x244 "LCDC_HCRCLUT145,Hardware Cursor CLUT Register 145 Register"
|
|
hexmask.long.byte 0x244 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x244 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x244 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x244 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x248 "LCDC_HCRCLUT146,Hardware Cursor CLUT Register 146 Register"
|
|
hexmask.long.byte 0x248 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x248 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x248 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x248 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x24C "LCDC_HCRCLUT147,Hardware Cursor CLUT Register 147 Register"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x24C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x24C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x24C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x250 "LCDC_HCRCLUT148,Hardware Cursor CLUT Register 148 Register"
|
|
hexmask.long.byte 0x250 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x250 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x250 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x250 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x254 "LCDC_HCRCLUT149,Hardware Cursor CLUT Register 149 Register"
|
|
hexmask.long.byte 0x254 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x254 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x254 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x254 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x258 "LCDC_HCRCLUT150,Hardware Cursor CLUT Register 150 Register"
|
|
hexmask.long.byte 0x258 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x258 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x258 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x258 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x25C "LCDC_HCRCLUT151,Hardware Cursor CLUT Register 151 Register"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x25C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x25C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x25C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x260 "LCDC_HCRCLUT152,Hardware Cursor CLUT Register 152 Register"
|
|
hexmask.long.byte 0x260 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x260 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x260 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x260 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x264 "LCDC_HCRCLUT153,Hardware Cursor CLUT Register 153 Register"
|
|
hexmask.long.byte 0x264 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x264 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x264 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x264 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x268 "LCDC_HCRCLUT154,Hardware Cursor CLUT Register 154 Register"
|
|
hexmask.long.byte 0x268 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x268 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x268 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x268 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x26C "LCDC_HCRCLUT155,Hardware Cursor CLUT Register 155 Register"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x26C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x26C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x26C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x270 "LCDC_HCRCLUT156,Hardware Cursor CLUT Register 156 Register"
|
|
hexmask.long.byte 0x270 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x270 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x270 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x270 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x274 "LCDC_HCRCLUT157,Hardware Cursor CLUT Register 157 Register"
|
|
hexmask.long.byte 0x274 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x274 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x274 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x274 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x278 "LCDC_HCRCLUT158,Hardware Cursor CLUT Register 158 Register"
|
|
hexmask.long.byte 0x278 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x278 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x278 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x278 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x27C "LCDC_HCRCLUT159,Hardware Cursor CLUT Register 159 Register"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x27C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x27C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x27C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x280 "LCDC_HCRCLUT160,Hardware Cursor CLUT Register 160 Register"
|
|
hexmask.long.byte 0x280 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x280 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x280 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x280 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x284 "LCDC_HCRCLUT161,Hardware Cursor CLUT Register 161 Register"
|
|
hexmask.long.byte 0x284 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x284 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x284 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x284 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x288 "LCDC_HCRCLUT162,Hardware Cursor CLUT Register 162 Register"
|
|
hexmask.long.byte 0x288 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x288 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x288 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x288 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x28C "LCDC_HCRCLUT163,Hardware Cursor CLUT Register 163 Register"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x28C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x28C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x28C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x290 "LCDC_HCRCLUT164,Hardware Cursor CLUT Register 164 Register"
|
|
hexmask.long.byte 0x290 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x290 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x290 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x290 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x294 "LCDC_HCRCLUT165,Hardware Cursor CLUT Register 165 Register"
|
|
hexmask.long.byte 0x294 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x294 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x294 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x294 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x298 "LCDC_HCRCLUT166,Hardware Cursor CLUT Register 166 Register"
|
|
hexmask.long.byte 0x298 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x298 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x298 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x298 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x29C "LCDC_HCRCLUT167,Hardware Cursor CLUT Register 167 Register"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x29C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x29C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x29C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A0 "LCDC_HCRCLUT168,Hardware Cursor CLUT Register 168 Register"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A4 "LCDC_HCRCLUT169,Hardware Cursor CLUT Register 169 Register"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2A8 "LCDC_HCRCLUT170,Hardware Cursor CLUT Register 170 Register"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2AC "LCDC_HCRCLUT171,Hardware Cursor CLUT Register 171 Register"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B0 "LCDC_HCRCLUT172,Hardware Cursor CLUT Register 172 Register"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B4 "LCDC_HCRCLUT173,Hardware Cursor CLUT Register 173 Register"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2B8 "LCDC_HCRCLUT174,Hardware Cursor CLUT Register 174 Register"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2BC "LCDC_HCRCLUT175,Hardware Cursor CLUT Register 175 Register"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C0 "LCDC_HCRCLUT176,Hardware Cursor CLUT Register 176 Register"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C4 "LCDC_HCRCLUT177,Hardware Cursor CLUT Register 177 Register"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2C8 "LCDC_HCRCLUT178,Hardware Cursor CLUT Register 178 Register"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2CC "LCDC_HCRCLUT179,Hardware Cursor CLUT Register 179 Register"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D0 "LCDC_HCRCLUT180,Hardware Cursor CLUT Register 180 Register"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D4 "LCDC_HCRCLUT181,Hardware Cursor CLUT Register 181 Register"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2D8 "LCDC_HCRCLUT182,Hardware Cursor CLUT Register 182 Register"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2DC "LCDC_HCRCLUT183,Hardware Cursor CLUT Register 183 Register"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E0 "LCDC_HCRCLUT184,Hardware Cursor CLUT Register 184 Register"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E4 "LCDC_HCRCLUT185,Hardware Cursor CLUT Register 185 Register"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2E8 "LCDC_HCRCLUT186,Hardware Cursor CLUT Register 186 Register"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2EC "LCDC_HCRCLUT187,Hardware Cursor CLUT Register 187 Register"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F0 "LCDC_HCRCLUT188,Hardware Cursor CLUT Register 188 Register"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F4 "LCDC_HCRCLUT189,Hardware Cursor CLUT Register 189 Register"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2F8 "LCDC_HCRCLUT190,Hardware Cursor CLUT Register 190 Register"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x2FC "LCDC_HCRCLUT191,Hardware Cursor CLUT Register 191 Register"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x2FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x300 "LCDC_HCRCLUT192,Hardware Cursor CLUT Register 192 Register"
|
|
hexmask.long.byte 0x300 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x300 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x300 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x300 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x304 "LCDC_HCRCLUT193,Hardware Cursor CLUT Register 193 Register"
|
|
hexmask.long.byte 0x304 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x304 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x304 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x304 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x308 "LCDC_HCRCLUT194,Hardware Cursor CLUT Register 194 Register"
|
|
hexmask.long.byte 0x308 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x308 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x308 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x308 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x30C "LCDC_HCRCLUT195,Hardware Cursor CLUT Register 195 Register"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x30C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x30C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x30C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x310 "LCDC_HCRCLUT196,Hardware Cursor CLUT Register 196 Register"
|
|
hexmask.long.byte 0x310 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x310 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x310 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x310 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x314 "LCDC_HCRCLUT197,Hardware Cursor CLUT Register 197 Register"
|
|
hexmask.long.byte 0x314 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x314 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x314 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x314 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x318 "LCDC_HCRCLUT198,Hardware Cursor CLUT Register 198 Register"
|
|
hexmask.long.byte 0x318 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x318 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x318 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x318 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x31C "LCDC_HCRCLUT199,Hardware Cursor CLUT Register 199 Register"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x31C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x31C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x31C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x320 "LCDC_HCRCLUT200,Hardware Cursor CLUT Register 200 Register"
|
|
hexmask.long.byte 0x320 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x320 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x320 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x320 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x324 "LCDC_HCRCLUT201,Hardware Cursor CLUT Register 201 Register"
|
|
hexmask.long.byte 0x324 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x324 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x324 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x324 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x328 "LCDC_HCRCLUT202,Hardware Cursor CLUT Register 202 Register"
|
|
hexmask.long.byte 0x328 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x328 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x328 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x328 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x32C "LCDC_HCRCLUT203,Hardware Cursor CLUT Register 203 Register"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x32C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x32C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x32C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x330 "LCDC_HCRCLUT204,Hardware Cursor CLUT Register 204 Register"
|
|
hexmask.long.byte 0x330 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x330 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x330 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x330 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x334 "LCDC_HCRCLUT205,Hardware Cursor CLUT Register 205 Register"
|
|
hexmask.long.byte 0x334 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x334 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x334 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x334 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x338 "LCDC_HCRCLUT206,Hardware Cursor CLUT Register 206 Register"
|
|
hexmask.long.byte 0x338 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x338 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x338 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x338 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x33C "LCDC_HCRCLUT207,Hardware Cursor CLUT Register 207 Register"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x33C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x33C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x33C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x340 "LCDC_HCRCLUT208,Hardware Cursor CLUT Register 208 Register"
|
|
hexmask.long.byte 0x340 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x340 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x340 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x340 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x344 "LCDC_HCRCLUT209,Hardware Cursor CLUT Register 209 Register"
|
|
hexmask.long.byte 0x344 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x344 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x344 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x344 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x348 "LCDC_HCRCLUT210,Hardware Cursor CLUT Register 210 Register"
|
|
hexmask.long.byte 0x348 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x348 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x348 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x348 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x34C "LCDC_HCRCLUT211,Hardware Cursor CLUT Register 211 Register"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x34C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x34C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x34C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x350 "LCDC_HCRCLUT212,Hardware Cursor CLUT Register 212 Register"
|
|
hexmask.long.byte 0x350 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x350 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x350 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x350 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x354 "LCDC_HCRCLUT213,Hardware Cursor CLUT Register 213 Register"
|
|
hexmask.long.byte 0x354 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x354 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x354 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x354 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x358 "LCDC_HCRCLUT214,Hardware Cursor CLUT Register 214 Register"
|
|
hexmask.long.byte 0x358 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x358 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x358 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x358 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x35C "LCDC_HCRCLUT215,Hardware Cursor CLUT Register 215 Register"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x35C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x35C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x35C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x360 "LCDC_HCRCLUT216,Hardware Cursor CLUT Register 216 Register"
|
|
hexmask.long.byte 0x360 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x360 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x360 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x360 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x364 "LCDC_HCRCLUT217,Hardware Cursor CLUT Register 217 Register"
|
|
hexmask.long.byte 0x364 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x364 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x364 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x364 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x368 "LCDC_HCRCLUT218,Hardware Cursor CLUT Register 218 Register"
|
|
hexmask.long.byte 0x368 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x368 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x368 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x368 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x36C "LCDC_HCRCLUT219,Hardware Cursor CLUT Register 219 Register"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x36C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x36C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x36C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x370 "LCDC_HCRCLUT220,Hardware Cursor CLUT Register 220 Register"
|
|
hexmask.long.byte 0x370 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x370 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x370 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x370 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x374 "LCDC_HCRCLUT221,Hardware Cursor CLUT Register 221 Register"
|
|
hexmask.long.byte 0x374 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x374 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x374 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x374 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x378 "LCDC_HCRCLUT222,Hardware Cursor CLUT Register 222 Register"
|
|
hexmask.long.byte 0x378 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x378 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x378 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x378 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x37C "LCDC_HCRCLUT223,Hardware Cursor CLUT Register 223 Register"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x37C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x37C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x37C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x380 "LCDC_HCRCLUT224,Hardware Cursor CLUT Register 224 Register"
|
|
hexmask.long.byte 0x380 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x380 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x380 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x380 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x384 "LCDC_HCRCLUT225,Hardware Cursor CLUT Register 225 Register"
|
|
hexmask.long.byte 0x384 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x384 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x384 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x384 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x388 "LCDC_HCRCLUT226,Hardware Cursor CLUT Register 226 Register"
|
|
hexmask.long.byte 0x388 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x388 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x388 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x388 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x38C "LCDC_HCRCLUT227,Hardware Cursor CLUT Register 227 Register"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x38C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x38C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x38C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x390 "LCDC_HCRCLUT228,Hardware Cursor CLUT Register 228 Register"
|
|
hexmask.long.byte 0x390 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x390 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x390 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x390 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x394 "LCDC_HCRCLUT229,Hardware Cursor CLUT Register 229 Register"
|
|
hexmask.long.byte 0x394 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x394 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x394 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x394 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x398 "LCDC_HCRCLUT230,Hardware Cursor CLUT Register 230 Register"
|
|
hexmask.long.byte 0x398 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x398 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x398 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x398 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x39C "LCDC_HCRCLUT231,Hardware Cursor CLUT Register 231 Register"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x39C 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x39C 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x39C 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A0 "LCDC_HCRCLUT232,Hardware Cursor CLUT Register 232 Register"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A4 "LCDC_HCRCLUT233,Hardware Cursor CLUT Register 233 Register"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3A8 "LCDC_HCRCLUT234,Hardware Cursor CLUT Register 234 Register"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3AC "LCDC_HCRCLUT235,Hardware Cursor CLUT Register 235 Register"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3AC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B0 "LCDC_HCRCLUT236,Hardware Cursor CLUT Register 236 Register"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B4 "LCDC_HCRCLUT237,Hardware Cursor CLUT Register 237 Register"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3B8 "LCDC_HCRCLUT238,Hardware Cursor CLUT Register 238 Register"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3BC "LCDC_HCRCLUT239,Hardware Cursor CLUT Register 239 Register"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3BC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C0 "LCDC_HCRCLUT240,Hardware Cursor CLUT Register 240 Register"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C4 "LCDC_HCRCLUT241,Hardware Cursor CLUT Register 241 Register"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3C8 "LCDC_HCRCLUT242,Hardware Cursor CLUT Register 242 Register"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3CC "LCDC_HCRCLUT243,Hardware Cursor CLUT Register 243 Register"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3CC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D0 "LCDC_HCRCLUT244,Hardware Cursor CLUT Register 244 Register"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D4 "LCDC_HCRCLUT245,Hardware Cursor CLUT Register 245 Register"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3D8 "LCDC_HCRCLUT246,Hardware Cursor CLUT Register 246 Register"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3DC "LCDC_HCRCLUT247,Hardware Cursor CLUT Register 247 Register"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3DC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E0 "LCDC_HCRCLUT248,Hardware Cursor CLUT Register 248 Register"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E4 "LCDC_HCRCLUT249,Hardware Cursor CLUT Register 249 Register"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3E8 "LCDC_HCRCLUT250,Hardware Cursor CLUT Register 250 Register"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3EC "LCDC_HCRCLUT251,Hardware Cursor CLUT Register 251 Register"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3EC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F0 "LCDC_HCRCLUT252,Hardware Cursor CLUT Register 252 Register"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F4 "LCDC_HCRCLUT253,Hardware Cursor CLUT Register 253 Register"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F4 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3F8 "LCDC_HCRCLUT254,Hardware Cursor CLUT Register 254 Register"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
line.long 0x3FC "LCDC_HCRCLUT255,Hardware Cursor CLUT Register 255 Register"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " ACLUT ,Alpha Color entry"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. " RCLUT ,Red Color entry"
|
|
hexmask.long.byte 0x3FC 8.--15. 1. " GCLUT ,Green Color entry"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. " BCLUT ,Blue Color entry"
|
|
tree.end
|
|
rgroup.long 0x1FEC++0x13
|
|
line.long 0x00 "LCDC_ADDRSIZE,Address Size Register"
|
|
line.long 0x04 "LCDC_IPNAME1,IP Name1 Register"
|
|
line.long 0x08 "LCDC_IPNAME2,IP Name2 Register"
|
|
line.long 0x0C "LCDC_FEATURES,Features Register"
|
|
line.long 0x10 "LCDC_VERSION,Version Register"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
textline ""
|