12806 lines
873 KiB
Plaintext
12806 lines
873 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: A34M41x On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-06 JDU
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; 2023-11-02 NEJ
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; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
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; @Doc: Generated (TRACE32, build: 164232.), based on:
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; A34M41x_fixed.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: A34M414RL, A34M414VL, A34M416RL, A34M416VL, A34M418RL,
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; A34M418VL, A34M418YL
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pera34m41x.per 16938 2023-11-07 18:43:11Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (12-bit Analog-to-Digital Converter)"
|
|
base ad:0x0
|
|
tree "ADC0"
|
|
base ad:0x4000B000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MR,ADC Mode Register"
|
|
bitfld.long 0x0 21. "TRGINFO,Trigger Information Option (In external trigger mode)" "0,1"
|
|
bitfld.long 0x0 20. "CHINFO,Channel Information Option" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DMAEN,DMA Enable Bit (only ADCEN=1)" "0: DMA Disable,1: DMA Enable"
|
|
hexmask.long.byte 0x0 12.--16. 1. "STSEL,Sampling Time Selection"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SEQCNT,Number of conversion in a sequence" "0: Single Mode,1: 2 Sequence ADC,2: 3 Sequence ADC,3: 4 Sequence ADC,4: 5 Sequence ADC,5: 6 Sequence ADC,6: 7 Sequence ADC,7: 8 Sequence ADC"
|
|
bitfld.long 0x0 7. "ADEN,ADC Enable Bit" "0: Disable ADC,1: Enable ADC"
|
|
newline
|
|
bitfld.long 0x0 6. "ARST,When sequence is over restart control bit" "0: after ending STOP,1: After ending restart"
|
|
bitfld.long 0x0 4.--5. "ADMOD,ADC Mode Selection Bit" "0: Single_Sequencial Conversion Mode,1: Burst Conversion Mode,2: Multiple Conversion Mode,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRGSEL,Trigger Selection Bit" "0: Software Trigger Only,1: TIMER event trigger,2: MPWM0 Event Trigger,3: MPWM1 Event Trigger"
|
|
line.long 0x4 "CSCR,ADC Current Sequence_Channel Register"
|
|
bitfld.long 0x4 8.--10. "CSEQN,Current Sequence Number" "0: Current Sequence 0,1: Current Sequence 1,2: Current Sequence 2,3: Current Sequence 3,4: Current Sequence 4,5: Current Sequence 5,6: Current Sequence 6,7: Current Sequence 7"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CACH,Current Active Channel"
|
|
line.long 0x8 "CCR,ADC Clock Control Register"
|
|
bitfld.long 0x8 15. "ADCPDA,ADC R DAC disable to save power (optional bit)" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC Clock Divider value bit ADC CLK = ADC Input Clock / CLKDIV (CLKDIV=1 ADC Stop CLKDIV=0 ADC Input Clock)"
|
|
newline
|
|
bitfld.long 0x8 7. "ADCPD,ADC Deep Sleep" "0: ADC Normal Mode,1: ADC Deep Sleep Mode"
|
|
bitfld.long 0x8 6. "EXTCLK,ADC External Clock Setting Bit" "0: ADC Internal Clock (CLKDIV Enable),1: ADC External Clock (SCU Clock)"
|
|
newline
|
|
bitfld.long 0x8 5. "CLKINVT,Divide Clock Inversion (Option bit)" "0: duty ratio of divided clock is larger than 50p,1: duty ratio of divided clock is less than 50p"
|
|
line.long 0xC "TRG,ADC Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,Sequence Trigger Source 8th"
|
|
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,Sequence Trigger Source 7th"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,Sequence Trigger Source 6th"
|
|
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,Sequence Trigger Source 5th"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,Sequence Trigger Source 4th"
|
|
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,Sequence Trigger Source 3th"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,Sequence Trigger Source 2th"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0_BSTTRG,Sequence Trigger Source 1th Burst Conversion Trigger Source"
|
|
group.long 0x18++0x13
|
|
line.long 0x0 "SCSR1,ADC Channel Selection Register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SEQ3CH,Conversion Sequence Channel Selection 4th"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SEQ2CH,Conversion Sequence Channel Selection 3th"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "SEQ1CH,Conversion Sequence Channel Selection 2th"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEQ0CH,Conversion Sequence Channel Selection 1th"
|
|
line.long 0x4 "SCSR2,ADC Channel Selection Register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SEQ7CH,Conversion Sequence Channel Selection 8th"
|
|
hexmask.long.byte 0x4 16.--20. 1. "SEQ6CH,Conversion Sequence Channel Selection 7th"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "SEQ5CH,Conversion Sequence Channel Selection 6th"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEQ4CH,Conversion Sequence Channel Selection 5th"
|
|
line.long 0x8 "CR,ADC Control Register"
|
|
bitfld.long 0x8 7. "ASTOP,ADC STOP bit" "0,1"
|
|
bitfld.long 0x8 1. "TRGCLR,ADC all trigger flags cleared option (previous ADC operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ASTART,ADC START Bit" "0,1"
|
|
line.long 0xC "SR,ADC Status Register"
|
|
bitfld.long 0xC 8. "COMPIFLG,Compare Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0xC 7. "EOC,End of ADC Conversion Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 6. "ABUSY,ADC Busy Flag" "0,1"
|
|
rbitfld.long 0xC 5. "DOVRUN,DMA Overrun Flag (Not Interrupt)" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 4. "DMAIF,DMA Done Received Flag (DMA transfer is completed)" "0,1"
|
|
bitfld.long 0xC 3. "TRGIF,ADC Trigger Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EOSIF,Sequence End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
bitfld.long 0xC 0. "EOCIF,Sequence Conversion End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
line.long 0x10 "IER,ADC Interrupt Enable Register"
|
|
bitfld.long 0x10 4. "DMAIE,DMA Done Interrupt Enable" "0: DMA Interrupt Disable,1: DMA Interrupt Enable"
|
|
bitfld.long 0x10 3. "TRGIE,ADC Trigger Conversion Interrupt Enable" "0: ADC Trigger Conversion Interrupt Disable,1: ADC Trigger Conversion Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "EOSIE,ADC Sequence Conversion Interrupt Enable" "0: ADC Sequence Conversion Interrupt Disable,1: ADC Sequence Conversion Interrupt Enable"
|
|
bitfld.long 0x10 0. "EOCIE,ADC Single Conversion Interrupt Enable" "0: ADC Single Conversion Interrupt Disable,1: ADC Single Conversion Interrupt Enable"
|
|
rgroup.long 0x2C++0x23
|
|
line.long 0x0 "DDR,ADC DMA Data Register"
|
|
bitfld.long 0x0 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "ADMACH,ADC Data Channel Indicator"
|
|
hexmask.long.word 0x0 4.--15. 1. "ADDMAR,ADC Conversion Result Data (12-bit)"
|
|
line.long 0x4 "DR0,ADC Sequence Data Register0"
|
|
bitfld.long 0x4 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x4 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x8 "DR1,ADC Sequence Data Register1"
|
|
bitfld.long 0x8 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x8 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0xC "DR2,ADC Sequence Data Register2"
|
|
bitfld.long 0xC 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0xC 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x10 "DR3,ADC Sequence Data Register3"
|
|
bitfld.long 0x10 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x10 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x14 "DR4,ADC Sequence Data Register4"
|
|
bitfld.long 0x14 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x14 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x18 "DR5,ADC Sequence Data Register5"
|
|
bitfld.long 0x18 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x18 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x1C "DR6,ADC Sequence Data Register6"
|
|
bitfld.long 0x1C 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x1C 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x20 "DR7,ADC Sequence Data Register7"
|
|
bitfld.long 0x20 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x20 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CMPR,ADC Channel Compare Register"
|
|
bitfld.long 0x0 24. "COMPIEN,Compare Interrupt Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
bitfld.long 0x0 23. "COMPEN,Compare Operation Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
newline
|
|
bitfld.long 0x0 21. "LTE,AD Conversion Value Output Timing Setting" "0: If ADC value is higher than CVAL value output.,1: If the ADC value is lower than the CVAL value it.."
|
|
hexmask.long.byte 0x0 16.--20. 1. "CCH,Compare Channel"
|
|
newline
|
|
hexmask.long.word 0x0 4.--15. 1. "CVAL,Compare Value"
|
|
tree.end
|
|
tree "ADC1"
|
|
base ad:0x4000B100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MR,ADC Mode Register"
|
|
bitfld.long 0x0 21. "TRGINFO,Trigger Information Option (In external trigger mode)" "0,1"
|
|
bitfld.long 0x0 20. "CHINFO,Channel Information Option" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DMAEN,DMA Enable Bit (only ADCEN=1)" "0: DMA Disable,1: DMA Enable"
|
|
hexmask.long.byte 0x0 12.--16. 1. "STSEL,Sampling Time Selection"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SEQCNT,Number of conversion in a sequence" "0: Single Mode,1: 2 Sequence ADC,2: 3 Sequence ADC,3: 4 Sequence ADC,4: 5 Sequence ADC,5: 6 Sequence ADC,6: 7 Sequence ADC,7: 8 Sequence ADC"
|
|
bitfld.long 0x0 7. "ADEN,ADC Enable Bit" "0: Disable ADC,1: Enable ADC"
|
|
newline
|
|
bitfld.long 0x0 6. "ARST,When sequence is over restart control bit" "0: after ending STOP,1: After ending restart"
|
|
bitfld.long 0x0 4.--5. "ADMOD,ADC Mode Selection Bit" "0: Single_Sequencial Conversion Mode,1: Burst Conversion Mode,2: Multiple Conversion Mode,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRGSEL,Trigger Selection Bit" "0: Software Trigger Only,1: TIMER event trigger,2: MPWM0 Event Trigger,3: MPWM1 Event Trigger"
|
|
line.long 0x4 "CSCR,ADC Current Sequence_Channel Register"
|
|
bitfld.long 0x4 8.--10. "CSEQN,Current Sequence Number" "0: Current Sequence 0,1: Current Sequence 1,2: Current Sequence 2,3: Current Sequence 3,4: Current Sequence 4,5: Current Sequence 5,6: Current Sequence 6,7: Current Sequence 7"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CACH,Current Active Channel"
|
|
line.long 0x8 "CCR,ADC Clock Control Register"
|
|
bitfld.long 0x8 15. "ADCPDA,ADC R DAC disable to save power (optional bit)" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC Clock Divider value bit ADC CLK = ADC Input Clock / CLKDIV (CLKDIV=1 ADC Stop CLKDIV=0 ADC Input Clock)"
|
|
newline
|
|
bitfld.long 0x8 7. "ADCPD,ADC Deep Sleep" "0: ADC Normal Mode,1: ADC Deep Sleep Mode"
|
|
bitfld.long 0x8 6. "EXTCLK,ADC External Clock Setting Bit" "0: ADC Internal Clock (CLKDIV Enable),1: ADC External Clock (SCU Clock)"
|
|
newline
|
|
bitfld.long 0x8 5. "CLKINVT,Divide Clock Inversion (Option bit)" "0: duty ratio of divided clock is larger than 50p,1: duty ratio of divided clock is less than 50p"
|
|
line.long 0xC "TRG,ADC Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,Sequence Trigger Source 8th"
|
|
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,Sequence Trigger Source 7th"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,Sequence Trigger Source 6th"
|
|
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,Sequence Trigger Source 5th"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,Sequence Trigger Source 4th"
|
|
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,Sequence Trigger Source 3th"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,Sequence Trigger Source 2th"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0_BSTTRG,Sequence Trigger Source 1th Burst Conversion Trigger Source"
|
|
group.long 0x18++0x13
|
|
line.long 0x0 "SCSR1,ADC Channel Selection Register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SEQ3CH,Conversion Sequence Channel Selection 4th"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SEQ2CH,Conversion Sequence Channel Selection 3th"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "SEQ1CH,Conversion Sequence Channel Selection 2th"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEQ0CH,Conversion Sequence Channel Selection 1th"
|
|
line.long 0x4 "SCSR2,ADC Channel Selection Register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SEQ7CH,Conversion Sequence Channel Selection 8th"
|
|
hexmask.long.byte 0x4 16.--20. 1. "SEQ6CH,Conversion Sequence Channel Selection 7th"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "SEQ5CH,Conversion Sequence Channel Selection 6th"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEQ4CH,Conversion Sequence Channel Selection 5th"
|
|
line.long 0x8 "CR,ADC Control Register"
|
|
bitfld.long 0x8 7. "ASTOP,ADC STOP bit" "0,1"
|
|
bitfld.long 0x8 1. "TRGCLR,ADC all trigger flags cleared option (previous ADC operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ASTART,ADC START Bit" "0,1"
|
|
line.long 0xC "SR,ADC Status Register"
|
|
bitfld.long 0xC 8. "COMPIFLG,Compare Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0xC 7. "EOC,End of ADC Conversion Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 6. "ABUSY,ADC Busy Flag" "0,1"
|
|
rbitfld.long 0xC 5. "DOVRUN,DMA Overrun Flag (Not Interrupt)" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 4. "DMAIF,DMA Done Received Flag (DMA transfer is completed)" "0,1"
|
|
bitfld.long 0xC 3. "TRGIF,ADC Trigger Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EOSIF,Sequence End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
bitfld.long 0xC 0. "EOCIF,Sequence Conversion End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
line.long 0x10 "IER,ADC Interrupt Enable Register"
|
|
bitfld.long 0x10 4. "DMAIE,DMA Done Interrupt Enable" "0: DMA Interrupt Disable,1: DMA Interrupt Enable"
|
|
bitfld.long 0x10 3. "TRGIE,ADC Trigger Conversion Interrupt Enable" "0: ADC Trigger Conversion Interrupt Disable,1: ADC Trigger Conversion Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "EOSIE,ADC Sequence Conversion Interrupt Enable" "0: ADC Sequence Conversion Interrupt Disable,1: ADC Sequence Conversion Interrupt Enable"
|
|
bitfld.long 0x10 0. "EOCIE,ADC Single Conversion Interrupt Enable" "0: ADC Single Conversion Interrupt Disable,1: ADC Single Conversion Interrupt Enable"
|
|
rgroup.long 0x2C++0x23
|
|
line.long 0x0 "DDR,ADC DMA Data Register"
|
|
bitfld.long 0x0 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "ADMACH,ADC Data Channel Indicator"
|
|
hexmask.long.word 0x0 4.--15. 1. "ADDMAR,ADC Conversion Result Data (12-bit)"
|
|
line.long 0x4 "DR0,ADC Sequence Data Register0"
|
|
bitfld.long 0x4 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x4 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x8 "DR1,ADC Sequence Data Register1"
|
|
bitfld.long 0x8 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x8 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0xC "DR2,ADC Sequence Data Register2"
|
|
bitfld.long 0xC 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0xC 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x10 "DR3,ADC Sequence Data Register3"
|
|
bitfld.long 0x10 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x10 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x14 "DR4,ADC Sequence Data Register4"
|
|
bitfld.long 0x14 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x14 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x18 "DR5,ADC Sequence Data Register5"
|
|
bitfld.long 0x18 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x18 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x1C "DR6,ADC Sequence Data Register6"
|
|
bitfld.long 0x1C 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x1C 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x20 "DR7,ADC Sequence Data Register7"
|
|
bitfld.long 0x20 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x20 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CMPR,ADC Channel Compare Register"
|
|
bitfld.long 0x0 24. "COMPIEN,Compare Interrupt Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
bitfld.long 0x0 23. "COMPEN,Compare Operation Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
newline
|
|
bitfld.long 0x0 21. "LTE,AD Conversion Value Output Timing Setting" "0: If ADC value is higher than CVAL value output.,1: If the ADC value is lower than the CVAL value it.."
|
|
hexmask.long.byte 0x0 16.--20. 1. "CCH,Compare Channel"
|
|
newline
|
|
hexmask.long.word 0x0 4.--15. 1. "CVAL,Compare Value"
|
|
tree.end
|
|
tree "ADC2"
|
|
base ad:0x4000B200
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MR,ADC Mode Register"
|
|
bitfld.long 0x0 21. "TRGINFO,Trigger Information Option (In external trigger mode)" "0,1"
|
|
bitfld.long 0x0 20. "CHINFO,Channel Information Option" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DMAEN,DMA Enable Bit (only ADCEN=1)" "0: DMA Disable,1: DMA Enable"
|
|
hexmask.long.byte 0x0 12.--16. 1. "STSEL,Sampling Time Selection"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SEQCNT,Number of conversion in a sequence" "0: Single Mode,1: 2 Sequence ADC,2: 3 Sequence ADC,3: 4 Sequence ADC,4: 5 Sequence ADC,5: 6 Sequence ADC,6: 7 Sequence ADC,7: 8 Sequence ADC"
|
|
bitfld.long 0x0 7. "ADEN,ADC Enable Bit" "0: Disable ADC,1: Enable ADC"
|
|
newline
|
|
bitfld.long 0x0 6. "ARST,When sequence is over restart control bit" "0: after ending STOP,1: After ending restart"
|
|
bitfld.long 0x0 4.--5. "ADMOD,ADC Mode Selection Bit" "0: Single_Sequencial Conversion Mode,1: Burst Conversion Mode,2: Multiple Conversion Mode,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRGSEL,Trigger Selection Bit" "0: Software Trigger Only,1: TIMER event trigger,2: MPWM0 Event Trigger,3: MPWM1 Event Trigger"
|
|
line.long 0x4 "CSCR,ADC Current Sequence_Channel Register"
|
|
bitfld.long 0x4 8.--10. "CSEQN,Current Sequence Number" "0: Current Sequence 0,1: Current Sequence 1,2: Current Sequence 2,3: Current Sequence 3,4: Current Sequence 4,5: Current Sequence 5,6: Current Sequence 6,7: Current Sequence 7"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CACH,Current Active Channel"
|
|
line.long 0x8 "CCR,ADC Clock Control Register"
|
|
bitfld.long 0x8 15. "ADCPDA,ADC R DAC disable to save power (optional bit)" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC Clock Divider value bit ADC CLK = ADC Input Clock / CLKDIV (CLKDIV=1 ADC Stop CLKDIV=0 ADC Input Clock)"
|
|
newline
|
|
bitfld.long 0x8 7. "ADCPD,ADC Deep Sleep" "0: ADC Normal Mode,1: ADC Deep Sleep Mode"
|
|
bitfld.long 0x8 6. "EXTCLK,ADC External Clock Setting Bit" "0: ADC Internal Clock (CLKDIV Enable),1: ADC External Clock (SCU Clock)"
|
|
newline
|
|
bitfld.long 0x8 5. "CLKINVT,Divide Clock Inversion (Option bit)" "0: duty ratio of divided clock is larger than 50p,1: duty ratio of divided clock is less than 50p"
|
|
line.long 0xC "TRG,ADC Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,Sequence Trigger Source 8th"
|
|
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,Sequence Trigger Source 7th"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,Sequence Trigger Source 6th"
|
|
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,Sequence Trigger Source 5th"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,Sequence Trigger Source 4th"
|
|
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,Sequence Trigger Source 3th"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,Sequence Trigger Source 2th"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0_BSTTRG,Sequence Trigger Source 1th Burst Conversion Trigger Source"
|
|
group.long 0x18++0x13
|
|
line.long 0x0 "SCSR1,ADC Channel Selection Register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SEQ3CH,Conversion Sequence Channel Selection 4th"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SEQ2CH,Conversion Sequence Channel Selection 3th"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "SEQ1CH,Conversion Sequence Channel Selection 2th"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEQ0CH,Conversion Sequence Channel Selection 1th"
|
|
line.long 0x4 "SCSR2,ADC Channel Selection Register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SEQ7CH,Conversion Sequence Channel Selection 8th"
|
|
hexmask.long.byte 0x4 16.--20. 1. "SEQ6CH,Conversion Sequence Channel Selection 7th"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "SEQ5CH,Conversion Sequence Channel Selection 6th"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEQ4CH,Conversion Sequence Channel Selection 5th"
|
|
line.long 0x8 "CR,ADC Control Register"
|
|
bitfld.long 0x8 7. "ASTOP,ADC STOP bit" "0,1"
|
|
bitfld.long 0x8 1. "TRGCLR,ADC all trigger flags cleared option (previous ADC operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ASTART,ADC START Bit" "0,1"
|
|
line.long 0xC "SR,ADC Status Register"
|
|
bitfld.long 0xC 8. "COMPIFLG,Compare Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0xC 7. "EOC,End of ADC Conversion Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 6. "ABUSY,ADC Busy Flag" "0,1"
|
|
rbitfld.long 0xC 5. "DOVRUN,DMA Overrun Flag (Not Interrupt)" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 4. "DMAIF,DMA Done Received Flag (DMA transfer is completed)" "0,1"
|
|
bitfld.long 0xC 3. "TRGIF,ADC Trigger Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EOSIF,Sequence End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
bitfld.long 0xC 0. "EOCIF,Sequence Conversion End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
line.long 0x10 "IER,ADC Interrupt Enable Register"
|
|
bitfld.long 0x10 4. "DMAIE,DMA Done Interrupt Enable" "0: DMA Interrupt Disable,1: DMA Interrupt Enable"
|
|
bitfld.long 0x10 3. "TRGIE,ADC Trigger Conversion Interrupt Enable" "0: ADC Trigger Conversion Interrupt Disable,1: ADC Trigger Conversion Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "EOSIE,ADC Sequence Conversion Interrupt Enable" "0: ADC Sequence Conversion Interrupt Disable,1: ADC Sequence Conversion Interrupt Enable"
|
|
bitfld.long 0x10 0. "EOCIE,ADC Single Conversion Interrupt Enable" "0: ADC Single Conversion Interrupt Disable,1: ADC Single Conversion Interrupt Enable"
|
|
rgroup.long 0x2C++0x23
|
|
line.long 0x0 "DDR,ADC DMA Data Register"
|
|
bitfld.long 0x0 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "ADMACH,ADC Data Channel Indicator"
|
|
hexmask.long.word 0x0 4.--15. 1. "ADDMAR,ADC Conversion Result Data (12-bit)"
|
|
line.long 0x4 "DR0,ADC Sequence Data Register0"
|
|
bitfld.long 0x4 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x4 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x8 "DR1,ADC Sequence Data Register1"
|
|
bitfld.long 0x8 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x8 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0xC "DR2,ADC Sequence Data Register2"
|
|
bitfld.long 0xC 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0xC 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x10 "DR3,ADC Sequence Data Register3"
|
|
bitfld.long 0x10 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x10 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x14 "DR4,ADC Sequence Data Register4"
|
|
bitfld.long 0x14 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x14 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x18 "DR5,ADC Sequence Data Register5"
|
|
bitfld.long 0x18 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x18 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x1C "DR6,ADC Sequence Data Register6"
|
|
bitfld.long 0x1C 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x1C 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x20 "DR7,ADC Sequence Data Register7"
|
|
bitfld.long 0x20 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x20 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CMPR,ADC Channel Compare Register"
|
|
bitfld.long 0x0 24. "COMPIEN,Compare Interrupt Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
bitfld.long 0x0 23. "COMPEN,Compare Operation Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
newline
|
|
bitfld.long 0x0 21. "LTE,AD Conversion Value Output Timing Setting" "0: If ADC value is higher than CVAL value output.,1: If the ADC value is lower than the CVAL value it.."
|
|
hexmask.long.byte 0x0 16.--20. 1. "CCH,Compare Channel"
|
|
newline
|
|
hexmask.long.word 0x0 4.--15. 1. "CVAL,Compare Value"
|
|
tree.end
|
|
tree.end
|
|
tree "AES-128 (Advanced Encryption Standard-128)"
|
|
base ad:0x40000500
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,AES Control Register"
|
|
bitfld.long 0x0 19. "DMAINIE,AES DMA Input Complete Interrupt Enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 18. "DMAOUTIE,AES DMA Output Complete Interrupt Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 17. "INVCIPHERIE,AES Inverse Cipher Mode Complete Interrupt Enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "CIPHERIE,AES Cipher Mode Complete Interrupt Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 9. "OUTFIFOFLUSH,AES Output FIFO Erase Bit(Auto Clear)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 8. "INFIFOFLUSH,AES Input FIFO Erase Bit(Auto Clear)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "TOINVMD,AES TEXT OUT Arrange Mode Setting Bit" "0: Default WORD Row(LSB),1: WORD Inverse Mode(MSB),2: BYTE Inverse in WORD Mode(MSB),?,4: BYTE Inverse Mode(MSB),?,?,?"
|
|
bitfld.long 0x0 2.--4. "TIINVMD,AES TEXT IN Arrange Mode Setting Bit" "0: Default WORD Row(LSB),1: WORD Inverse Mode(MSB),2: BYTE Inverse in WORD Mode(MSB),?,4: BYTE Inverse Mode(MSB),?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE,AES Mode Selection Bit" "?,1: Cipher Mode,2: Inverse Cipher Mode,?"
|
|
line.long 0x4 "STAT,AES Status Register"
|
|
rbitfld.long 0x4 19. "DMAINRS,AES DMA Input Complete Status Bit(Raw data)" "0,1"
|
|
rbitfld.long 0x4 18. "DMAOUTRS,AES DMA Output Complete Status Bit(Raw data)" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 17. "INVCIPDRS,AES DMA Input Complete Status Bit(Raw data)" "0,1"
|
|
rbitfld.long 0x4 16. "CIPDRS,AES DMA Input Complete Status Bit(Raw data)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAIN,AES DMA Input Complete Flag Bit" "0: Not Complete,1: Inverse Ciper Done (to clear write '1')"
|
|
bitfld.long 0x4 2. "DMAOUT,AES DMA Output Complete Flag Bit" "0: Not Complete,1: Inverse Ciper Done (to clear write '1')"
|
|
newline
|
|
bitfld.long 0x4 1. "INVCIPDONE,AES Inverse Cipher Done Flag Bit" "0: Not Complete,1: Inverse Ciper Done (to clear write '1')"
|
|
bitfld.long 0x4 0. "CIPDONE,AES Cipher Done Flag Bit" "0: Not Complete,1: Ciper Done (to clear write '1')"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "INFIFO,AES Input FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "TEXTIN,TEST IN FIFO Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "OUTFIFO,AES Output FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "TEXTOUT,TEST OUT FIFO Register"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "KEYIN0,AES KEY IN Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEYIND0,KEY IN Value Register 0"
|
|
line.long 0x4 "KEYIN1,AES KEY IN Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEYIND1,KEY IN Value Register 1"
|
|
line.long 0x8 "KEYIN2,AES KEY IN Register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEYIND2,KEY IN Value Register 2"
|
|
line.long 0xC "KEYIN3,AES KEY IN Register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEYIND3,KEY IN Value Register 3"
|
|
rgroup.long 0x20++0x1F
|
|
line.long 0x0 "TEXTIN0,AES TEXT IN 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "TEXTIN0,TEST IN Value Register"
|
|
line.long 0x4 "TEXTIN1,AES TEXT IN 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "TEXTIN1,TEST IN Value Register"
|
|
line.long 0x8 "TEXTIN2,AES TEXT IN 2 Register"
|
|
hexmask.long 0x8 0.--31. 1. "TEXTIN2,TEST IN Value Register"
|
|
line.long 0xC "TEXTIN3,AES TEXT IN 3 Register"
|
|
hexmask.long 0xC 0.--31. 1. "TEXTIN3,TEST IN Value Register"
|
|
line.long 0x10 "TEXTOUT0,AES TEXT OUT Register 0"
|
|
hexmask.long 0x10 0.--31. 1. "OUTD0,TEXT OUT Value Bit"
|
|
line.long 0x14 "TEXTOUT1,AES TEXT OUT Register 1"
|
|
hexmask.long 0x14 0.--31. 1. "OUTD1,TEXT OUT Value Bit"
|
|
line.long 0x18 "TEXTOUT2,AES TEXT OUT Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "OUTD2,TEXT OUT Value Bit"
|
|
line.long 0x1C "TEXTOUT3,AES TEXT OUT Register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTD3,TEXT OUT Value Bit"
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,CAN Control Register"
|
|
bitfld.long 0x0 7. "TEST,Test Mode Enable Bit" "0: Normal Mode,1: Test Mode"
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DAR,Automatic Re-transmit Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 1. "IE,CAN Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "INIT,Internal Initialization Pending" "0: Normal Operation,1: Initialization is started"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "SR,CAN Status Register"
|
|
rbitfld.long 0x0 7. "BOFF,Bus Off Status" "0,1"
|
|
rbitfld.long 0x0 6. "EWARN,Error Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EPASS,Error Passive" "0,1"
|
|
rbitfld.long 0x0 4. "RXOK,Received a Message Successfully" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "TXOK,Transmitted a Message Successfully" "0,1"
|
|
rbitfld.long 0x0 0.--2. "LEC,Last Error Code" "0: No Error,1: Stuff Error,2: Form Error,3: Acknowledgment Error,4: Bit1 Error,5: Bit0 Error,6: CRC Error,?"
|
|
line.long 0x4 "ERRCNT,CAN Error Counter Register"
|
|
bitfld.long 0x4 15. "REP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "REC,Receive Error Count"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEC,Transmit Error Count"
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x0 12.--14. "TSEG2,Timing Segment 2" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSEG1,Timing Segment 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "SWJ,Synchronous Width Jump" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler"
|
|
line.long 0x4 "IER,CAN Interrupt Enable Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTID,Interrupt Identifier"
|
|
line.long 0x8 "TEST,CAN Test Register"
|
|
rbitfld.long 0x8 7. "RX,Monitors the actual value of the CAN_RX Pin" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of CAN_TX Pin" "0: Reset Value CAN_TX is controlled by the CAN Core,1: Sample Point cna be monitored at CAN_TX Pin,2: CAN_TX pin drivers a dominant('0') value,3: CAN_TX pin drivers a recessive('1') value"
|
|
newline
|
|
bitfld.long 0x8 4. "LB,Loop Back Mode (Receiving its own transmission)" "0: Disable,1: Enable"
|
|
bitfld.long 0x8 3. "SILENT,Silent Mode (Never Send Dominant Bits)" "0: Normal Mode,1: Silent Mode"
|
|
newline
|
|
bitfld.long 0x8 2. "BASIC,Basic Mode (Message RAM is not abailable)" "0: regular mode (message RAM is used as transmit..,1: IF1 register are used as transmit buffers and.."
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BRPEXT,CAN BRP Extend Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BRPE,Baud Rate"
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "EN,CAN Enable Register"
|
|
bitfld.long 0x0 0. "EN,CAN Module Enable Bit" "0,1"
|
|
line.long 0x4 "I1COMR,CAN Interface 1 Command Request Register"
|
|
bitfld.long 0x4 15. "BUSY,Busy Flag (Write Access Only When Busy = '0')" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "MSGNUM,Message Number"
|
|
line.long 0x8 "I1COMM,CAN Interface1 Command Mask Register"
|
|
bitfld.long 0x8 7. "WR_RD,Write/Read" "0: Read Data From the Message Object addressed by..,1: Write data from the selected interface register.."
|
|
bitfld.long 0x8 6. "MASK,Access interface X Mask Bits" "0: Mask Bits unchanged,1: read/write identifier mask + Mdir + MXtd"
|
|
newline
|
|
bitfld.long 0x8 5. "ARB,Access Interface X Arbitration" "0: Arbitration bits unchanged,1: read/write identifier mask + Mdir + MXtd"
|
|
bitfld.long 0x8 4. "CONTROL,Access Interface X Message Control Bits" "0: control Bits unchanged,1: read/write conrol bits"
|
|
newline
|
|
bitfld.long 0x8 3. "CLTPND,Clear(Reset) Interface X Clear Interrupt Pending" "0: Interrupt Pending Bit remains unchanged when..,1: Clear Interrupt pending bit when reading the.."
|
|
bitfld.long 0x8 2. "TXRQST_ND,Write(TXRQST) - Access transmission request / read(ND) - New Data Bit" "0: Write - Tx Request bit unchanged / Read - New..,1: Write - Set Tx Request Bit / Read - Reset NewDat.."
|
|
newline
|
|
bitfld.long 0x8 1. "DATAA,Access Data Byte 0-3" "0: Data Byte 0-3 Unchanged,1: Read/Write Data Byte 0-3"
|
|
bitfld.long 0x8 0. "DATAB,Access Data Byte 4-7" "0: Data Byte 4-7 Unchanged,1: Read/Write Data Byte 4-7"
|
|
line.long 0xC "I1MSK1,CAN Interface1 Mask1 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "MSK1,Identifier Mask Standard Message"
|
|
line.long 0x10 "I1MSK2,CAN Interface1 Mask2 Register"
|
|
bitfld.long 0x10 15. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x10 14. "Mdir,Mask Message Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "MSK28,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 11. "MSK27,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "MSK26,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 9. "MSK25,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "MSK24,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 7. "MSK23,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "MSK22,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 5. "MSK21,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "MSK20,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 3. "MSK19,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "MSK18,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0x10 1. "MSK17,Identifier Mask Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "MSK16,Identifier Mask Extended Message" "0,1"
|
|
line.long 0x14 "I1ARB1,CAN Interface1 Arbitration1 Register"
|
|
bitfld.long 0x14 15. "ID15,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 14. "ID14,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "ID13,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 12. "ID12,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "ID11,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 10. "ID10,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "ID9,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 8. "ID8,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "ID7,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 6. "ID6,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "ID5,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 4. "ID4,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "ID3,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 2. "ID2,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "ID1,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 0. "ID0,Identifier Extended Message" "0,1"
|
|
line.long 0x18 "I1ARB2,CAN Interface1 Arbitration2 Register"
|
|
bitfld.long 0x18 15. "MSGV,Message Validation" "0,1"
|
|
bitfld.long 0x18 14. "Xtd,Extended Identifier" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "Dir,Message Direction" "0,1"
|
|
bitfld.long 0x18 12. "ID28,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "ID27,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x18 10. "ID26,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "ID25,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x18 8. "ID24,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "ID23,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x18 6. "ID22,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "ID21,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x18 4. "ID20,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "ID19,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x18 2. "ID18,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "ID17,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x18 0. "ID16,Identifier Extended Message" "0,1"
|
|
line.long 0x1C "I1MCR,CAN Interface1 Message Control Register"
|
|
bitfld.long 0x1C 15. "NEWDAT,New Data" "0,1"
|
|
bitfld.long 0x1C 14. "MSGLST,Message Lost(Only valid for direction = receive)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "INTPND,Interrupt Pending" "0,1"
|
|
bitfld.long 0x1C 12. "UMASK,Use Identifier Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "TXIE,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 10. "RXIE,Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "RMTEN,Remote Enable" "0,1"
|
|
bitfld.long 0x1C 8. "TXRQST,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "EOB,End of Buffer (For normal Operation This bit must be set to one)" "0,1"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "DLC,Data Length Code Number of Data Bytes"
|
|
line.long 0x20 "I1DA1,CAN Interface1 Data A1 Register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DATA1,DATA1 : Shifter Register Byte 1"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DATA0,DATA0 : Shifter Register Byte 0"
|
|
line.long 0x24 "I1DA2,CAN Interface1 Data A2 Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DATA3,DATA3 : Shifter Register Byte 3"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DATA2,DATA2 : Shifter Register Byte 2"
|
|
line.long 0x28 "I1DB1,CAN Interface1 Data B1 Register"
|
|
hexmask.long.byte 0x28 8.--15. 1. "DATA5,DATA5 : Shifter Register Byte 5"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DATA4,DATA4 : Shifter Register Byte 4"
|
|
line.long 0x2C "I1DB2,CAN Interface1 Data B2 Register"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "DATA7,DATA7 : Shifter Register Byte 7"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "DATA6,DATA6 : Shifter Register Byte 6"
|
|
group.long 0x80++0x2B
|
|
line.long 0x0 "I2COMR,CAN Interface 2 Command Request Register"
|
|
bitfld.long 0x0 15. "BUSY,Busy Flag (Write Access Only When Busy = '0')" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MSGNUM,Message Number"
|
|
line.long 0x4 "I2COMM,CAN Interface2 Command Mask Register"
|
|
bitfld.long 0x4 7. "WR_RD,Write/Read" "0: Read Data From the Message Object addressed by..,1: Write data from the selected interface register.."
|
|
bitfld.long 0x4 6. "MASK,Access interface X Mask Bits" "0: Mask Bits unchanged,1: read/write identifier mask + Mdir + MXtd"
|
|
newline
|
|
bitfld.long 0x4 5. "ARB,Access Interface X Arbitration" "0: Arbitration bits unchanged,1: read/write identifier mask + Mdir + MXtd"
|
|
bitfld.long 0x4 4. "CONTROL,Access Interface X Message Control Bits" "0: control Bits unchanged,1: read/write conrol bits"
|
|
newline
|
|
bitfld.long 0x4 3. "CLTPND,Clear(Reset) Interface X Clear Interrupt Pending" "0: Interrupt Pending Bit remains unchanged when..,1: Clear Interrupt pending bit when reading the.."
|
|
bitfld.long 0x4 2. "TXRQST_ND,Write(TXRQST) - Access transmission request / read(ND) - New Data Bit" "0: Write - Tx Request bit unchanged / Read - New..,1: Write - Set Tx Request Bit / Read - Reset NewDat.."
|
|
newline
|
|
bitfld.long 0x4 1. "DATAA,Access Data Byte 0-3" "0: Data Byte 0-3 Unchanged,1: Read/Write Data Byte 0-3"
|
|
bitfld.long 0x4 0. "DATAB,Access Data Byte 4-7" "0: Data Byte 4-7 Unchanged,1: Read/Write Data Byte 4-7"
|
|
line.long 0x8 "I2MSK1,CAN Interface2 Mask1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "MSK1,Identifier Mask Standard Message"
|
|
line.long 0xC "I2MSK2,CAN Interface2 Mask2 Register"
|
|
bitfld.long 0xC 15. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0xC 14. "Mdir,Mask Message Direction" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "MSK28,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 11. "MSK27,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "MSK26,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 9. "MSK25,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "MSK24,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 7. "MSK23,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "MSK22,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 5. "MSK21,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "MSK20,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 3. "MSK19,Identifier Mask Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "MSK18,Identifier Mask Standard Message" "0,1"
|
|
bitfld.long 0xC 1. "MSK17,Identifier Mask Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "MSK16,Identifier Mask Extended Message" "0,1"
|
|
line.long 0x10 "I2ARB1,CAN Interface2 Arbitration1 Register"
|
|
bitfld.long 0x10 15. "ID15,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 14. "ID14,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "ID13,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 12. "ID12,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "ID11,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 10. "ID10,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "ID9,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 8. "ID8,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "ID7,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 6. "ID6,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "ID5,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 4. "ID4,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "ID3,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 2. "ID2,Identifier Extended Message" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "ID1,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x10 0. "ID0,Identifier Extended Message" "0,1"
|
|
line.long 0x14 "I2ARB2,CAN Interface2 Arbitration2 Register"
|
|
bitfld.long 0x14 15. "MSGV,Message Validation" "0,1"
|
|
bitfld.long 0x14 14. "Xtd,Extended Identifier" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "Dir,Message Direction" "0,1"
|
|
bitfld.long 0x14 12. "ID28,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "ID27,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x14 10. "ID26,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "ID25,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x14 8. "ID24,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "ID23,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x14 6. "ID22,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "ID21,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x14 4. "ID20,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "ID19,Identifier Standard Message" "0,1"
|
|
bitfld.long 0x14 2. "ID18,Identifier Standard Message" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "ID17,Identifier Extended Message" "0,1"
|
|
bitfld.long 0x14 0. "ID16,Identifier Extended Message" "0,1"
|
|
line.long 0x18 "I2MCR,CAN Interface2 Message Control Register"
|
|
bitfld.long 0x18 15. "NEWDAT,New Data" "0,1"
|
|
bitfld.long 0x18 14. "MSGLST,Message Lost(Only valid for direction = receive)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "INTPND,Interrupt Pending" "0,1"
|
|
bitfld.long 0x18 12. "UMASK,Use Identifier Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "TXIE,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 10. "RXIE,Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "RMTEN,Remote Enable" "0,1"
|
|
bitfld.long 0x18 8. "TXRQST,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "EOB,End of Buffer (For normal Operation This bit must be set to one)" "0,1"
|
|
hexmask.long.byte 0x18 0.--3. 1. "DLC,Data Length Code Number of Data Bytes"
|
|
line.long 0x1C "I2DA1,CAN Interface2 Data A1 Register"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "DATA1,DATA1 : Shifter Register Byte 1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DATA0,DATA0 : Shifter Register Byte 0"
|
|
line.long 0x20 "I2DA2,CAN Interface2 Data A2 Register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DATA3,DATA3 : Shifter Register Byte 3"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DATA2,DATA2 : Shifter Register Byte 2"
|
|
line.long 0x24 "I2DB1,CAN Interface2 Data B1 Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DATA5,DATA5 : Shifter Register Byte 5"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DATA4,DATA4 : Shifter Register Byte 4"
|
|
line.long 0x28 "I2DB2,CAN Interface2 Data B2 Register"
|
|
hexmask.long.byte 0x28 8.--15. 1. "DATA7,DATA7 : Shifter Register Byte 7"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DATA6,DATA6 : Shifter Register Byte 6"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "TXR1,CAN transmission Request Bit (n=16~1)"
|
|
bitfld.long 0x0 15. "TxRQST16,Transmission Request Bit 16" "0,1"
|
|
bitfld.long 0x0 14. "TxRQST15,Transmission Request Bit 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TxRQST14,Transmission Request Bit 14" "0,1"
|
|
bitfld.long 0x0 12. "TxRQST13,Transmission Request Bit 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TxRQST12,Transmission Request Bit 12" "0,1"
|
|
bitfld.long 0x0 10. "TxRQST11,Transmission Request Bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TxRQST10,Transmission Request Bit 10" "0,1"
|
|
bitfld.long 0x0 8. "TxRQST9,Transmission Request Bit 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TxRQST8,Transmission Request Bit 8" "0,1"
|
|
bitfld.long 0x0 6. "TxRQST7,Transmission Request Bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TxRQST6,Transmission Request Bit 6" "0,1"
|
|
bitfld.long 0x0 4. "TxRQST5,Transmission Request Bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TxRQST4,Transmission Request Bit 4" "0,1"
|
|
bitfld.long 0x0 2. "TxRQST3,Transmission Request Bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TxRQST2,Transmission Request Bit 2" "0,1"
|
|
bitfld.long 0x0 0. "TxRQST1,Transmission Request Bit 1" "0,1"
|
|
line.long 0x4 "TXR2,CAN transmission Request Bit (n=32~17)"
|
|
bitfld.long 0x4 15. "TxRQST32,Transmission Request Bit 32" "0,1"
|
|
bitfld.long 0x4 14. "TxRQST31,Transmission Request Bit 31" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TxRQST30,Transmission Request Bit 30" "0,1"
|
|
bitfld.long 0x4 12. "TxRQST29,Transmission Request Bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TxRQST28,Transmission Request Bit 28" "0,1"
|
|
bitfld.long 0x4 10. "TxRQST27,Transmission Request Bit 27" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TxRQST26,Transmission Request Bit 26" "0,1"
|
|
bitfld.long 0x4 8. "TxRQST25,Transmission Request Bit 25" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TxRQST24,Transmission Request Bit 24" "0,1"
|
|
bitfld.long 0x4 6. "TxRQST23,Transmission Request Bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TxRQST22,Transmission Request Bit 22" "0,1"
|
|
bitfld.long 0x4 4. "TxRQST21,Transmission Request Bit 21" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TxRQST20,Transmission Request Bit 20" "0,1"
|
|
bitfld.long 0x4 2. "TxRQST19,Transmission Request Bit 19" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TxRQST18,Transmission Request Bit 18" "0,1"
|
|
bitfld.long 0x4 0. "TxRQST17,Transmission Request Bit 17" "0,1"
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x0 "ND1,CAN New Data Register (n=16~1)"
|
|
bitfld.long 0x0 15. "NDA16,New Data Bit 16" "0,1"
|
|
bitfld.long 0x0 14. "NDA15,New Data Bit 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NDA14,New Data Bit 14" "0,1"
|
|
bitfld.long 0x0 12. "NDA13,New Data Bit 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NDA12,New Data Bit 12" "0,1"
|
|
bitfld.long 0x0 10. "NDA11,New Data Bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "NDA10,New Data Bit 10" "0,1"
|
|
bitfld.long 0x0 8. "NDA9,New Data Bit 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NDA8,New Data Bit 8" "0,1"
|
|
bitfld.long 0x0 6. "NDA7,New Data Bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "NDA6,New Data Bit 6" "0,1"
|
|
bitfld.long 0x0 4. "NDA5,New Data Bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "NDA4,New Data Bit 4" "0,1"
|
|
bitfld.long 0x0 2. "NDA3,New Data Bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NDA2,New Data Bit 2" "0,1"
|
|
bitfld.long 0x0 0. "NDA1,New Data Bit 1" "0,1"
|
|
line.long 0x4 "ND2,CAN New Data Register (n=32~17)"
|
|
bitfld.long 0x4 15. "NDA32,New Data Bit 32" "0,1"
|
|
bitfld.long 0x4 14. "NDA31,New Data Bit 31" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NDA30,New Data Bit 30" "0,1"
|
|
bitfld.long 0x4 12. "NDA29,New Data Bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "NDA28,New Data Bit 28" "0,1"
|
|
bitfld.long 0x4 10. "NDA27,New Data Bit 27" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "NDA26,New Data Bit 26" "0,1"
|
|
bitfld.long 0x4 8. "NDA25,New Data Bit 25" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "NDA24,New Data Bit 24" "0,1"
|
|
bitfld.long 0x4 6. "NDA23,New Data Bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NDA22,New Data Bit 22" "0,1"
|
|
bitfld.long 0x4 4. "NDA21,New Data Bit 21" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "NDA20,New Data Bit 20" "0,1"
|
|
bitfld.long 0x4 2. "NDA19,New Data Bit 19" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NDA18,New Data Bit 18" "0,1"
|
|
bitfld.long 0x4 0. "NDA17,New Data Bit 17" "0,1"
|
|
rgroup.long 0x140++0x7
|
|
line.long 0x0 "ISR1,CAN Interrupt Status Register (n=16~1)"
|
|
bitfld.long 0x0 15. "INTPND16,Interrupt Pending Bit 16" "0,1"
|
|
bitfld.long 0x0 14. "INTPND15,Interrupt Pending Bit 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "INTPND14,Interrupt Pending Bit 14" "0,1"
|
|
bitfld.long 0x0 12. "INTPND13,Interrupt Pending Bit 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "INTPND12,Interrupt Pending Bit 12" "0,1"
|
|
bitfld.long 0x0 10. "INTPND11,Interrupt Pending Bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "INTPND10,Interrupt Pending Bit 10" "0,1"
|
|
bitfld.long 0x0 8. "INTPND9,Interrupt Pending Bit 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "INTPND8,Interrupt Pending Bit 8" "0,1"
|
|
bitfld.long 0x0 6. "INTPND7,Interrupt Pending Bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INTPND6,Interrupt Pending Bit 6" "0,1"
|
|
bitfld.long 0x0 4. "INTPND5,Interrupt Pending Bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "INTPND4,Interrupt Pending Bit 4" "0,1"
|
|
bitfld.long 0x0 2. "INTPND3,Interrupt Pending Bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTPND2,Interrupt Pending Bit 2" "0,1"
|
|
bitfld.long 0x0 0. "INTPND1,Interrupt Pending Bit 1" "0,1"
|
|
line.long 0x4 "ISR2,CAN Interrupt Status Register (n=32~17)"
|
|
bitfld.long 0x4 15. "INTPND32,Interrupt Pending Bit 32" "0,1"
|
|
bitfld.long 0x4 14. "INTPND31,Interrupt Pending Bit 31" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "INTPND30,Interrupt Pending Bit 30" "0,1"
|
|
bitfld.long 0x4 12. "INTPND29,Interrupt Pending Bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "INTPND28,Interrupt Pending Bit 28" "0,1"
|
|
bitfld.long 0x4 10. "INTPND27,Interrupt Pending Bit 27" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "INTPND26,Interrupt Pending Bit 26" "0,1"
|
|
bitfld.long 0x4 8. "INTPND25,Interrupt Pending Bit 25" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "INTPND24,Interrupt Pending Bit 24" "0,1"
|
|
bitfld.long 0x4 6. "INTPND23,Interrupt Pending Bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INTPND22,Interrupt Pending Bit 22" "0,1"
|
|
bitfld.long 0x4 4. "INTPND21,Interrupt Pending Bit 21" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "INTPND20,Interrupt Pending Bit 20" "0,1"
|
|
bitfld.long 0x4 2. "INTPND19,Interrupt Pending Bit 19" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "INTPND18,Interrupt Pending Bit 18" "0,1"
|
|
bitfld.long 0x4 0. "INTPND17,Interrupt Pending Bit 17" "0,1"
|
|
rgroup.long 0x160++0x7
|
|
line.long 0x0 "MVR1,CAN Message Validation Register (n=16~1)"
|
|
bitfld.long 0x0 15. "MSGVAL16,Message Validation Bit 16" "0,1"
|
|
bitfld.long 0x0 14. "MSGVAL15,Message Validation Bit 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MSGVAL14,Message Validation Bit 14" "0,1"
|
|
bitfld.long 0x0 12. "MSGVAL13,Message Validation Bit 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MSGVAL12,Message Validation Bit 12" "0,1"
|
|
bitfld.long 0x0 10. "MSGVAL11,Message Validation Bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MSGVAL10,Message Validation Bit 10" "0,1"
|
|
bitfld.long 0x0 8. "MSGVAL9,Message Validation Bit 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MSGVAL8,Message Validation Bit 8" "0,1"
|
|
bitfld.long 0x0 6. "MSGVAL7,Message Validation Bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MSGVAL6,Message Validation Bit 6" "0,1"
|
|
bitfld.long 0x0 4. "MSGVAL5,Message Validation Bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSGVAL4,Message Validation Bit 4" "0,1"
|
|
bitfld.long 0x0 2. "MSGVAL3,Message Validation Bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MSGVAL2,Message Validation Bit 2" "0,1"
|
|
bitfld.long 0x0 0. "MSGVAL1,Message Validation Bit 1" "0,1"
|
|
line.long 0x4 "MVR2,CAN Message Validation Register (n=32~17)"
|
|
bitfld.long 0x4 15. "MSGVAL32,Message Validation Bit 32" "0,1"
|
|
bitfld.long 0x4 14. "MSGVAL31,Message Validation Bit 31" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MSGVAL30,Message Validation Bit 30" "0,1"
|
|
bitfld.long 0x4 12. "MSGVAL29,Message Validation Bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MSGVAL28,Message Validation Bit 28" "0,1"
|
|
bitfld.long 0x4 10. "MSGVAL27,Message Validation Bit 27" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MSGVAL26,Message Validation Bit 26" "0,1"
|
|
bitfld.long 0x4 8. "MSGVAL25,Message Validation Bit 25" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MSGVAL24,Message Validation Bit 24" "0,1"
|
|
bitfld.long 0x4 6. "MSGVAL23,Message Validation Bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MSGVAL22,Message Validation Bit 22" "0,1"
|
|
bitfld.long 0x4 4. "MSGVAL21,Message Validation Bit 21" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MSGVAL20,Message Validation Bit 20" "0,1"
|
|
bitfld.long 0x4 2. "MSGVAL19,Message Validation Bit 19" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MSGVAL18,Message Validation Bit 18" "0,1"
|
|
bitfld.long 0x4 0. "MSGVAL17,Message Validation Bit 17" "0,1"
|
|
tree.end
|
|
tree "CHIPCONFIG (Chip Configuration Data)"
|
|
base ad:0x4000F000
|
|
rgroup.long 0x0++0xB
|
|
line.long 0x0 "VENDORID,Vendor ID Register"
|
|
line.long 0x4 "CHIPID,Chip ID Register"
|
|
line.long 0x8 "REVNR,Revision Number Register"
|
|
tree.end
|
|
tree "COMP (Comparator)"
|
|
base ad:0x0
|
|
tree "COMP0"
|
|
base ad:0x4000B380
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CONF,Comparator 0 Configuration Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FLTSEL,Filter Counter Bit Selection"
|
|
bitfld.long 0x0 20. "HYSEN,Comparator Hysteresis Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "HYSSEL,Comparator Hysteresis Selection Bit" "0: 5mV Hysteresis,1: 20mV Hysteresis"
|
|
bitfld.long 0x0 10. "INTPOL,Interrupt Polarity Selection Bit" "0: Low,1: High"
|
|
bitfld.long 0x0 8.--9. "INTTYPE,Interrupt Type Selection Bit" "0: Disable,1: Level,2: Single Edge,3: Both Edge"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CINNSEL,Comparator Reference (Input) Selection Bit" "0: Comparator Reference 0,1: Comparator Reference 1,?,?"
|
|
bitfld.long 0x0 0.--1. "CINPSEL,Comparator Input (Input) Selection Bit" "0: Comparator Input 0,1: Comparator Input 1,2: Comparator Input 2,3: Comparator Input 3"
|
|
line.long 0x4 "CTRL,Comparator 0 Control Register"
|
|
bitfld.long 0x4 8. "COMPINTEN,Comparator Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "COMPEN,Comparator Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x8 "STAT,Comparator 0 Status Register"
|
|
bitfld.long 0x8 8. "COMPINTF,Comparator Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0x8 0. "COMPFLAG,Comparator Output Flag" "0,1"
|
|
tree.end
|
|
tree "COMP1"
|
|
base ad:0x4000B38C
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CONF,Comparator 0 Configuration Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FLTSEL,Filter Counter Bit Selection"
|
|
bitfld.long 0x0 20. "HYSEN,Comparator Hysteresis Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "HYSSEL,Comparator Hysteresis Selection Bit" "0: 5mV Hysteresis,1: 20mV Hysteresis"
|
|
bitfld.long 0x0 10. "INTPOL,Interrupt Polarity Selection Bit" "0: Low,1: High"
|
|
bitfld.long 0x0 8.--9. "INTTYPE,Interrupt Type Selection Bit" "0: Disable,1: Level,2: Single Edge,3: Both Edge"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CINNSEL,Comparator Reference (Input) Selection Bit" "0: Comparator Reference 0,1: Comparator Reference 1,?,?"
|
|
bitfld.long 0x0 0.--1. "CINPSEL,Comparator Input (Input) Selection Bit" "0: Comparator Input 0,1: Comparator Input 1,2: Comparator Input 2,3: Comparator Input 3"
|
|
line.long 0x4 "CTRL,Comparator 0 Control Register"
|
|
bitfld.long 0x4 8. "COMPINTEN,Comparator Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "COMPEN,Comparator Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x8 "STAT,Comparator 0 Status Register"
|
|
bitfld.long 0x8 8. "COMPINTF,Comparator Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0x8 0. "COMPFLAG,Comparator Output Flag" "0,1"
|
|
tree.end
|
|
tree "COMP2"
|
|
base ad:0x4000B398
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CONF,Comparator 0 Configuration Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FLTSEL,Filter Counter Bit Selection"
|
|
bitfld.long 0x0 20. "HYSEN,Comparator Hysteresis Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "HYSSEL,Comparator Hysteresis Selection Bit" "0: 5mV Hysteresis,1: 20mV Hysteresis"
|
|
bitfld.long 0x0 10. "INTPOL,Interrupt Polarity Selection Bit" "0: Low,1: High"
|
|
bitfld.long 0x0 8.--9. "INTTYPE,Interrupt Type Selection Bit" "0: Disable,1: Level,2: Single Edge,3: Both Edge"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CINNSEL,Comparator Reference (Input) Selection Bit" "0: Comparator Reference 0,1: Comparator Reference 1,?,?"
|
|
bitfld.long 0x0 0.--1. "CINPSEL,Comparator Input (Input) Selection Bit" "0: Comparator Input 0,1: Comparator Input 1,2: Comparator Input 2,3: Comparator Input 3"
|
|
line.long 0x4 "CTRL,Comparator 0 Control Register"
|
|
bitfld.long 0x4 8. "COMPINTEN,Comparator Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "COMPEN,Comparator Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x8 "STAT,Comparator 0 Status Register"
|
|
bitfld.long 0x8 8. "COMPINTF,Comparator Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0x8 0. "COMPFLAG,Comparator Output Flag" "0,1"
|
|
tree.end
|
|
tree "COMP3"
|
|
base ad:0x4000B3A4
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CONF,Comparator 0 Configuration Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FLTSEL,Filter Counter Bit Selection"
|
|
bitfld.long 0x0 20. "HYSEN,Comparator Hysteresis Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "HYSSEL,Comparator Hysteresis Selection Bit" "0: 5mV Hysteresis,1: 20mV Hysteresis"
|
|
bitfld.long 0x0 10. "INTPOL,Interrupt Polarity Selection Bit" "0: Low,1: High"
|
|
bitfld.long 0x0 8.--9. "INTTYPE,Interrupt Type Selection Bit" "0: Disable,1: Level,2: Single Edge,3: Both Edge"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CINNSEL,Comparator Reference (Input) Selection Bit" "0: Comparator Reference 0,1: Comparator Reference 1,?,?"
|
|
bitfld.long 0x0 0.--1. "CINPSEL,Comparator Input (Input) Selection Bit" "0: Comparator Input 0,1: Comparator Input 1,2: Comparator Input 2,3: Comparator Input 3"
|
|
line.long 0x4 "CTRL,Comparator 0 Control Register"
|
|
bitfld.long 0x4 8. "COMPINTEN,Comparator Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "COMPEN,Comparator Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x8 "STAT,Comparator 0 Status Register"
|
|
bitfld.long 0x8 8. "COMPINTF,Comparator Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0x8 0. "COMPFLAG,Comparator Output Flag" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check and Checksum)"
|
|
base ad:0x41002000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,CRC Control Register"
|
|
bitfld.long 0x0 21. "OUT_INV,CRC Output Data Inversion Enable bit" "0,1"
|
|
bitfld.long 0x0 20. "OUT_REV,CRC Output Data Reverse Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "IN_REV,Input Data Reverse Mode Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "DMADINT,DMA Done Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1.--2. "POLY,Polynomal Selection Bit" "0: 0x04C1_1DB7,1: 0x8005,2: 0x07,3: 0x09"
|
|
bitfld.long 0x0 0. "INIT_EN,CRC Init Register Apply Bit" "0,1"
|
|
line.long 0x4 "INIT,CRC Init value Register"
|
|
hexmask.long 0x4 0.--31. 1. "INIT,CRC Initial Value"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "IDR,CRC Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "INPUT,CRC Input Data Bit"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ODR,CRC Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "OUTPUT,CRC Output Data Bit"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "STAT,CRC Status Register"
|
|
bitfld.long 0x0 8. "DMADINT,DMA Done Interrupt Flag Bit" "0,1"
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA0"
|
|
base ad:0x40000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x40000410
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x40000420
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA3"
|
|
base ad:0x40000430
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA4"
|
|
base ad:0x40000440
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA5"
|
|
base ad:0x40000450
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA6"
|
|
base ad:0x40000460
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA7"
|
|
base ad:0x40000470
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA8"
|
|
base ad:0x40000480
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA9"
|
|
base ad:0x40000490
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA10"
|
|
base ad:0x400004A0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA11"
|
|
base ad:0x400004B0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA12"
|
|
base ad:0x400004C0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA13"
|
|
base ad:0x400004D0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA14"
|
|
base ad:0x400004E0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree "DMA15"
|
|
base ad:0x400004F0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,DMA Transmit counter"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral Selection Bit"
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus Transmit Size" "0: transmit byte size,1: transmit half word size,2: transmit word size,?"
|
|
bitfld.long 0x0 1. "DIR,Transmit direction selection bit" "0: Memory->Peripheral,1: Peripheral->Memory"
|
|
line.long 0x4 "SR,DMA Status Register"
|
|
rbitfld.long 0x4 7. "EOT,Transmit is over" "0,1"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable Bit" "0,1"
|
|
line.long 0x8 "PAR,DMA Peripheral address register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PARBASEOFFSET,Peripheral Base Offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Peripheral address bit"
|
|
line.long 0xC "MAR,DMA Memory address register"
|
|
hexmask.long.word 0xC 16.--31. 1. "MEMBASEADDRESS,Memory Base Address"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,Purpose Memory Address"
|
|
tree.end
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x0
|
|
tree "CFMC (Code Flash Memory Controller)"
|
|
base ad:0x41000000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CONF,Flash Memory Control Register"
|
|
bitfld.long 0x0 24. "BBLOCK,Boot Block Lock Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "DCRST,Data Cache Reset Control bit (Auto Clear)" "0,1"
|
|
bitfld.long 0x0 16. "ICRST,Instruction Cache Reset Control Bit (Auto Clear)" "0,1"
|
|
bitfld.long 0x0 9. "DCEN,Data Cache Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "ICEN,Instruction Cache Enable Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Flash Wait Value Bits"
|
|
line.long 0x4 "FLSKEY,Flash Memory Access Key Register"
|
|
hexmask.long 0x4 0.--31. 1. "FKEY,Flash Memory Access Key KEY1(0x01234567) -> KEY2(0x12345678) -> KEY3(0x23456789)"
|
|
line.long 0x8 "OTPKEY,Flash OTP Access Key Register"
|
|
hexmask.long 0x8 0.--31. 1. "OKEY,OTP Access Key Bits KEY1(0x3456789A) -> KEY2(0x456789AB) -> KEY3(0x56789ABC)"
|
|
line.long 0xC "FLSPROT,Flash Memory Protection Register"
|
|
bitfld.long 0xC 31. "FUP512B_7,Flash upper 4KB Unprotection 0x0007_FE00 0x0007FFFF" "0,1"
|
|
bitfld.long 0xC 30. "FUP512B_6,Flash upper 4KB Unprotection 0x0007_FC00 0x0007FDFF" "0,1"
|
|
bitfld.long 0xC 29. "FUP512B_5,Flash upper 4KB Unprotection 0x0007_FA00 0x0007FBFF" "0,1"
|
|
bitfld.long 0xC 28. "FUP512B_4,Flash upper 4KB Unprotection 0x0007_F800 0x0007F9FF" "0,1"
|
|
bitfld.long 0xC 27. "FUP512B_3,Flash upper 4KB Unprotection 0x0007_F600 0x0007F7FF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 26. "FUP512B_2,Flash upper 4KB Unprotection 0x0007_F400 0x0007F5FF" "0,1"
|
|
bitfld.long 0xC 25. "FUP512B_1,Flash upper 4KB Unprotection 0x0007_F200 0x0007F3FF" "0,1"
|
|
bitfld.long 0xC 24. "FUP512B_0,Flash upper 4KB Unprotection 0x0007_F000 0x0007F1FF" "0,1"
|
|
bitfld.long 0xC 15. "FPBY32K_15,Flash 32KB Protection 0x0007_8000 0x0007_FFFF" "0,1"
|
|
bitfld.long 0xC 14. "FPBY32K_14,Flash 32KB Protection 0x0007_0000 0x0007_7FFF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FPBY32K_13,Flash 32KB Protection 0x0006_8000 0x0006_FFFF" "0,1"
|
|
bitfld.long 0xC 12. "FPBY32K_12,Flash 32KB Protection 0x0006_0000 0x0006_7FFF" "0,1"
|
|
bitfld.long 0xC 11. "FPBY32K_11,Flash 32KB Protection 0x0005_8000 0x0005_FFFF" "0,1"
|
|
bitfld.long 0xC 10. "FPBY32K_10,Flash 32KB Protection 0x0005_0000 0x0005_7FFF" "0,1"
|
|
bitfld.long 0xC 9. "FPBY32K_9,Flash 32KB Protection 0x0004_8000 0x0004_FFFF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "FPBY32K_8,Flash 32KB Protection 0x0004_0000 0x0004_7FFF" "0,1"
|
|
bitfld.long 0xC 7. "FPBY32K_7,Flash 32KB Protection 0x0003_8000 0x0003_FFFF" "0,1"
|
|
bitfld.long 0xC 6. "FPBY32K_6,Flash 32KB Protection 0x0003_0000 0x0003_7FFF" "0,1"
|
|
bitfld.long 0xC 5. "FPBY32K_5,Flash 32KB Protection 0x0002_8000 0x0002_FFFF" "0,1"
|
|
bitfld.long 0xC 4. "FPBY32K_4,Flash 32KB Protection 0x0002_0000 0x0002_7FFF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FPBY32K_3,Flash 32KB Protection 0x0001_8000 0x0001_FFFF" "0,1"
|
|
bitfld.long 0xC 2. "FPBY32K_2,Flash 32KB Protection 0x0001_0000 0x0001_7FFF" "0,1"
|
|
bitfld.long 0xC 1. "FPBY32K_1,Flash 32KB Protection 0x0000_8000 0x0000_FFFF" "0,1"
|
|
bitfld.long 0xC 0. "FPBY32K_0,Flash 32KB Protection 0x0000_0000 0x0000_7FFF" "0,1"
|
|
line.long 0x10 "OTPPROT,Flash OTP Protection Register"
|
|
bitfld.long 0x10 2. "OP2,OTP Area Protection bit 0x0F00_0400 0x0F00_05FF" "0,1"
|
|
bitfld.long 0x10 1. "OP1,OTP Area Protection bit 0x0F00_0200 0x0F00_03FF" "0,1"
|
|
bitfld.long 0x10 0. "OP0,OTP Area Protection bit 0x0F00_0000 0x0F00_01FF" "0,1"
|
|
line.long 0x14 "CTRL,Flash Access Control Register"
|
|
bitfld.long 0x14 31. "FLOCK,Flash Lock Setting Bit" "0,1"
|
|
bitfld.long 0x14 30. "OLOCK,OTP Lock Setting Bit" "0,1"
|
|
bitfld.long 0x14 8. "WDIEN,Write done interrupt enable bit" "0,1"
|
|
bitfld.long 0x14 4. "CERS,Chip Erase Mode Bit" "0,1"
|
|
bitfld.long 0x14 3. "S4KERS,Sector 4KB Erase Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "S1KERS,Sector 1KB Erase Mode" "0,1"
|
|
bitfld.long 0x14 1. "PERS,Page Erase Mode" "0,1"
|
|
bitfld.long 0x14 0. "PGM,Program Mode" "0,1"
|
|
line.long 0x18 "STAT,Flash Access Status Register"
|
|
bitfld.long 0x18 21. "RPERR,Read Protect Error(Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 20. "WSERR,Write Sequence Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 19. "OPERR,OTP Protect Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 18. "FPERR,Flash Protect Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 17. "OLERR,OTP Lock Error (Auto Cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "FLERR,Flash Lock Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 9. "CDONE,Checksum Done Check (Auto Cleared)" "0,1"
|
|
bitfld.long 0x18 8. "WDONE,Write Done Check (Auto Cleared)" "0,1"
|
|
rbitfld.long 0x18 1. "CBUSY,Checksum Busy Check" "0: Checksum Not Busy,1: Checksum Busy"
|
|
rbitfld.long 0x18 0. "WBUSY,Write Busy Check" "0: Checksum Not Busy,1: Checksum Busy"
|
|
line.long 0x1C "READPROT,Flash Read Protection Register"
|
|
rbitfld.long 0x1C 31. "DBGMOD,Debug Operating Status Bit" "0,1"
|
|
rbitfld.long 0x1C 30. "SRBOOT,Sram Boot Mode Status Bit" "0,1"
|
|
rbitfld.long 0x1C 26. "PWMATCH,Password Match Flag Bit" "0,1"
|
|
rbitfld.long 0x1C 25. "OTP0ERSD,Chip & OTP0 Erase Done Flag Bit" "0,1"
|
|
rbitfld.long 0x1C 24. "CERSD,Chip Erase Done Flag Bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x1C 17. "LVL2_STS,Protection Level 2 Status Bit (Raw Data)" "0,1"
|
|
rbitfld.long 0x1C 16. "LVL1_STS,Protection Level 1 Status Bit (Raw Data)" "0,1"
|
|
rbitfld.long 0x1C 9. "LVL2_EN,Protection Level 2 Enable Bit" "0,1"
|
|
rbitfld.long 0x1C 8. "LVL1_EN,Protection Level 1 Enable Bit" "0,1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "RPROT,Read Protection Control Bit"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "PWIN,Flash Read Protection Password Input Register"
|
|
hexmask.long 0x0 0.--31. 1. "PWIN,Password Input Data Bit"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CHKCTRL,Flash Checksum Control Register"
|
|
bitfld.long 0x0 16. "CDRST,Checksum Data Reset (Auto Cleared)" "0: No Effect,1: Reset"
|
|
bitfld.long 0x0 8. "CDIEN,Checksum Done Interrupt" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 1. "BSTEN,Burst Mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "BGEN,Back Ground Mode" "0: Disable,1: Enable"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CHKDOUT,Flash Checksum Data Output Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CDOUT,Flash Checksum Data Output bit"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "CHKSADDR,Flash Checksum Start Address Resgister"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "SADDR,Flash Checksum Start Address bit"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIXED_VALUE,Fixed Vaule"
|
|
line.long 0x4 "CHKEADDR,Flash Checksum End Address Register"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "EADDR,Flash Checksum End Address bit"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FIXED_VALUE,Fixed Value"
|
|
wgroup.long 0xF18++0x3
|
|
line.long 0x0 "PWPRST,Flash Read Protection Password Preset Register"
|
|
hexmask.long 0x0 0.--31. 1. "PWPRST,Password Preset Data Bit"
|
|
tree.end
|
|
tree "DFMC (Data Flash Memory Controller)"
|
|
base ad:0x41001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CONF,Flash Memory Control Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Flash Wait Value Bits"
|
|
line.long 0x4 "FLSKEY,Flash Memory Access Key Register"
|
|
hexmask.long 0x4 0.--31. 1. "FKEY,Flash Memory Access Key KEY1(0x01234567) -> KEY2(0x12345678) -> KEY3(0x23456789)"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLSPROT,Flash Memory Protection Register"
|
|
bitfld.long 0x0 31. "FUP512B_7,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 30. "FUP512B_6,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 29. "FUP512B_5,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 28. "FUP512B_4,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 27. "FUP512B_3,Flash upper 4KB Unprotection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "FUP512B_2,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 25. "FUP512B_1,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 24. "FUP512B_0,Flash upper 4KB Unprotection" "0,1"
|
|
bitfld.long 0x0 15. "FPBY2K_15,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 14. "FPBY2K_14,Flash 2KB Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "FPBY2K_13,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 12. "FPBY2K_12,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 11. "FPBY2K_11,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 10. "FPBY2K_10,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 9. "FPBY2K_9,Flash 2KB Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FPBY2K_8,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 7. "FPBY2K_7,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 6. "FPBY2K_6,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 5. "FPBY2K_5,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 4. "FPBY2K_4,Flash 2KB Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPBY2K_3,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 2. "FPBY2K_2,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 1. "FPBY2K_1,Flash 2KB Protection" "0,1"
|
|
bitfld.long 0x0 0. "FPBY2K_0,Flash 2KB Protection" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "CTRL,Flash Access Control Register"
|
|
bitfld.long 0x0 31. "FLOCK,Flash Lock Setting Bit" "0,1"
|
|
bitfld.long 0x0 8. "WDIEN,Write done interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CERS,Chip Erase Mode Bit" "0,1"
|
|
bitfld.long 0x0 3. "S4KERS,Sector 4KB Erase Mode" "0,1"
|
|
bitfld.long 0x0 2. "S1KERS,Sector 1KB Erase Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PERS,Page Erase Mode" "0,1"
|
|
bitfld.long 0x0 0. "PGM,Program Mode" "0,1"
|
|
line.long 0x4 "STAT,Flash Access Status Register"
|
|
bitfld.long 0x4 21. "RPERR,Read Protect Error(Auto Cleared)" "0,1"
|
|
bitfld.long 0x4 20. "WSERR,Write Sequence Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x4 18. "FPERR,Flash Protect Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x4 16. "FLERR,Flash Lock Error (Auto Cleared)" "0,1"
|
|
bitfld.long 0x4 9. "CDONE,Checksum Done Check (Auto Cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "WDONE,Write Done Check (Auto Cleared)" "0,1"
|
|
rbitfld.long 0x4 1. "CBUSY,Checksum Busy Check" "0: Checksum Not Busy,1: Checksum Busy"
|
|
rbitfld.long 0x4 0. "WBUSY,Write Busy Check" "0: Checksum Not Busy,1: Checksum Busy"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CHKCTRL,Flash Checksum Control Register"
|
|
bitfld.long 0x0 16. "CDRST,Checksum Data Reset (Auto Cleared)" "0: No Effect,1: Reset"
|
|
bitfld.long 0x0 8. "CDIEN,Checksum Done Interrupt" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 1. "BSTEN,Burst Mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "BGEN,Back Ground Mode" "0: Disable,1: Enable"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CHKDOUT,Flash Checksum Data Output Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CDOUT,Flash Checksum Data Output bit"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "CHKSADDR,Flash Checksum Start Address Resgister"
|
|
hexmask.long 0x0 6.--31. 1. "SADDR,Flash Checksum Start Address bit"
|
|
hexmask.long.byte 0x0 0.--5. 1. "FIXED_VALUE,Fixed Vaule"
|
|
line.long 0x4 "CHKEADDR,Flash Checksum End Address Register"
|
|
hexmask.long 0x4 6.--31. 1. "EADDR,Flash Checksum End Address bit"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FIXED_VALUE,Fixed Value"
|
|
tree.end
|
|
tree.end
|
|
tree "FRT (Free-Run Timer)"
|
|
base ad:0x0
|
|
tree "FRT0"
|
|
base ad:0x40000600
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRL,FRT n Control Register"
|
|
bitfld.long 0x0 9. "OVFIE,Over Flow Interrupt Enable bit" "0: Interrupt Disable,1: Interrupt Enable"
|
|
bitfld.long 0x0 8. "MATCHIE,Match Interrupt Enable Bit" "0: Interrupt Disable,1: Interrupt Enable"
|
|
bitfld.long 0x0 1. "MODE,FRT Mode Selection Bit" "0: Free-Run Timer,1: Match Timer"
|
|
bitfld.long 0x0 0. "EN,FRT Enable Bit" "0: FRT Disable,1: FRT Enable"
|
|
line.long 0x4 "MCNT,FRT n Match Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "MCNT,Match Counter Bit"
|
|
line.long 0x8 "CNT,FRT n Counter Register"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,Counter Bit *only write '0x0'"
|
|
line.long 0xC "STAT,FRT n Status Register"
|
|
bitfld.long 0xC 9. "OVFI,Overflow Interrupt Status" "0,1"
|
|
bitfld.long 0xC 8. "MATCHI,Match Interrupt Status" "0,1"
|
|
tree.end
|
|
tree "FRT1"
|
|
base ad:0x40000700
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRL,FRT n Control Register"
|
|
bitfld.long 0x0 9. "OVFIE,Over Flow Interrupt Enable bit" "0: Interrupt Disable,1: Interrupt Enable"
|
|
bitfld.long 0x0 8. "MATCHIE,Match Interrupt Enable Bit" "0: Interrupt Disable,1: Interrupt Enable"
|
|
bitfld.long 0x0 1. "MODE,FRT Mode Selection Bit" "0: Free-Run Timer,1: Match Timer"
|
|
bitfld.long 0x0 0. "EN,FRT Enable Bit" "0: FRT Disable,1: FRT Enable"
|
|
line.long 0x4 "MCNT,FRT n Match Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "MCNT,Match Counter Bit"
|
|
line.long 0x8 "CNT,FRT n Counter Register"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,Counter Bit *only write '0x0'"
|
|
line.long 0xC "STAT,FRT n Status Register"
|
|
bitfld.long 0xC 9. "OVFI,Overflow Interrupt Status" "0,1"
|
|
bitfld.long 0xC 8. "MATCHI,Match Interrupt Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
tree "I2C0"
|
|
base ad:0x4000A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DR,I2Cn Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICDR,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "SR,I2Cn Status Register"
|
|
bitfld.long 0x0 7. "GCALL,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
bitfld.long 0x0 6. "TEND,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
bitfld.long 0x0 5. "STOP,This bit is set when a STOP condition is detected." "0,1"
|
|
bitfld.long 0x0 4. "SSEL,This bit is set when I2C is addressed by other master." "0,1"
|
|
bitfld.long 0x0 3. "MLOST,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
bitfld.long 0x0 2. "BUSY,This bit reflects bus status." "0,1"
|
|
rbitfld.long 0x0 1. "TMOD,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
bitfld.long 0x0 0. "RXACK,This bit shows the state of ACK signal." "0,1"
|
|
line.long 0x4 "SAR,I2Cn Slave Address Register"
|
|
hexmask.long.byte 0x4 1.--7. 1. "SVAD,These bits configure the slave address in slave mode."
|
|
bitfld.long 0x4 0. "GCEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "CR,I2Cn Control Register"
|
|
bitfld.long 0x0 8.--9. "INTDEL,between Address and Transmit data delay" "0: Delay = 1*ICnSCLL,1: Delay = 2*ICnSCLL,2: Delay = 4*ICnSCLL,3: Delay = 8*ICnSCLL"
|
|
rbitfld.long 0x0 7. "IIF,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
bitfld.long 0x0 5. "SOFTRST,Software Reset allow bit" "0,1"
|
|
bitfld.long 0x0 4. "INTEN,Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "ACKEN,received mode ACK allow bit" "0,1"
|
|
bitfld.long 0x0 1. "STOP,STOP Condition Generation When I2Cn is master." "0,1"
|
|
bitfld.long 0x0 0. "START,START Condition Generation When I2Cn is master." "0,1"
|
|
line.long 0x4 "SCLL,I2Cn SCL Low Period Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x8 "SCLH,I2Cn SCL High Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SCLH,SCLH Value"
|
|
line.long 0xC "SDH,I2Cn SCL Hold Time Register"
|
|
hexmask.long.word 0xC 0.--14. 1. "SDH,SDH Value"
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x4000A100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DR,I2Cn Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICDR,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "SR,I2Cn Status Register"
|
|
bitfld.long 0x0 7. "GCALL,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
bitfld.long 0x0 6. "TEND,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
bitfld.long 0x0 5. "STOP,This bit is set when a STOP condition is detected." "0,1"
|
|
bitfld.long 0x0 4. "SSEL,This bit is set when I2C is addressed by other master." "0,1"
|
|
bitfld.long 0x0 3. "MLOST,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
bitfld.long 0x0 2. "BUSY,This bit reflects bus status." "0,1"
|
|
rbitfld.long 0x0 1. "TMOD,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
bitfld.long 0x0 0. "RXACK,This bit shows the state of ACK signal." "0,1"
|
|
line.long 0x4 "SAR,I2Cn Slave Address Register"
|
|
hexmask.long.byte 0x4 1.--7. 1. "SVAD,These bits configure the slave address in slave mode."
|
|
bitfld.long 0x4 0. "GCEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "CR,I2Cn Control Register"
|
|
bitfld.long 0x0 8.--9. "INTDEL,between Address and Transmit data delay" "0: Delay = 1*ICnSCLL,1: Delay = 2*ICnSCLL,2: Delay = 4*ICnSCLL,3: Delay = 8*ICnSCLL"
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|
rbitfld.long 0x0 7. "IIF,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
bitfld.long 0x0 5. "SOFTRST,Software Reset allow bit" "0,1"
|
|
bitfld.long 0x0 4. "INTEN,Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "ACKEN,received mode ACK allow bit" "0,1"
|
|
bitfld.long 0x0 1. "STOP,STOP Condition Generation When I2Cn is master." "0,1"
|
|
bitfld.long 0x0 0. "START,START Condition Generation When I2Cn is master." "0,1"
|
|
line.long 0x4 "SCLL,I2Cn SCL Low Period Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x8 "SCLH,I2Cn SCL High Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SCLH,SCLH Value"
|
|
line.long 0xC "SDH,I2Cn SCL Hold Time Register"
|
|
hexmask.long.word 0xC 0.--14. 1. "SDH,SDH Value"
|
|
tree.end
|
|
tree.end
|
|
tree "MPWM (Motor Pulse-Width Modulation)"
|
|
base ad:0x0
|
|
tree "MPWM0"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x4F
|
|
line.long 0x0 "MR,MPWM n Mode Register"
|
|
bitfld.long 0x0 14.--15. "MOTORB,MPWM Mode Selection Bit" "0: Motor PWM Mode,1: Normal PWM Mode,?,3: Extend PWM Mode"
|
|
bitfld.long 0x0 7. "UAO,Update Timing Selection Bit" "0: Designate timing update,1: Once Duty Period Update"
|
|
newline
|
|
bitfld.long 0x0 5. "TUP,DUTY Period Update Enable bit (When same period)" "0: None Update,1: Update"
|
|
bitfld.long 0x0 4. "BUP,DUTY Period Update Enable bit (When same bottom)" "0: None Update,1: Update"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "MCHMOD,Channel Symmetry/Asymmetry Mode Selection Bit" "0: 2-ch symmetry mode,1: 1-ch asymmetry mode,2: 1-ch symmetry mode,?"
|
|
bitfld.long 0x0 0. "UPDOWN,PWM Up/Down Counter Mode Selection Bit" "0: PWM Up Counter Mode(MOTORB = 1),1: Up/Down Counter Mode (MOTORB = 0 1 3)"
|
|
line.long 0x4 "OLR,MPWM n Output Level Register"
|
|
bitfld.long 0x4 13. "DOLWH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 12. "DOLVH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 11. "DOLUH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 10. "DOLWL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 9. "DOLVL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 8. "DOLUL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 5. "WHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 4. "VHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
newline
|
|
bitfld.long 0x4 3. "UHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 2. "WLL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
newline
|
|
bitfld.long 0x4 1. "VLL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 0. "ULL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
line.long 0x8 "FOLR,MPWM n compulsion Output Register"
|
|
bitfld.long 0x8 5. "WHFL,WH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 4. "VHFL,VH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
newline
|
|
bitfld.long 0x8 3. "UHFL,UH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 2. "WLFL,WL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
newline
|
|
bitfld.long 0x8 1. "VLFL,VL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 0. "ULFL,UL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
line.long 0xC "PRD,MPWM n Period Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PERIOD,16bit pwm period"
|
|
line.long 0x10 "DUH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "DUTY_UH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x14 "DVH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "DUTY_VH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x18 "DWH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "DUTY_WH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x1C "DUL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DUTY_UL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x20 "DVL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "DUTY_VL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x24 "DWL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "DUTY_WL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x28 "CR1,MPWM n Control Register 1"
|
|
bitfld.long 0x28 8.--10. "IRQN,IRQ number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 0. "PWMEN,PWM Enable Bit" "0,1"
|
|
line.long 0x2C "CR2,MPWM n Control Register 2"
|
|
bitfld.long 0x2C 7. "HALT,PWM HALT" "0,1"
|
|
bitfld.long 0x2C 0. "PSTART,PWM Phase x counter start" "0,1"
|
|
line.long 0x30 "SR,MPWM n Status Register"
|
|
rbitfld.long 0x30 23. "WDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 20.--22. "IRQWCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x30 19. "VDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 16.--18. "IRQVCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x30 15. "UDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 12.--14. "IRQUCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x30 11. "PRDWIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 10. "BOTWIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 9. "PRDVIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 8. "BOTVIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 7. "PRDUIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 6. "BOTUIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 5. "DWHIF_ATR6F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 4. "DVHIF_ATR5F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 3. "DUHIF_ATR4F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 2. "DWLIF_ATR3F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 1. "DVLIF_ATR2F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 0. "DULIF_ATR1F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
line.long 0x34 "IER,MPWM n Interrupt Enable Register"
|
|
bitfld.long 0x34 11. "PRDWIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 10. "BOTWIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "PRDVIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 8. "BOTVIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "PRDUIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 6. "BOTUIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "WHIE_ATR6IE,Duty or ATR6 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 4. "VHIE_ATR5IE,Duty or ATR5 Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "UHIE_ATR4IE,Duty or ATR4 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 2. "WLIE_ATR3IE,Duty or ATR3 Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "VLIE_ATR2IE,Duty or ATR2 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 0. "ULIE_ATR1IE,Duty or ATR1 Match Interrupt Enable bit" "0,1"
|
|
line.long 0x38 "CNT,MPWM n Counter Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "CNT,PWM Counter Value"
|
|
line.long 0x3C "DTR,MPWM n Dead-Time Register"
|
|
bitfld.long 0x3C 15. "DTEN,Dead-time Function Enable Bit" "0,1"
|
|
bitfld.long 0x3C 14. "PSHRT,Short Protecion Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 13. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: Insert Before of PWMxH After of PWMxL,1: Insert Before of PWMxL After of PWMxH"
|
|
bitfld.long 0x3C 8.--9. "DTCLK,Dead-time Prescaler Setting Bit" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "DT,Rising/Falling Edge Dead-time Value"
|
|
line.long 0x40 "PCR,MPWM n Protection Control Register"
|
|
bitfld.long 0x40 31. "WPROTEN,Protection Input Enable" "0,1"
|
|
bitfld.long 0x40 30. "WPROTPOL,Protection Input Polarity Selection Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x40 24.--26. "WPROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 23. "VPROTEN,Protection Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 22. "VPROTPOL,Protection Input Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x40 16.--18. "VPROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 15. "PROTEN,Protection Input Enable" "0,1"
|
|
bitfld.long 0x40 14. "PROTPOL,Protection Input Polarity Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x40 8.--10. "PROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 7. "PROTIE,Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 5. "WHPROTM,Ph-W H Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 4. "VHPROTM,Ph-V H Protection Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 3. "UHPROTM,Ph-U H Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 2. "WLPROTM,Ph-W L Protection Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 1. "VLPROTM,Ph-V L Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 0. "ULPROTM,Ph-U L Protection Output Enable" "0,1"
|
|
line.long 0x44 "PSR,MPWM n Protection Status Register"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PROTKEY,Protection Clear Access Key (KEY : 0xCA)"
|
|
bitfld.long 0x44 7. "PROTIF,Protection Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x44 5. "WHPROT,Ph-W H Protection Flag" "0,1"
|
|
bitfld.long 0x44 4. "VHPROT,Ph-V H Protection Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x44 3. "UHPROT,Ph-U H Protection Flag" "0,1"
|
|
bitfld.long 0x44 2. "WLPROT,Ph-W L Protection Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x44 1. "VLPROT,Ph-V L Protection Flag" "0,1"
|
|
bitfld.long 0x44 0. "ULPROT,Ph-U L Protection Flag" "0,1"
|
|
line.long 0x48 "OCR,MPWM n Overvoltage Control Register"
|
|
bitfld.long 0x48 31. "WOVINEN,Overvoltage Input Enable" "0,1"
|
|
bitfld.long 0x48 30. "WOVINPOL,Overvoltage Input Polarity Selection Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x48 24.--26. "WOVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 23. "VOVINEN,Overvoltage Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 22. "VOVINPOL,Overvoltage Input Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x48 16.--18. "VOVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 15. "OVINEN,Overvoltage Input Enable" "0,1"
|
|
bitfld.long 0x48 14. "OVINPOL,Overvoltage Input Polarity Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x48 8.--10. "OVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 7. "OVINIE,Overvoltage Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 5. "WHOVINM,Ph-W H Protection Output Enable" "0,1"
|
|
bitfld.long 0x48 4. "VHOVINM,Ph-V H Protection Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 3. "UHOVINM,Ph-U H Protection Output Enable" "0,1"
|
|
bitfld.long 0x48 2. "WLOVINM,Ph-W L Protection Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 1. "VLOVINM,Ph-V L Protection Output Enable" "0,1"
|
|
bitfld.long 0x48 0. "ULOVINM,Ph-U L Protection Output Enable" "0,1"
|
|
line.long 0x4C "OSR,MPWM n Overvoltage Status Register"
|
|
hexmask.long.byte 0x4C 8.--15. 1. "OVINKEY,Overvoltage Clear Access Key (KEY : 0xAC)"
|
|
bitfld.long 0x4C 7. "OVINIF,Overvoltage Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 5. "WHOVIN,Ph-W H Protection Flag" "0,1"
|
|
bitfld.long 0x4C 4. "VHOVIN,Ph-V H Protection Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 3. "UHOVIN,Ph-U H Protection Flag" "0,1"
|
|
bitfld.long 0x4C 2. "WLOVIN,Ph-W L Protection Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 1. "VLOVIN,Ph-V L Protection Flag" "0,1"
|
|
bitfld.long 0x4C 0. "ULOVIN,Ph-U L Protection Flag" "0,1"
|
|
group.long 0x58++0x17
|
|
line.long 0x0 "ATR1,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x0 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x0 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
|
|
hexmask.long.word 0x0 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
|
line.long 0x4 "ATR2,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x4 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x4 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
|
|
hexmask.long.word 0x4 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
|
line.long 0x8 "ATR3,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x8 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x8 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
|
|
hexmask.long.word 0x8 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
|
line.long 0xC "ATR4,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0xC 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0xC 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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|
hexmask.long.word 0xC 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
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line.long 0x10 "ATR5,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x10 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x10 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
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bitfld.long 0x10 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
|
|
hexmask.long.word 0x10 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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|
line.long 0x14 "ATR6,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x14 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x14 19. "ATUDT,ADC Register Update Mode" "0,1"
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|
newline
|
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bitfld.long 0x14 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
|
|
hexmask.long.word 0x14 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "CR3,MPWM n Control Register 3"
|
|
bitfld.long 0x0 20.--22. "WIRQN,Ph-W Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19. "WHALT,Ph-W counter stop in current status" "0,1"
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|
newline
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bitfld.long 0x0 17. "WSTART,Ph-W Start Bit" "0,1"
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bitfld.long 0x0 16. "WEN,Ph-W Enable Bit" "0,1"
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|
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|
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bitfld.long 0x0 12.--14. "VIRQN,Ph-V Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "VHALT,Ph-V counter stop in current status" "0,1"
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|
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|
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bitfld.long 0x0 9. "VSTART,Ph-V Start Bit" "0,1"
|
|
bitfld.long 0x0 8. "VEN,Ph-V Enable Bit" "0,1"
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|
newline
|
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bitfld.long 0x0 4.--6. "UIRQN,Ph-U Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "UHALT,Ph-U counter stop in current status" "0,1"
|
|
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|
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bitfld.long 0x0 1. "USTART,Ph-U Start Bit" "0,1"
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bitfld.long 0x0 0. "UEN,Ph-V Enable Bit" "0,1"
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line.long 0x4 "CR4,MPWM n Control Register 4"
|
|
bitfld.long 0x4 19. "WCONTI,Ph-W Counter Continuous Setting" "0,1"
|
|
bitfld.long 0x4 17. "WSTOP,Ph-W Counter Stop and Reset Setting" "0,1"
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|
newline
|
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bitfld.long 0x4 16. "WDIS,Ph-W Disable Setting (Status reset)" "0,1"
|
|
bitfld.long 0x4 11. "VCONTI,Ph-V Counter Continuous Setting" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "VSTOP,Ph-V Counter Stop and Reset Setting" "0,1"
|
|
bitfld.long 0x4 8. "VDIS,Ph-W Disable Setting (Status reset)" "0,1"
|
|
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|
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bitfld.long 0x4 3. "UCONTI,Ph-U Counter Continuous Setting" "0,1"
|
|
bitfld.long 0x4 1. "USTOP,Ph-U Counter Stop and Reset Setting" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "UDIS,Ph-U Disable Setting (Status reset)" "0,1"
|
|
group.long 0x90++0xB
|
|
line.long 0x0 "PRDU,MPWM n Phase U Period Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD_U,16bit pwm period"
|
|
line.long 0x4 "PRDV,MPWM n Phase V Period Register"
|
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hexmask.long.word 0x4 0.--15. 1. "PERIOD_V,16bit pwm period"
|
|
line.long 0x8 "PRDW,MPWM n Phase W Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD_W,16bit pwm period"
|
|
group.long 0xA0++0xB
|
|
line.long 0x0 "CNTU,MPWM n Counter U Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT_U,PWM Counter Value"
|
|
line.long 0x4 "CNTV,MPWM n Counter V Register"
|
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hexmask.long.word 0x4 0.--15. 1. "CNT_V,PWM Counter Value"
|
|
line.long 0x8 "CNTW,MPWM n Counter W Register"
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hexmask.long.word 0x8 0.--15. 1. "CNT_W,PWM Counter Value"
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group.long 0xB0++0xB
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line.long 0x0 "DTRU,MPWM n Dead-Time Register"
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bitfld.long 0x0 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
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bitfld.long 0x0 23. "UDTEN,Dead-time Function Enable Bit" "0,1"
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newline
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bitfld.long 0x0 22. "UPSHRT,Short Condition Protection" "0,1"
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bitfld.long 0x0 16.--17. "UDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
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hexmask.long.byte 0x0 0.--7. 1. "UDT,Falling Dead-time Value Bit"
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line.long 0x4 "DTRV,MPWM n Dead-Time Register"
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bitfld.long 0x4 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
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bitfld.long 0x4 23. "VDTEN,Dead-time Function Enable Bit" "0,1"
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newline
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bitfld.long 0x4 22. "VPSHRT,Short Condition Protection" "0,1"
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bitfld.long 0x4 16.--17. "VDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "VDT,Falling Dead-time Value Bit"
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line.long 0x8 "DTRW,MPWM n Dead-Time Register"
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bitfld.long 0x8 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
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bitfld.long 0x8 23. "WDTEN,Dead-time Function Enable Bit" "0,1"
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newline
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bitfld.long 0x8 22. "WPSHRT,Short Condition Protection" "0,1"
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bitfld.long 0x8 16.--17. "WDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
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newline
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hexmask.long.byte 0x8 0.--7. 1. "WDT,Falling Dead-time Value Bit"
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group.long 0xC0++0xB
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line.long 0x0 "CAPCNTU,MPWM n Capture Counter Register (Ph-U)"
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bitfld.long 0x0 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
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bitfld.long 0x0 27. "CAPEN,Capture Function Enable bit" "0,1"
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newline
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hexmask.long.tbyte 0x0 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
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line.long 0x4 "CAPCNTV,MPWM n Capture Counter Register (Ph-V)"
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bitfld.long 0x4 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
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bitfld.long 0x4 27. "CAPEN,Capture Function Enable bit" "0,1"
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newline
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hexmask.long.tbyte 0x4 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
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line.long 0x8 "CAPCNTW,MPWM n Capture Counter Register (Ph-W)"
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bitfld.long 0x8 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
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bitfld.long 0x8 27. "CAPEN,Capture Function Enable bit" "0,1"
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|
newline
|
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hexmask.long.tbyte 0x8 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
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group.long 0xD0++0xB
|
|
line.long 0x0 "RCAPU,MPWM n Capture Rising Value Register (Ph-U)"
|
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bitfld.long 0x0 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x0 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
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line.long 0x4 "RCAPV,MPWM n Capture Rising Value Register (Ph-V)"
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bitfld.long 0x4 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x4 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
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line.long 0x8 "RCAPW,MPWM n Capture Rising Value Register (Ph-W)"
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bitfld.long 0x8 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x8 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
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group.long 0xE0++0xB
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line.long 0x0 "FCAPU,MPWM n Capture Falling Value Register (Ph-U)"
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bitfld.long 0x0 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x0 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
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line.long 0x4 "FCAPV,MPWM n Capture Falling Value Register (Ph-V)"
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bitfld.long 0x4 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x4 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
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line.long 0x8 "FCAPW,MPWM n Capture Falling Value Register (Ph-W)"
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bitfld.long 0x8 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
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hexmask.long.tbyte 0x8 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
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group.long 0xF0++0xB
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line.long 0x0 "SCAPU,MPWM n Sub Capture Value Register (Ph-U)"
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bitfld.long 0x0 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
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bitfld.long 0x0 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
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hexmask.long.tbyte 0x0 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
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line.long 0x4 "SCAPV,MPWM n Sub Capture Value Register (Ph-V)"
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bitfld.long 0x4 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
|
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bitfld.long 0x4 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
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hexmask.long.tbyte 0x4 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
|
line.long 0x8 "SCAPW,MPWM n Sub Capture Value Register (Ph-W)"
|
|
bitfld.long 0x8 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
|
|
bitfld.long 0x8 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
|
tree.end
|
|
tree "MPWM1"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x4F
|
|
line.long 0x0 "MR,MPWM n Mode Register"
|
|
bitfld.long 0x0 14.--15. "MOTORB,MPWM Mode Selection Bit" "0: Motor PWM Mode,1: Normal PWM Mode,?,3: Extend PWM Mode"
|
|
bitfld.long 0x0 7. "UAO,Update Timing Selection Bit" "0: Designate timing update,1: Once Duty Period Update"
|
|
newline
|
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bitfld.long 0x0 5. "TUP,DUTY Period Update Enable bit (When same period)" "0: None Update,1: Update"
|
|
bitfld.long 0x0 4. "BUP,DUTY Period Update Enable bit (When same bottom)" "0: None Update,1: Update"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "MCHMOD,Channel Symmetry/Asymmetry Mode Selection Bit" "0: 2-ch symmetry mode,1: 1-ch asymmetry mode,2: 1-ch symmetry mode,?"
|
|
bitfld.long 0x0 0. "UPDOWN,PWM Up/Down Counter Mode Selection Bit" "0: PWM Up Counter Mode(MOTORB = 1),1: Up/Down Counter Mode (MOTORB = 0 1 3)"
|
|
line.long 0x4 "OLR,MPWM n Output Level Register"
|
|
bitfld.long 0x4 13. "DOLWH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 12. "DOLVH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
newline
|
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bitfld.long 0x4 11. "DOLUH,Output level selection bit when PWMxH Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 10. "DOLWL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 9. "DOLVL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
bitfld.long 0x4 8. "DOLUL,Output level selection bit when PWMxL Disable" "0: Low Level,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 5. "WHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 4. "VHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
newline
|
|
bitfld.long 0x4 3. "UHL,Output polarity selection bit when PWMxH Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 2. "WLL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
newline
|
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bitfld.long 0x4 1. "VLL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
bitfld.long 0x4 0. "ULL,Output polarity selection bit when PWMxL Start" "0: default output level(low level),1: polarity output level(high level)"
|
|
line.long 0x8 "FOLR,MPWM n compulsion Output Register"
|
|
bitfld.long 0x8 5. "WHFL,WH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 4. "VHFL,VH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
newline
|
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bitfld.long 0x8 3. "UHFL,UH Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 2. "WLFL,WL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
newline
|
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bitfld.long 0x8 1. "VLFL,VL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
bitfld.long 0x8 0. "ULFL,UL Compulsion output level selection bit" "0: compulsion output level low,1: compulsion output level high"
|
|
line.long 0xC "PRD,MPWM n Period Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PERIOD,16bit pwm period"
|
|
line.long 0x10 "DUH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "DUTY_UH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x14 "DVH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "DUTY_VH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x18 "DWH,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "DUTY_WH,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x1C "DUL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DUTY_UL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x20 "DVL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "DUTY_VL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x24 "DWL,MPWM n DUTY x Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "DUTY_WL,16 bit PWM Duty setting bit for X output"
|
|
line.long 0x28 "CR1,MPWM n Control Register 1"
|
|
bitfld.long 0x28 8.--10. "IRQN,IRQ number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 0. "PWMEN,PWM Enable Bit" "0,1"
|
|
line.long 0x2C "CR2,MPWM n Control Register 2"
|
|
bitfld.long 0x2C 7. "HALT,PWM HALT" "0,1"
|
|
bitfld.long 0x2C 0. "PSTART,PWM Phase x counter start" "0,1"
|
|
line.long 0x30 "SR,MPWM n Status Register"
|
|
rbitfld.long 0x30 23. "WDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 20.--22. "IRQWCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x30 19. "VDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 16.--18. "IRQVCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x30 15. "UDOWN,Current PWM Counter Mode" "0,1"
|
|
rbitfld.long 0x30 12.--14. "IRQUCNT,Interrupt Counter Number of Period Match" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x30 11. "PRDWIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 10. "BOTWIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 9. "PRDVIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 8. "BOTVIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 7. "PRDUIF,PWM Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x30 6. "BOTUIF,PWM Bottom Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x30 5. "DWHIF_ATR6F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 4. "DVHIF_ATR5F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 3. "DUHIF_ATR4F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 2. "DWLIF_ATR3F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 1. "DVLIF_ATR2F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
bitfld.long 0x30 0. "DULIF_ATR1F,PWM Duty Interrupt Flag (Duty Interrupt Enable when ATR6 disable)" "0,1"
|
|
line.long 0x34 "IER,MPWM n Interrupt Enable Register"
|
|
bitfld.long 0x34 11. "PRDWIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 10. "BOTWIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "PRDVIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 8. "BOTVIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "PRDUIE,PWM Counter Period Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 6. "BOTUIE,PWM Counter Botom Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "WHIE_ATR6IE,Duty or ATR6 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 4. "VHIE_ATR5IE,Duty or ATR5 Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "UHIE_ATR4IE,Duty or ATR4 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 2. "WLIE_ATR3IE,Duty or ATR3 Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "VLIE_ATR2IE,Duty or ATR2 Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x34 0. "ULIE_ATR1IE,Duty or ATR1 Match Interrupt Enable bit" "0,1"
|
|
line.long 0x38 "CNT,MPWM n Counter Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "CNT,PWM Counter Value"
|
|
line.long 0x3C "DTR,MPWM n Dead-Time Register"
|
|
bitfld.long 0x3C 15. "DTEN,Dead-time Function Enable Bit" "0,1"
|
|
bitfld.long 0x3C 14. "PSHRT,Short Protecion Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 13. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: Insert Before of PWMxH After of PWMxL,1: Insert Before of PWMxL After of PWMxH"
|
|
bitfld.long 0x3C 8.--9. "DTCLK,Dead-time Prescaler Setting Bit" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
|
|
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|
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hexmask.long.byte 0x3C 0.--7. 1. "DT,Rising/Falling Edge Dead-time Value"
|
|
line.long 0x40 "PCR,MPWM n Protection Control Register"
|
|
bitfld.long 0x40 31. "WPROTEN,Protection Input Enable" "0,1"
|
|
bitfld.long 0x40 30. "WPROTPOL,Protection Input Polarity Selection Bit" "0,1"
|
|
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|
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bitfld.long 0x40 24.--26. "WPROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 23. "VPROTEN,Protection Input Enable" "0,1"
|
|
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|
|
bitfld.long 0x40 22. "VPROTPOL,Protection Input Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x40 16.--18. "VPROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x40 15. "PROTEN,Protection Input Enable" "0,1"
|
|
bitfld.long 0x40 14. "PROTPOL,Protection Input Polarity Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x40 8.--10. "PROTD,Protection Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 7. "PROTIE,Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 5. "WHPROTM,Ph-W H Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 4. "VHPROTM,Ph-V H Protection Output Enable" "0,1"
|
|
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|
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bitfld.long 0x40 3. "UHPROTM,Ph-U H Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 2. "WLPROTM,Ph-W L Protection Output Enable" "0,1"
|
|
newline
|
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bitfld.long 0x40 1. "VLPROTM,Ph-V L Protection Output Enable" "0,1"
|
|
bitfld.long 0x40 0. "ULPROTM,Ph-U L Protection Output Enable" "0,1"
|
|
line.long 0x44 "PSR,MPWM n Protection Status Register"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PROTKEY,Protection Clear Access Key (KEY : 0xCA)"
|
|
bitfld.long 0x44 7. "PROTIF,Protection Interrupt Status" "0,1"
|
|
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|
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bitfld.long 0x44 5. "WHPROT,Ph-W H Protection Flag" "0,1"
|
|
bitfld.long 0x44 4. "VHPROT,Ph-V H Protection Flag" "0,1"
|
|
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|
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bitfld.long 0x44 3. "UHPROT,Ph-U H Protection Flag" "0,1"
|
|
bitfld.long 0x44 2. "WLPROT,Ph-W L Protection Flag" "0,1"
|
|
newline
|
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bitfld.long 0x44 1. "VLPROT,Ph-V L Protection Flag" "0,1"
|
|
bitfld.long 0x44 0. "ULPROT,Ph-U L Protection Flag" "0,1"
|
|
line.long 0x48 "OCR,MPWM n Overvoltage Control Register"
|
|
bitfld.long 0x48 31. "WOVINEN,Overvoltage Input Enable" "0,1"
|
|
bitfld.long 0x48 30. "WOVINPOL,Overvoltage Input Polarity Selection Bit" "0,1"
|
|
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|
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bitfld.long 0x48 24.--26. "WOVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 23. "VOVINEN,Overvoltage Input Enable" "0,1"
|
|
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|
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bitfld.long 0x48 22. "VOVINPOL,Overvoltage Input Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x48 16.--18. "VOVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x48 15. "OVINEN,Overvoltage Input Enable" "0,1"
|
|
bitfld.long 0x48 14. "OVINPOL,Overvoltage Input Polarity Selection" "0,1"
|
|
newline
|
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bitfld.long 0x48 8.--10. "OVIND,Overvoltage Input Debounce" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 7. "OVINIE,Overvoltage Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x48 5. "WHOVINM,Ph-W H Protection Output Enable" "0,1"
|
|
bitfld.long 0x48 4. "VHOVINM,Ph-V H Protection Output Enable" "0,1"
|
|
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|
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bitfld.long 0x48 3. "UHOVINM,Ph-U H Protection Output Enable" "0,1"
|
|
bitfld.long 0x48 2. "WLOVINM,Ph-W L Protection Output Enable" "0,1"
|
|
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|
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bitfld.long 0x48 1. "VLOVINM,Ph-V L Protection Output Enable" "0,1"
|
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bitfld.long 0x48 0. "ULOVINM,Ph-U L Protection Output Enable" "0,1"
|
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line.long 0x4C "OSR,MPWM n Overvoltage Status Register"
|
|
hexmask.long.byte 0x4C 8.--15. 1. "OVINKEY,Overvoltage Clear Access Key (KEY : 0xAC)"
|
|
bitfld.long 0x4C 7. "OVINIF,Overvoltage Interrupt Status" "0,1"
|
|
newline
|
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bitfld.long 0x4C 5. "WHOVIN,Ph-W H Protection Flag" "0,1"
|
|
bitfld.long 0x4C 4. "VHOVIN,Ph-V H Protection Flag" "0,1"
|
|
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|
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bitfld.long 0x4C 3. "UHOVIN,Ph-U H Protection Flag" "0,1"
|
|
bitfld.long 0x4C 2. "WLOVIN,Ph-W L Protection Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4C 1. "VLOVIN,Ph-V L Protection Flag" "0,1"
|
|
bitfld.long 0x4C 0. "ULOVIN,Ph-U L Protection Flag" "0,1"
|
|
group.long 0x58++0x17
|
|
line.long 0x0 "ATR1,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x0 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x0 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
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|
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bitfld.long 0x0 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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|
hexmask.long.word 0x0 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
|
|
line.long 0x4 "ATR2,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x4 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x4 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
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bitfld.long 0x4 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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hexmask.long.word 0x4 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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|
line.long 0x8 "ATR3,MPWM n ADC Trigger Counter m Register"
|
|
bitfld.long 0x8 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x8 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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hexmask.long.word 0x8 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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|
line.long 0xC "ATR4,MPWM n ADC Trigger Counter m Register"
|
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bitfld.long 0xC 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0xC 19. "ATUDT,ADC Register Update Mode" "0,1"
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newline
|
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bitfld.long 0xC 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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hexmask.long.word 0xC 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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line.long 0x10 "ATR5,MPWM n ADC Trigger Counter m Register"
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|
bitfld.long 0x10 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x10 19. "ATUDT,ADC Register Update Mode" "0,1"
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newline
|
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bitfld.long 0x10 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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hexmask.long.word 0x10 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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line.long 0x14 "ATR6,MPWM n ADC Trigger Counter m Register"
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bitfld.long 0x14 22.--23. "ATSRC,ADC Trigger Source Counter" "0: Ph-U Counter Compare source,1: Ph-V Counter Compare source,2: Ph-W Counter Compare source,?"
|
|
bitfld.long 0x14 19. "ATUDT,ADC Register Update Mode" "0,1"
|
|
newline
|
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bitfld.long 0x14 16.--17. "ATMOD,ADC Trigger Mode Selection Register" "0: ADC Trigger Disable,1: Trigger out When up counter match,2: Trigger out When down counter match,3: Trigger out When up-down counter match"
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hexmask.long.word 0x14 0.--15. 1. "ATCNT,ADC Trigger Counter (only less then PWM Period)"
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group.long 0x80++0x7
|
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line.long 0x0 "CR3,MPWM n Control Register 3"
|
|
bitfld.long 0x0 20.--22. "WIRQN,Ph-W Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19. "WHALT,Ph-W counter stop in current status" "0,1"
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|
newline
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bitfld.long 0x0 17. "WSTART,Ph-W Start Bit" "0,1"
|
|
bitfld.long 0x0 16. "WEN,Ph-W Enable Bit" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--14. "VIRQN,Ph-V Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "VHALT,Ph-V counter stop in current status" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "VSTART,Ph-V Start Bit" "0,1"
|
|
bitfld.long 0x0 8. "VEN,Ph-V Enable Bit" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--6. "UIRQN,Ph-U Interrupt Interval Setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "UHALT,Ph-U counter stop in current status" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "USTART,Ph-U Start Bit" "0,1"
|
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bitfld.long 0x0 0. "UEN,Ph-V Enable Bit" "0,1"
|
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line.long 0x4 "CR4,MPWM n Control Register 4"
|
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bitfld.long 0x4 19. "WCONTI,Ph-W Counter Continuous Setting" "0,1"
|
|
bitfld.long 0x4 17. "WSTOP,Ph-W Counter Stop and Reset Setting" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "WDIS,Ph-W Disable Setting (Status reset)" "0,1"
|
|
bitfld.long 0x4 11. "VCONTI,Ph-V Counter Continuous Setting" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "VSTOP,Ph-V Counter Stop and Reset Setting" "0,1"
|
|
bitfld.long 0x4 8. "VDIS,Ph-W Disable Setting (Status reset)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "UCONTI,Ph-U Counter Continuous Setting" "0,1"
|
|
bitfld.long 0x4 1. "USTOP,Ph-U Counter Stop and Reset Setting" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "UDIS,Ph-U Disable Setting (Status reset)" "0,1"
|
|
group.long 0x90++0xB
|
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line.long 0x0 "PRDU,MPWM n Phase U Period Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD_U,16bit pwm period"
|
|
line.long 0x4 "PRDV,MPWM n Phase V Period Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PERIOD_V,16bit pwm period"
|
|
line.long 0x8 "PRDW,MPWM n Phase W Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD_W,16bit pwm period"
|
|
group.long 0xA0++0xB
|
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line.long 0x0 "CNTU,MPWM n Counter U Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT_U,PWM Counter Value"
|
|
line.long 0x4 "CNTV,MPWM n Counter V Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT_V,PWM Counter Value"
|
|
line.long 0x8 "CNTW,MPWM n Counter W Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_W,PWM Counter Value"
|
|
group.long 0xB0++0xB
|
|
line.long 0x0 "DTRU,MPWM n Dead-Time Register"
|
|
bitfld.long 0x0 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
|
|
bitfld.long 0x0 23. "UDTEN,Dead-time Function Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "UPSHRT,Short Condition Protection" "0,1"
|
|
bitfld.long 0x0 16.--17. "UDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "UDT,Falling Dead-time Value Bit"
|
|
line.long 0x4 "DTRV,MPWM n Dead-Time Register"
|
|
bitfld.long 0x4 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
|
|
bitfld.long 0x4 23. "VDTEN,Dead-time Function Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "VPSHRT,Short Condition Protection" "0,1"
|
|
bitfld.long 0x4 16.--17. "VDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "VDT,Falling Dead-time Value Bit"
|
|
line.long 0x8 "DTRW,MPWM n Dead-Time Register"
|
|
bitfld.long 0x8 31. "DTMDSEL,Dead-time Operation Mode Selection Bit" "0: dead-time insert before PWMxH After PWMxL,1: dead-time insert before PWMxL After PWMxH"
|
|
bitfld.long 0x8 23. "WDTEN,Dead-time Function Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "WPSHRT,Short Condition Protection" "0,1"
|
|
bitfld.long 0x8 16.--17. "WDTCLK,Dead-time Prescaler" "0: Dead-time counter is PWM CLK/2,1: Dead-time counter is PWM CLK/4,2: Dead-time counter is PWM CLK/8,3: Dead-time counter is PWM CLK/16"
|
|
newline
|
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hexmask.long.byte 0x8 0.--7. 1. "WDT,Falling Dead-time Value Bit"
|
|
group.long 0xC0++0xB
|
|
line.long 0x0 "CAPCNTU,MPWM n Capture Counter Register (Ph-U)"
|
|
bitfld.long 0x0 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
|
|
bitfld.long 0x0 27. "CAPEN,Capture Function Enable bit" "0,1"
|
|
newline
|
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hexmask.long.tbyte 0x0 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
|
|
line.long 0x4 "CAPCNTV,MPWM n Capture Counter Register (Ph-V)"
|
|
bitfld.long 0x4 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
|
|
bitfld.long 0x4 27. "CAPEN,Capture Function Enable bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
|
|
line.long 0x8 "CAPCNTW,MPWM n Capture Counter Register (Ph-W)"
|
|
bitfld.long 0x8 31. "CNTCLEAR,Capture Counter Clear Bit" "0,1"
|
|
bitfld.long 0x8 27. "CAPEN,Capture Function Enable bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "CAPCNTx,Capture Counter Value Bit"
|
|
group.long 0xD0++0xB
|
|
line.long 0x0 "RCAPU,MPWM n Capture Rising Value Register (Ph-U)"
|
|
bitfld.long 0x0 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
|
|
line.long 0x4 "RCAPV,MPWM n Capture Rising Value Register (Ph-V)"
|
|
bitfld.long 0x4 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
|
|
line.long 0x8 "RCAPW,MPWM n Capture Rising Value Register (Ph-W)"
|
|
bitfld.long 0x8 31. "RCAPFLAG,Capture Counter Flag (Clear RCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "RCAPx,Rising Capture Counter Value Bit"
|
|
group.long 0xE0++0xB
|
|
line.long 0x0 "FCAPU,MPWM n Capture Falling Value Register (Ph-U)"
|
|
bitfld.long 0x0 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
|
|
line.long 0x4 "FCAPV,MPWM n Capture Falling Value Register (Ph-V)"
|
|
bitfld.long 0x4 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
|
|
line.long 0x8 "FCAPW,MPWM n Capture Falling Value Register (Ph-W)"
|
|
bitfld.long 0x8 31. "FCAPFLAG,Capture Counter Flag (Clear FCAPx and Flag write '1')" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "FCAPx,Falling Capture Counter Value Bit"
|
|
group.long 0xF0++0xB
|
|
line.long 0x0 "SCAPU,MPWM n Sub Capture Value Register (Ph-U)"
|
|
bitfld.long 0x0 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
|
|
bitfld.long 0x0 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
|
line.long 0x4 "SCAPV,MPWM n Sub Capture Value Register (Ph-V)"
|
|
bitfld.long 0x4 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
|
|
bitfld.long 0x4 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
|
line.long 0x8 "SCAPW,MPWM n Sub Capture Value Register (Ph-W)"
|
|
bitfld.long 0x8 31. "SCAPFLAG,Sub Capture Counter Flag (Clear SCAPx and Flag write '1')" "0,1"
|
|
bitfld.long 0x8 28. "EDGESEL,External Signal Capture Edge Selection Bit" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "SCAPx,Sub Capture Counter Value Bit"
|
|
tree.end
|
|
tree.end
|
|
tree "PCU (Port Control Unit)"
|
|
base ad:0x0
|
|
tree "PA"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
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bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
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bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
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bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
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wgroup.long 0x38++0x7
|
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line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
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bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
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bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
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bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
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bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PB"
|
|
base ad:0x40001100
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PC"
|
|
base ad:0x40001200
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PD"
|
|
base ad:0x40001300
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PE"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PF"
|
|
base ad:0x40001500
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PG"
|
|
base ad:0x40001600
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR1,Port n MUX1 Selection Register"
|
|
bitfld.long 0x0 28.--30. "P7MUX,Pin 7 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "P6MUX,Pin 6 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. "P5MUX,Pin 5 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "P4MUX,Pin 4 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "P3MUX,Pin 3 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "P2MUX,Pin 2 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "P1MUX,Pin 1 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "P0MUX,Pin 0 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MR2,Port n MUX2 Selection Register"
|
|
bitfld.long 0x4 28.--30. "P15MUX,Pin 15 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "P14MUX,Pin 14 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "P13MUX,Pin 13 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "P12MUX,Pin 12 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "P11MUX,Pin 11 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "P10MUX,Pin 10 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "P9MUX,Pin 9 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "P8MUX,Pin 8 Mode Selection bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Port n Type Selection Register"
|
|
bitfld.long 0x8 30.--31. "P15,Pin 15 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "P14,Pin 14 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "P13,Pin 13 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "P12,Pin 12 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "P11,Pin 11 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "P10,Pin 10 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "P9,Pin 9 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "P8,Pin 8 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "P7,Pin 7 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,Pin 6 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "P5,Pin 5 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,Pin 4 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,Pin 3 Type Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "P2,Pin 2 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,Pin 1 Type Selection bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,Pin 0 Type Selection bit" "0,1,2,3"
|
|
line.long 0xC "PRCR,Port n Pull-up/down Selection Register"
|
|
bitfld.long 0xC 30.--31. "PUE15,Pin 15 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUE14,Pin 14 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUE13,Pin 13 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUE12,Pin 12 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUE11,Pin 11 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUE10,Pin 10 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUE9,Pin 9 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUE8,Pin 8 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUE7,Pin 7 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUE6,Pin 6 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUE5,Pin 5 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUE4,Pin 4 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUE3,Pin 3 Pull-up/down Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "PUE2,Pin 2 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUE1,Pin 1 Pull-up/down Selection bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUE0,Pin 0 Pull-up/down Selection bits" "0,1,2,3"
|
|
line.long 0x10 "DER,Port n Debounce Enable Register"
|
|
bitfld.long 0x10 15. "PDE15,Pin 15 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 14. "PDE14,Pin 14 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 13. "PDE13,Pin 13 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 12. "PDE12,Pin 12 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 11. "PDE11,Pin 11 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 10. "PDE10,Pin 10 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 9. "PDE9,Pin 9 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 8. "PDE8,Pin 8 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 7. "PDE7,Pin 7 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 6. "PDE6,Pin 6 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 5. "PDE5,Pin 5 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 4. "PDE4,Pin 4 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 3. "PDE3,Pin 3 Debounce Enable bits" "0,1"
|
|
newline
|
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bitfld.long 0x10 2. "PDE2,Pin 2 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 1. "PDE1,Pin 1 Debounce Enable bits" "0,1"
|
|
bitfld.long 0x10 0. "PDE0,Pin 0 Debounce Enable bits" "0,1"
|
|
line.long 0x14 "STR,Port n Strength Selection Register"
|
|
bitfld.long 0x14 15. "PST15,Pin 15 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 14. "PST14,Pin 14 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 13. "PST13,Pin 13 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 12. "PST12,Pin 12 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 11. "PST11,Pin 11 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 10. "PST10,Pin 10 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 9. "PST9,Pin 9 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 8. "PST8,Pin 8 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 7. "PST7,Pin 7 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 6. "PST6,Pin 6 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 5. "PST5,Pin 5 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 4. "PST4,Pin 4 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 3. "PST3,Pin 3 Strength Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "PST2,Pin 2 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 1. "PST1,Pin 1 Strength Selection bit" "0,1"
|
|
bitfld.long 0x14 0. "PST0,Pin 0 Strength Selection bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "IER,Port n Interrupt Enable Register"
|
|
bitfld.long 0x0 30.--31. "PIE15,Pin 15 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "PIE14,Pin 14 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "PIE13,Pin 13 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "PIE12,Pin 12 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PIE11,Pin 11 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "PIE10,Pin 10 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "PIE9,Pin 9 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "PIE8,Pin 8 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PIE7,Pin 7 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PIE6,Pin 6 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "PIE5,Pin 5 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PIE4,Pin 4 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PIE3,Pin 3 Interrupt Enable bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PIE2,Pin 2 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PIE1,Pin 1 Interrupt Enable bit" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PIE0,Pin 0 Interrupt Enable bit" "0,1,2,3"
|
|
line.long 0x4 "ISR,Port n Interrupt Status Register"
|
|
bitfld.long 0x4 30.--31. "PIS15,Pin 15 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "PIS14,Pin 14 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PIS13,Pin 13 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "PIS12,Pin 12 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PIS11,Pin 11 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "PIS10,Pin 10 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "PIS9,Pin 9 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "PIS8,Pin 8 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PIS7,Pin 7 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "PIS6,Pin 6 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "PIS5,Pin 5 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "PIS4,Pin 4 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PIS3,Pin 3 Interrupt Status bit" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x4 4.--5. "PIS2,Pin 2 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PIS1,Pin 1 Interrupt Status bit" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PIS0,Pin 0 Interrupt Status bit" "0,1,2,3"
|
|
line.long 0x8 "ICR,Port n Interrupt Control Register"
|
|
bitfld.long 0x8 30.--31. "PIC15,Pin 15 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "PIC14,Pin 14 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "PIC13,Pin 13 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "PIC12,Pin 12 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PIC11,Pin 11 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "PIC10,Pin 10 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "PIC9,Pin 9 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "PIC8,Pin 8 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PIC7,Pin 7 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "PIC6,Pin 6 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "PIC5,Pin 5 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "PIC4,Pin 4 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PIC3,Pin 3 Interrupt Control bit" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 4.--5. "PIC2,Pin 2 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PIC1,Pin 1 Interrupt Control bit" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PIC0,Pin 0 Interrupt Control bit" "0,1,2,3"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ODR,Port n Output Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "POD,Pin Output Data bit"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IDR,Port n Input Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PID,Port Input Data bits"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "BSR,Port n Bit Set Register"
|
|
bitfld.long 0x0 15. "BSD15,Port 15 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 14. "BSD14,Port 14 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 13. "BSD13,Port 13 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 12. "BSD12,Port 12 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 11. "BSD11,Port 11 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 10. "BSD10,Port 10 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 9. "BSD9,Port 9 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 8. "BSD8,Port 8 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 7. "BSD7,Port 7 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 6. "BSD6,Port 6 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 5. "BSD5,Port 5 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 4. "BSD4,Port 4 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 3. "BSD3,Port 3 Bit Set bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BSD2,Port 2 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 1. "BSD1,Port 1 Bit Set bits" "0,1"
|
|
bitfld.long 0x0 0. "BSD0,Port 0 Bit Set bits" "0,1"
|
|
line.long 0x4 "BCR,Port n Bit Clear Register"
|
|
bitfld.long 0x4 15. "BCD15,Port 15 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 14. "BCD14,Port 14 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 13. "BCD13,Port 13 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 12. "BCD12,Port 12 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 11. "BCD11,Port 11 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 10. "BCD10,Port 10 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 9. "BCD9,Port 9 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 8. "BCD8,Port 8 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 7. "BCD7,Port 7 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 6. "BCD6,Port 6 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 5. "BCD5,Port 5 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 4. "BCD4,Port 4 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 3. "BCD3,Port 3 Bit Clear bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BCD2,Port 2 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 1. "BCD1,Port 1 Bit Clear bits" "0,1"
|
|
bitfld.long 0x4 0. "BCD0,Port 0 Bit Clear bits" "0,1"
|
|
tree.end
|
|
tree "PORTEN"
|
|
base ad:0x40001FF0
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "EN,Port Access Enable Register"
|
|
rbitfld.long 0x0 8. "ENS,Enable Status Bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORTEN,Port Access Enable bit write sequence 0x15 0x51"
|
|
tree.end
|
|
tree.end
|
|
tree "PGA (Programmable Gain AMP)"
|
|
base ad:0x0
|
|
tree "PGA0"
|
|
base ad:0x4000B300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,PGA Control Register"
|
|
bitfld.long 0x0 16.--17. "AMPISEL,OPAMP Current Setting Bit" "0: Current 0%,1: Current 17%,2: Current -21%,3: Current -12%"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GAINSEL,OPAMP n GAIN Control Bit"
|
|
bitfld.long 0x0 1. "UGAINEN,Unit Gain Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "AMPEN,PGA Enable Bit" "0: Disable,1: Enable"
|
|
tree.end
|
|
tree "PGA1"
|
|
base ad:0x4000B304
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,PGA Control Register"
|
|
bitfld.long 0x0 16.--17. "AMPISEL,OPAMP Current Setting Bit" "0: Current 0%,1: Current 17%,2: Current -21%,3: Current -12%"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GAINSEL,OPAMP n GAIN Control Bit"
|
|
bitfld.long 0x0 1. "UGAINEN,Unit Gain Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "AMPEN,PGA Enable Bit" "0: Disable,1: Enable"
|
|
tree.end
|
|
tree "PGA2"
|
|
base ad:0x4000B308
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,PGA Control Register"
|
|
bitfld.long 0x0 16.--17. "AMPISEL,OPAMP Current Setting Bit" "0: Current 0%,1: Current 17%,2: Current -21%,3: Current -12%"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GAINSEL,OPAMP n GAIN Control Bit"
|
|
bitfld.long 0x0 1. "UGAINEN,Unit Gain Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "AMPEN,PGA Enable Bit" "0: Disable,1: Enable"
|
|
tree.end
|
|
tree.end
|
|
tree "QEI (Quadrature Encoder Interface)"
|
|
base ad:0x0
|
|
tree "QEI0"
|
|
base ad:0x4000B400
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "MR,QEI n Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "INXGATE,Index Gating Configuration"
|
|
bitfld.long 0x0 7. "QDVEL,Velocity Counter Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "DIRI,Index Counter Direction Control bit" "0: DI Status Not Affect to the counter,1: DIR Status Will Change Count Direction"
|
|
bitfld.long 0x0 5. "DIRPC,Position Counter Direction Control bit" "0: DI Status Not Affect to the counter,1: DIR Status Will Change Count Direction"
|
|
newline
|
|
bitfld.long 0x0 4. "QDRST,Reset Mode Setting Bit" "0: Reset With Maximum Position Reset,1: Reset with index pulse"
|
|
bitfld.long 0x0 3. "QDCAP,Capture Mode Setting Bit" "0: Only Ph-A Edge is Counted,1: Ph-A and Ph-B Edge are counted"
|
|
newline
|
|
bitfld.long 0x0 2. "QDSIG,Signal Mode Setting Bit" "0: Quadrature phase signal (Ph-A Ph-B),1: Clock Signal = Ph-A Direction Signal = Ph-B"
|
|
bitfld.long 0x0 1. "QDSWAP,QEI Input Signal SWAP Setting Bit" "0: No Swap,1: Swap Ph-A and Ph-B"
|
|
newline
|
|
bitfld.long 0x0 0. "QDMOD,QEI Module Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x4 "CON,QEI n Control Register"
|
|
bitfld.long 0x4 8. "INVI,Index Pulse Reverse Setting Bit" "0: None,1: Index Input Pulse Reverse"
|
|
bitfld.long 0x4 2. "RESV,Velocity Counter Init Bit" "0: None,1: Velocity Counter Init"
|
|
newline
|
|
bitfld.long 0x4 1. "RESI,Index Counter Init Bit" "0: None,1: Index Counter Init"
|
|
bitfld.long 0x4 0. "RESP,Position Counter Init Bit" "0: None,1: Position Counter Init"
|
|
line.long 0x8 "SR,QEI n Status Register"
|
|
bitfld.long 0x8 1. "Direction,Direction Status Bit" "0: Direction is reverse,1: Direction is positive"
|
|
bitfld.long 0x8 0. "Error,Error was detected in the gray code sequence" "0,1"
|
|
line.long 0xC "POS,QEI n Position Counter Register"
|
|
hexmask.long 0xC 0.--31. 1. "QEIPOS,Current Position Counter Value"
|
|
line.long 0x10 "MAX,QEI n Position Counter Maximum Register"
|
|
hexmask.long 0x10 0.--31. 1. "QEIMAX,Position Counter Maximum Value Setting Bit"
|
|
line.long 0x14 "CMP0,QEI n Position Counter Compare0 Register"
|
|
hexmask.long 0x14 0.--31. 1. "QEICMP0,Position Compare0 Value Setting Bit"
|
|
line.long 0x18 "CMP1,QEI n Position Counter Compare1 Register"
|
|
hexmask.long 0x18 0.--31. 1. "QEICMP1,Position Compare1 Value Setting Bit"
|
|
line.long 0x1C "CMP2,QEI n Position Counter Compare2 Register"
|
|
hexmask.long 0x1C 0.--31. 1. "QEICMP2,Position Compare2 Value Setting Bit"
|
|
line.long 0x20 "IDX,QEI n Index Counter Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "QEIIDX,Current Index Counter Value"
|
|
line.long 0x24 "CMPI,QEI n Index Comapre Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "QEICMPI,Index Counter Compare Value Setting Bit"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "VLR,QEI n Velocity Reload Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "QEIVLR,Velocity Timer Reload Value Bit"
|
|
line.long 0x4 "VLT,QEI n Velocity Timer Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "QEIVLT,Current Velocity Timer Value Bit"
|
|
line.long 0x8 "VLP,QEI n Velocity Pulse Counter Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "QEIVLP,Current Velocity Pulse Counter Value Bit"
|
|
line.long 0xC "VLC,QEI n Velocity Capture Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "QEIVLC,Velocity Capture Value Register"
|
|
line.long 0x10 "VLCOM,QEI n Velocity Compare Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "QEIVLCOM,Velocity Compare Value Register"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "IER,QEI n Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "VELCEN,Interrupt when a capture value smaaler than the velocity comparison value is input" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 9. "VELTEN,Interrupt when velocity timer value is '0'" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8. "IDXEN,Interrupt when Index counter same as Index comparison value" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 7. "MAXEN,Interrupt when position counter is maximum value (setting value)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2EN,Position 2 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 5. "POS1EN,Position 1 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0EN,Position 0 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 3. "ENCLKEN,Decoder Clock Pulse Occurred Flag Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 2. "ERREN,Decoder Phase Error Occurred Flag Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 1. "DIREN,Direction Change Occurred Flag Enable bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "INXEN,Index Pulse Occurred Flag Enable bit" "0: Disable,1: Enable"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "ISR,QEI n Interrupt Status Register"
|
|
bitfld.long 0x0 10. "VELC,Flag when a capture value smaaler than the velocity comparison value is input" "0,1"
|
|
bitfld.long 0x0 9. "VELT,Flag when velocity timer value is '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDX,Flag when Index counter same as Index comparison value" "0,1"
|
|
bitfld.long 0x0 7. "MAX,Flag when position counter is maximum value (setting value)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2,Position 2 Flag when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 5. "POS1,Position 1 Flag when compare value register and current counter value are the same" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0,Position 0 Flag when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 3. "ENCLK,Decoder Clock Pulse Occurred Flag Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ERR,Decoder Phase Error Occurred Flag Bit" "0,1"
|
|
bitfld.long 0x0 1. "DIR,Direction Change Occurred Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INX,Index Pulse Occurred Flag bit" "0,1"
|
|
wgroup.long 0x58++0x3
|
|
line.long 0x0 "ISCR,QEI n Interrupt Status Clear Register"
|
|
bitfld.long 0x0 10. "VELC,Flag Clear when a capture value smaaler than the velocity comparison value is input" "0,1"
|
|
bitfld.long 0x0 9. "VELT,Flag Clear when velocity timer value is '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDX,Flag Clear when Index counter same as Index comparison value" "0,1"
|
|
bitfld.long 0x0 7. "MAX,Flag Clear when position counter is maximum value (setting value)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2,Position 2 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 5. "POS1,Position 1 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0,Position 0 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 3. "ENCLK,Decoder Clock Pulse Occurred Flag Clear Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ERR,Decoder Phase Error Occurred Flag Clear Bit" "0,1"
|
|
bitfld.long 0x0 1. "DIR,Direction Change Occurred Flag Clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INX,Index Pulse Occurred Flag Clear bit" "0,1"
|
|
tree.end
|
|
tree "QEI1"
|
|
base ad:0x4000B500
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "MR,QEI n Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "INXGATE,Index Gating Configuration"
|
|
bitfld.long 0x0 7. "QDVEL,Velocity Counter Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "DIRI,Index Counter Direction Control bit" "0: DI Status Not Affect to the counter,1: DIR Status Will Change Count Direction"
|
|
bitfld.long 0x0 5. "DIRPC,Position Counter Direction Control bit" "0: DI Status Not Affect to the counter,1: DIR Status Will Change Count Direction"
|
|
newline
|
|
bitfld.long 0x0 4. "QDRST,Reset Mode Setting Bit" "0: Reset With Maximum Position Reset,1: Reset with index pulse"
|
|
bitfld.long 0x0 3. "QDCAP,Capture Mode Setting Bit" "0: Only Ph-A Edge is Counted,1: Ph-A and Ph-B Edge are counted"
|
|
newline
|
|
bitfld.long 0x0 2. "QDSIG,Signal Mode Setting Bit" "0: Quadrature phase signal (Ph-A Ph-B),1: Clock Signal = Ph-A Direction Signal = Ph-B"
|
|
bitfld.long 0x0 1. "QDSWAP,QEI Input Signal SWAP Setting Bit" "0: No Swap,1: Swap Ph-A and Ph-B"
|
|
newline
|
|
bitfld.long 0x0 0. "QDMOD,QEI Module Enable Bit" "0: Disable,1: Enable"
|
|
line.long 0x4 "CON,QEI n Control Register"
|
|
bitfld.long 0x4 8. "INVI,Index Pulse Reverse Setting Bit" "0: None,1: Index Input Pulse Reverse"
|
|
bitfld.long 0x4 2. "RESV,Velocity Counter Init Bit" "0: None,1: Velocity Counter Init"
|
|
newline
|
|
bitfld.long 0x4 1. "RESI,Index Counter Init Bit" "0: None,1: Index Counter Init"
|
|
bitfld.long 0x4 0. "RESP,Position Counter Init Bit" "0: None,1: Position Counter Init"
|
|
line.long 0x8 "SR,QEI n Status Register"
|
|
bitfld.long 0x8 1. "Direction,Direction Status Bit" "0: Direction is reverse,1: Direction is positive"
|
|
bitfld.long 0x8 0. "Error,Error was detected in the gray code sequence" "0,1"
|
|
line.long 0xC "POS,QEI n Position Counter Register"
|
|
hexmask.long 0xC 0.--31. 1. "QEIPOS,Current Position Counter Value"
|
|
line.long 0x10 "MAX,QEI n Position Counter Maximum Register"
|
|
hexmask.long 0x10 0.--31. 1. "QEIMAX,Position Counter Maximum Value Setting Bit"
|
|
line.long 0x14 "CMP0,QEI n Position Counter Compare0 Register"
|
|
hexmask.long 0x14 0.--31. 1. "QEICMP0,Position Compare0 Value Setting Bit"
|
|
line.long 0x18 "CMP1,QEI n Position Counter Compare1 Register"
|
|
hexmask.long 0x18 0.--31. 1. "QEICMP1,Position Compare1 Value Setting Bit"
|
|
line.long 0x1C "CMP2,QEI n Position Counter Compare2 Register"
|
|
hexmask.long 0x1C 0.--31. 1. "QEICMP2,Position Compare2 Value Setting Bit"
|
|
line.long 0x20 "IDX,QEI n Index Counter Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "QEIIDX,Current Index Counter Value"
|
|
line.long 0x24 "CMPI,QEI n Index Comapre Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "QEICMPI,Index Counter Compare Value Setting Bit"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "VLR,QEI n Velocity Reload Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "QEIVLR,Velocity Timer Reload Value Bit"
|
|
line.long 0x4 "VLT,QEI n Velocity Timer Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "QEIVLT,Current Velocity Timer Value Bit"
|
|
line.long 0x8 "VLP,QEI n Velocity Pulse Counter Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "QEIVLP,Current Velocity Pulse Counter Value Bit"
|
|
line.long 0xC "VLC,QEI n Velocity Capture Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "QEIVLC,Velocity Capture Value Register"
|
|
line.long 0x10 "VLCOM,QEI n Velocity Compare Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "QEIVLCOM,Velocity Compare Value Register"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "IER,QEI n Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "VELCEN,Interrupt when a capture value smaaler than the velocity comparison value is input" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 9. "VELTEN,Interrupt when velocity timer value is '0'" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8. "IDXEN,Interrupt when Index counter same as Index comparison value" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 7. "MAXEN,Interrupt when position counter is maximum value (setting value)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2EN,Position 2 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 5. "POS1EN,Position 1 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0EN,Position 0 Interrupt when compare value register and current counter value are the same" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 3. "ENCLKEN,Decoder Clock Pulse Occurred Flag Enable Bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 2. "ERREN,Decoder Phase Error Occurred Flag Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 1. "DIREN,Direction Change Occurred Flag Enable bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "INXEN,Index Pulse Occurred Flag Enable bit" "0: Disable,1: Enable"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "ISR,QEI n Interrupt Status Register"
|
|
bitfld.long 0x0 10. "VELC,Flag when a capture value smaaler than the velocity comparison value is input" "0,1"
|
|
bitfld.long 0x0 9. "VELT,Flag when velocity timer value is '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDX,Flag when Index counter same as Index comparison value" "0,1"
|
|
bitfld.long 0x0 7. "MAX,Flag when position counter is maximum value (setting value)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2,Position 2 Flag when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 5. "POS1,Position 1 Flag when compare value register and current counter value are the same" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0,Position 0 Flag when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 3. "ENCLK,Decoder Clock Pulse Occurred Flag Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ERR,Decoder Phase Error Occurred Flag Bit" "0,1"
|
|
bitfld.long 0x0 1. "DIR,Direction Change Occurred Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INX,Index Pulse Occurred Flag bit" "0,1"
|
|
wgroup.long 0x58++0x3
|
|
line.long 0x0 "ISCR,QEI n Interrupt Status Clear Register"
|
|
bitfld.long 0x0 10. "VELC,Flag Clear when a capture value smaaler than the velocity comparison value is input" "0,1"
|
|
bitfld.long 0x0 9. "VELT,Flag Clear when velocity timer value is '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDX,Flag Clear when Index counter same as Index comparison value" "0,1"
|
|
bitfld.long 0x0 7. "MAX,Flag Clear when position counter is maximum value (setting value)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "POS2,Position 2 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 5. "POS1,Position 1 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "POS0,Position 0 Flag Clear when compare value register and current counter value are the same" "0,1"
|
|
bitfld.long 0x0 3. "ENCLK,Decoder Clock Pulse Occurred Flag Clear Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ERR,Decoder Phase Error Occurred Flag Clear Bit" "0,1"
|
|
bitfld.long 0x0 1. "DIR,Direction Change Occurred Flag Clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INX,Index Pulse Occurred Flag Clear bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RNG (Random Number Generator)"
|
|
base ad:0x40000A00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,RNG Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "GCP,Generation Counter Parameter"
|
|
bitfld.long 0x0 15. "CCS,CASR Clock Selection Bit" "0: LSI,1: HSI"
|
|
bitfld.long 0x0 14. "LCS,LFSR Clock Selection Bit" "0: LSI,1: HSI"
|
|
bitfld.long 0x0 9. "ERRIE,Error Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 8. "RDYIE,RNGD Data Ready Interrupt Enable Bit" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "EN,RNG Start Bit" "0: RNG STOP,1: RNG START"
|
|
line.long 0x4 "SEED,RNG SEED Register"
|
|
hexmask.long 0x4 0.--31. 1. "SEED,RND Seed Setting Bit"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RNGD,RNG Random number data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNG_Data,Random number generation data bit"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "STAT,RNG Status Register"
|
|
bitfld.long 0x0 9. "ERRI,Error Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 8. "RDYI,RNGD Data Ready Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 1. "ERR,Error Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "RDY,RNGD Data Ready Status Bit" "0,1"
|
|
tree.end
|
|
tree "SCU (System Control Unit)"
|
|
base ad:0x40000000
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "SMR,System Mode Register"
|
|
bitfld.long 0x0 13. "LSEAON,Auto LSE operation in power down mode" "0,1"
|
|
bitfld.long 0x0 12. "HSEAON,Auto HSE operation in power down mode" "0,1"
|
|
bitfld.long 0x0 11. "PLLAON,Auto PLL operation in power down mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "HSIAON,Auto HSI operation in power down mode" "0,1"
|
|
bitfld.long 0x0 9. "LSIAON,Auto LSI operation in power down mode" "0,1"
|
|
bitfld.long 0x0 8. "VDCAON,Auto VDC operation in power down mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4.--5. "PREVMODE,Previous operation mode in current reset event" "0: Previous mode is run,1: Previous mode is sleep,2: Previous mode is powerdown,3: Previous mode is init"
|
|
line.long 0x4 "SRCR,System reset control Register"
|
|
bitfld.long 0x4 4. "STBYO,STBYO pin output polarity selection bit" "0,1"
|
|
bitfld.long 0x4 0. "SWRST,Internal soft reset enable bit" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WUER,Wake-up Source Setting Register"
|
|
bitfld.long 0x0 14. "GPIOGWUE,GPIOG Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 13. "GPIOFWUE,GPIOF Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 12. "GPIOEWUE,GPIOE Wake-up source setting" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIODWUE,GPIOD Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 10. "GPIOCWUE,GPIOC Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 9. "GPIOBWUE,GPIOB Wake-up source setting" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GPIOAWUE,GPIOA Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 3. "FRT1WUE,FRT1 Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 2. "FRT0WUE,FRT0 Wake-up source setting" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WDTWUE,WDT Wake-up source setting" "0,1"
|
|
bitfld.long 0x0 0. "LVDWUE,LVD Wake-up source setting" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "WUSR,Wake-up Source Status Register"
|
|
bitfld.long 0x0 14. "GPIOGWU,GPIOG Wake-up source status" "0,1"
|
|
bitfld.long 0x0 13. "GPIOFWU,GPIOF Wake-up source status" "0,1"
|
|
bitfld.long 0x0 12. "GPIOEWU,GPIOE Wake-up source status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIODWU,GPIOD Wake-up source status" "0,1"
|
|
bitfld.long 0x0 10. "GPIOCWU,GPIOC Wake-up source status" "0,1"
|
|
bitfld.long 0x0 9. "GPIOBWU,GPIOB Wake-up source status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GPIOAWU,GPIOA Wake-up source status" "0,1"
|
|
bitfld.long 0x0 3. "FRT1WU,FRT1 Wake-up source status" "0,1"
|
|
bitfld.long 0x0 2. "FRT0WU,FRT0 Wake-up source status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WDTWU,WDT Wake-up source status" "0,1"
|
|
bitfld.long 0x0 0. "LVDWU,LVD Wake-up source status" "0,1"
|
|
group.long 0x18++0x1F
|
|
line.long 0x0 "RSER,Reset Source Setting Register"
|
|
bitfld.long 0x0 9. "LOCKUPRST,CPU Lock up reset setting bit" "0,1"
|
|
bitfld.long 0x0 7. "PINRST,External Pin reset setting bit" "0,1"
|
|
bitfld.long 0x0 6. "CPURST,CPU request reset setting bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWRST,Software reset setting bit" "0,1"
|
|
bitfld.long 0x0 4. "WDTRST,WDT reset setting bit" "0,1"
|
|
bitfld.long 0x0 3. "MCKFRST,MCLK Clock Fail reset setting bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LSEFRST,LSE Clock Fail reset setting bit" "0,1"
|
|
bitfld.long 0x0 1. "HSEFRST,HSE Clock Fail reset setting bit" "0,1"
|
|
bitfld.long 0x0 0. "LVDRST,LVD reset setting bit" "0,1"
|
|
line.long 0x4 "RSSR,Reset Source Status Register"
|
|
bitfld.long 0x4 9. "LOCKUPRST,CPU Lock up reset Status bit" "0,1"
|
|
bitfld.long 0x4 8. "PORST,POR Status bit" "0,1"
|
|
bitfld.long 0x4 7. "PINRST,External Pin reset Status bit" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "CPURST,CPU request reset Status bit" "0,1"
|
|
bitfld.long 0x4 5. "SWRST,Software reset Status bit" "0,1"
|
|
bitfld.long 0x4 4. "WDTRST,WDT reset Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKFRST,MCLK Clock Fail reset Status bit" "0,1"
|
|
bitfld.long 0x4 2. "LSEFRST,LSE Clock Fail reset Status bit" "0,1"
|
|
bitfld.long 0x4 1. "HSEFRST,HSE Clock Fail reset Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LVDRST,LVD reset Status bit" "0,1"
|
|
line.long 0x8 "PRER1,Peripheral Reset Setting Register1"
|
|
bitfld.long 0x8 29. "QEI1,QEI1 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 28. "QEI0,QEI0 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 25. "TIMER9,TIMER9 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "TIMER8,TIMER8 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 23. "TIMER7,TIMER7 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 22. "TIMER6,TIMER6 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "TIMER5,TIMER5 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 20. "TIMER4,TIMER4 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 19. "TIMER3,TIMER3 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "TIMER2,TIMER2 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 17. "TIMER1,TIMER1 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 16. "TIMER0,TIMER0 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "GPIOG,GPIOG Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 13. "GPIOF,GPIOF Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 12. "GPIOE,GPIOE Reset Mask bit" "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "GPIOD,GPIOD Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 10. "GPIOC,GPIOC Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 9. "GPIOB,GPIOB Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "GPIOA,GPIOA Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 7. "FRT1,FRT1 Reset Mask bit" "0,1"
|
|
bitfld.long 0x8 6. "FRT0,FRT0 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DMA,DMA Reset Mask bit" "0,1"
|
|
line.long 0xC "PRER2,Peripheral Reset Setting Register2"
|
|
bitfld.long 0xC 31. "RNG,RNG Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 30. "AES,AES Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 29. "CRC,CRC-32 Reset Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 28. "COMPARATOR,COMPARATOR Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 26. "CAN,CAN Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 24. "PGA,PGA Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "ADC2,ADC2 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 21. "ADC1,ADC1 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 20. "ADC0,ADC0 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MPWM1,MPWM1 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 16. "MPWM0,MPWM0 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 13. "UART5,UART5 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "UART4,UART4 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 11. "UART3,UART3 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 10. "UART2,UART2 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "UART1,UART1 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 8. "UART0,UART0 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 5. "I2C1,I2C1 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "I2C0,I2C0 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 2. "SPI2,SPI2 Reset Mask bit" "0,1"
|
|
bitfld.long 0xC 1. "SPI1,SPI1 Reset Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "SPI0,SPI0 Reset Mask bit" "0,1"
|
|
line.long 0x10 "PER1,Peripheral Enable Register1"
|
|
bitfld.long 0x10 29. "QEI1,QEI1 Enable bit" "0,1"
|
|
bitfld.long 0x10 28. "QEI0,QEI0 Enable bit" "0,1"
|
|
bitfld.long 0x10 25. "TIMER9,TIMER9 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "TIMER8,TIMER8 Enable bit" "0,1"
|
|
bitfld.long 0x10 23. "TIMER7,TIMER7 Enable bit" "0,1"
|
|
bitfld.long 0x10 22. "TIMER6,TIMER6 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "TIMER5,TIMER5 Enable bit" "0,1"
|
|
bitfld.long 0x10 20. "TIMER4,TIMER4 Enable bit" "0,1"
|
|
bitfld.long 0x10 19. "TIMER3,TIMER3 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "TIMER2,TIMER2 Enable bit" "0,1"
|
|
bitfld.long 0x10 17. "TIMER1,TIMER1 Enable bit" "0,1"
|
|
bitfld.long 0x10 16. "TIMER0,TIMER0 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "GPIOG,GPIOG Enable bit" "0,1"
|
|
bitfld.long 0x10 13. "GPIOF,GPIOF Enable bit" "0,1"
|
|
bitfld.long 0x10 12. "GPIOE,GPIOE Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIOD,GPIOD Enable bit" "0,1"
|
|
bitfld.long 0x10 10. "GPIOC,GPIOC Enable bit" "0,1"
|
|
bitfld.long 0x10 9. "GPIOB,GPIOB Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "GPIOA,GPIOA Enable bit" "0,1"
|
|
bitfld.long 0x10 7. "FRT1,FRT1 Enable bit" "0,1"
|
|
bitfld.long 0x10 6. "FRT0,FRT0 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "DMA,DMA Enable bit" "0,1"
|
|
line.long 0x14 "PER2,Peripheral Enable Register2"
|
|
bitfld.long 0x14 31. "RNG,RNG Enable bit" "0,1"
|
|
bitfld.long 0x14 30. "AES,AES Enable bit" "0,1"
|
|
bitfld.long 0x14 29. "CRC,CRC32 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. "COMPARATOR,COMPARATOR Enable bit" "0,1"
|
|
bitfld.long 0x14 26. "CAN,CAN Enable bit" "0,1"
|
|
bitfld.long 0x14 24. "PGA,PGA Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. "ADC2,ADC2 Enable bit" "0,1"
|
|
bitfld.long 0x14 21. "ADC1,ADC1 Enable bit" "0,1"
|
|
bitfld.long 0x14 20. "ADC0,ADC0 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "MPWM1,MPWM1 Enable bit" "0,1"
|
|
bitfld.long 0x14 16. "MPWM0,MPWM0 Enable bit" "0,1"
|
|
bitfld.long 0x14 13. "UART5,UART5 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "UART4,UART4 Enable bit" "0,1"
|
|
bitfld.long 0x14 11. "UART3,UART3 Enable bit" "0,1"
|
|
bitfld.long 0x14 10. "UART2,UART2 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "UART1,UART1 Enable bit" "0,1"
|
|
bitfld.long 0x14 8. "UART0,UART0 Enable bit" "0,1"
|
|
bitfld.long 0x14 5. "I2C1,I2C1 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "I2C0,I2C0 Enable bit" "0,1"
|
|
bitfld.long 0x14 2. "SPI2,SPI2 Enable bit" "0,1"
|
|
bitfld.long 0x14 1. "SPI1,SPI1 Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SPI0,SPI0 Enable bit" "0,1"
|
|
line.long 0x18 "PCER1,Peripheral Clock Enable Register1"
|
|
bitfld.long 0x18 29. "QEI1,QEI1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 28. "QEI0,QEI0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 25. "TIMER9,TIMER9 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "TIMER8,TIMER8 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 23. "TIMER7,TIMER7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 22. "TIMER6,TIMER6 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "TIMER5,TIMER5 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 20. "TIMER4,TIMER4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 19. "TIMER3,TIMER3 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "TIMER2,TIMER2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 17. "TIMER1,TIMER1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 16. "TIMER0,TIMER0 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "GPIOG,GPIOG Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 13. "GPIOF,GPIOF Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 12. "GPIOE,GPIOE Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "GPIOD,GPIOD Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 10. "GPIOC,GPIOC Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 9. "GPIOB,GPIOB Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "GPIOA,GPIOA Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 7. "FRT1,FRT1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x18 6. "FRT0,FRT0 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "DMA,DMA Clock Enable bit" "0,1"
|
|
line.long 0x1C "PCER2,Peripheral Clock Enable Register2"
|
|
bitfld.long 0x1C 31. "RNG,RNG Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 30. "AES,AES Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 29. "CRC,CRC32 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 28. "COMPARATOR,COMPARATOR Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 26. "CAN,CAN Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 24. "PGA,PGA Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "ADC2,ADC2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 21. "ADC1,ADC1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 20. "ADC0,ADC0 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 17. "MPWM1,MPWM1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 16. "MPWM0,MPWM0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 13. "UART5,UART5 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 12. "UART4,UART4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 11. "UART3,UART3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 10. "UART2,UART2 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "UART1,UART1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 8. "UART0,UART0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "I2C1,I2C1 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "I2C0,I2C0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "SPI2,SPI2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "SPI1,SPI1 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "SPI0,SPI0 Clock Enable bit" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CSCR,Clock Source Control Register"
|
|
bitfld.long 0x0 7. "LSECON,Low Speed External Sub Crystal Control bit" "0,1"
|
|
bitfld.long 0x0 5. "LSICON,Low Speed Internal Ring Oscillator Control bit" "0,1"
|
|
bitfld.long 0x0 3. "HSICON,High Speed Internal Oscillator Control bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HSECON,High Speed External Main Crystal Control bit" "0,1"
|
|
line.long 0x4 "SCCR,System clock control register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HCLKDIV,HCLK input clock divide bit"
|
|
bitfld.long 0x4 16.--18. "PCLKDIV,PCLK input clock divide bit" "0: HCLK=MCLK_div_1,1: PCLK=HCLK_div_2,2: PCLK=HCLK_div_4,3: PCLK=HCLK_div_8,4: PCLK=HCLK_div_16,?,?,?"
|
|
bitfld.long 0x4 12. "PLLCLKSEL,PLL Input clock selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "PLLPREDIV,PLL Input clock divide bit" "0: PLL Input clock div 1,1: PLL Input clock div 2,2: PLL Input clock div 4,3: PLL Input clock div 8"
|
|
bitfld.long 0x4 0.--2. "MCLKSEL,System Clock Selection bit" "0: system clock is LSI,1: system clock is LSE,2: system clock is HSI,?,?,?,6: system clock is HSE,7: system clock is PLL"
|
|
line.long 0x8 "CMR,Clock Monitoring Register"
|
|
bitfld.long 0x8 15. "MCLKREC,MCLK auto recovery" "0,1"
|
|
bitfld.long 0x8 11. "LSEMNT,LSE Monitoring Enable bit" "0,1"
|
|
bitfld.long 0x8 10. "LSEIE,LSE Fail Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "LSEFAIL,LSE Fail Interrupt Flag bit" "0,1"
|
|
rbitfld.long 0x8 8. "LSESTS,LSE Status bit" "0,1"
|
|
bitfld.long 0x8 7. "MCLKMNT,MCLK Monitoring Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MCLKIE,MCLK Fail Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 5. "MCLKFAIL,MCLK Fail Interrupt Flag bit" "0,1"
|
|
rbitfld.long 0x8 4. "MCLKSTS,MCLK Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "HSEMNT,HSE Monitoring Enable bit" "0,1"
|
|
bitfld.long 0x8 2. "HSEIE,HSE Fail Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 1. "HSEFAIL,HSE Fail Interrupt Flag bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 0. "HSESTS,HSE Status bit" "0,1"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "COR,Clock Output Setting Register"
|
|
bitfld.long 0x0 5.--7. "CLKOINSEL,Ouput Clock Selection bit" "0: Output clock is LSI,1: Output clock is LSE,?,?,4: Output clock is MCLK,5: Output clock is HSI,6: Output clock is HSE,7: Output clock is PLL"
|
|
bitfld.long 0x0 4. "CLKOEN,Clock Output Enable bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLKODIV,Clock Output divide Setting bit"
|
|
line.long 0x4 "NMICR,NMI Control Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NMISRC,NMI Source Selection bits"
|
|
bitfld.long 0x4 15. "NMIINEN,NMI Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "PROT1EN,MPWM1 Protection Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVP1EN,MPWM1 Over Voltage Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
bitfld.long 0x4 4. "PROT0EN,MPWM0 Protection Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
bitfld.long 0x4 3. "OVP0EN,MPWM0 Over Voltage Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WDTINTEN,WDT Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
bitfld.long 0x4 1. "MCLKFAILEN,MCLK Fail Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "LVDEN,LVD Interrupt Enable bit for NMI Interrupt" "0,1"
|
|
line.long 0x8 "NMISR,NMI Status Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "WTIDKY,NMI Status Register Write Identification Key (0x8C)"
|
|
rbitfld.long 0x8 15. "NMIINTSTS,NMI Interrupt Status bit(Not Flag)" "0,1"
|
|
bitfld.long 0x8 6. "PROT1STS,MPWM1 Protection Interrupt Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVP1STS,MPWM1 Over Voltage Interrupt Status bit" "0,1"
|
|
bitfld.long 0x8 4. "PROT0STS,MPWM0 Protection Interrupt Status bit" "0,1"
|
|
bitfld.long 0x8 3. "OVP0STS,MPWM0 Over Voltage Interrupt Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "WDTINTSTS,WDT Interrupt Status bit" "0,1"
|
|
bitfld.long 0x8 1. "MCLKFAILSTS,MCLK Fail Interrupt Status bit" "0,1"
|
|
bitfld.long 0x8 0. "LVDSTS,LVD Interrupt Status bit" "0,1"
|
|
group.long 0x60++0x13
|
|
line.long 0x0 "PLLCON,PLL Control Register"
|
|
rbitfld.long 0x0 31. "LOCKSTS,PLL Lock Status Bit" "0,1"
|
|
bitfld.long 0x0 26.--27. "PLLICP,PLL Charge Pump Current Option" "0: Charge Pump Current,1: Charge Pump Current,2: Charge Pump Current,3: Charge Pump Current"
|
|
bitfld.long 0x0 24.--25. "PLLVCOC,PLL VCO Bias Current Option" "0: VCO Bias Current X 1/4,1: VCO Bias Current X 1/2,2: VCO Bias Current X 1,3: VCO Bias Current X 2"
|
|
newline
|
|
bitfld.long 0x0 23. "PLLRSTB,PLL Reset bit" "0,1"
|
|
bitfld.long 0x0 22. "PLLEN,PLL Enable bit" "0,1"
|
|
bitfld.long 0x0 21. "BYPASSB,PLL Bypass Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PLLMODE,PLL VCO Mode Selection bit" "0,1"
|
|
bitfld.long 0x0 16.--18. "PREDIV,FIN Predivider bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. "POSTDIV1,PLL Feedback control 1(N1) bit"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "POSTDIV2,PLL Feedback control 2(N2) bit"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OUTDIV,Output divider Control(P) bit"
|
|
line.long 0x4 "VDCCON,VDC Control Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "VDCWDLY,VDC Warm-up Delay Count Value Bit"
|
|
line.long 0x8 "LVICR,Low Voltage Indicator Control Register"
|
|
bitfld.long 0x8 7. "LVIEN,LVI Enable Bit" "0,1"
|
|
bitfld.long 0x8 5. "LVIINTEN,LVI Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x8 4. "LVIAON,LVI Operation Control Bit in Deep Sleep Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "LVIVS,LVI Voltage Selection Bit"
|
|
line.long 0xC "LVISR,Low Voltage Indicator Status Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "WTIDKY,LVI Status Write Identification Key (0x7A)"
|
|
bitfld.long 0xC 5. "LVIIFLAG,LVI Interrupt Flag Bit" "0,1"
|
|
rbitfld.long 0xC 0. "LVIINTSTS,LVI Interrupt Status Bit" "0,1"
|
|
line.long 0x10 "LVRCR,Low Voltage Reset Control Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "LVREN,LVR Enable Bit"
|
|
bitfld.long 0x10 4. "LVRAON,LVR Enable Bit" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "LVRVS,LVR Voltage Selection Bit"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "EOSCR,External Oscillator Control Register"
|
|
bitfld.long 0x0 24.--25. "LSEISEL,LSE Current Capability Selection" "0,1,2,3"
|
|
bitfld.long 0x0 16. "LSENFEN,LSE Noise Filter Enable Bit" "0,1"
|
|
bitfld.long 0x0 8.--9. "HSEISEL,HSE Current Capability Selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "HSENFEN,HSE Noise Filter Enable Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "HSENFSEL,HSE Noise Filter Selection" "0,1,2,3"
|
|
group.long 0x90++0x1B
|
|
line.long 0x0 "MCCR1,MISC Clock Control Register1"
|
|
bitfld.long 0x0 24.--26. "WDTCSEL,WDT Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x0 16.--23. 1. "WDTCDIV,WDT Clock N divider"
|
|
bitfld.long 0x0 8.--10. "STCSEL,SYSTIC Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "STCDIV,SYSTIC Clock N divider"
|
|
line.long 0x4 "MCCR2,MISC Clock Control Register2"
|
|
bitfld.long 0x4 24.--26. "MPWM1CSEL,MPWM1 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x4 16.--23. 1. "MPWM1CDIV,MPWM1 Clock N divider"
|
|
bitfld.long 0x4 8.--10. "MPWM0CSEL,MPWM0 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "MPWM0CDIV,MPWM0 Clock N divider"
|
|
line.long 0x8 "MCCR3,MISC Clock Control Register3"
|
|
bitfld.long 0x8 24.--26. "TIMER59CSEL,TIMER5-9 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x8 16.--23. 1. "TIMER59CDIV,TIMER5-9 Clock N divider"
|
|
bitfld.long 0x8 8.--10. "TIMER04CSEL,TIMER0-4 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "TIMER04CDIV,TIMER0-4 Clock N divider"
|
|
line.long 0xC "MCCR4,MISC Clock Control Register4"
|
|
bitfld.long 0xC 24.--26. "PGADCSEL,Port A-B Debounce Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PGADCDIV,Port A-B debounce Clock N divider"
|
|
bitfld.long 0xC 8.--10. "ADCCSEL,ADC Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "ADCCDIV,ADC Clock N divider"
|
|
line.long 0x10 "MCCR5,MISC Clock Control Register5"
|
|
bitfld.long 0x10 24.--26. "PGCDCSEL,Port E-G Debounce Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x10 16.--23. 1. "PGCDCDIV,Port E-G debounce Clock N divider"
|
|
bitfld.long 0x10 8.--10. "PGBDCSEL,Port C-D debounce Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PGBDCDIV,Port C-D debounce Clock N divider"
|
|
line.long 0x14 "MCCR6,MISC Clock Control Register6"
|
|
bitfld.long 0x14 24.--26. "FRT1CSEL,FRT1 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x14 16.--23. 1. "FRT1CDIV,FRT1 Clock N divider"
|
|
bitfld.long 0x14 8.--10. "FRT0CSEL,FRT0 Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "FRT0CDIV,FRT0 Clock N divider"
|
|
line.long 0x18 "MCCR7,MISC Clock Control Register7"
|
|
bitfld.long 0x18 24.--26. "UARTCSEL,UART Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
hexmask.long.byte 0x18 16.--23. 1. "UARTCDIV,UART Clock N divider"
|
|
bitfld.long 0x18 8.--10. "CANCSEL,CAN Clock Source Selection Bit" "0: Clock Source is LSI,1: Clock Source is LSE,?,?,4: Clock Source is MCLK,5: Clock Source is HSI,6: Clock Source is HSE,7: Clock Source is PLL"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "CANCDIV,CAN Clock N divider"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SYSTEN,System Access Key Register"
|
|
rbitfld.long 0x0 8. "ENS,Enable Status Bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SYSTEN,System Enable bit"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI0"
|
|
base ad:0x40009000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Received Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 18. "DTXIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "DRXIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
|
|
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
|
|
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
|
|
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
|
|
line.long 0xC "EN,SPI n Enable Register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
|
|
line.long 0x10 "LR,SPI n Delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40009100
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Received Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 18. "DTXIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "DRXIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
|
|
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
|
|
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
|
|
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
|
|
line.long 0xC "EN,SPI n Enable Register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
|
|
line.long 0x10 "LR,SPI n Delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x40009200
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Received Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 18. "DTXIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "DRXIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
|
|
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
|
|
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
|
|
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
|
|
line.long 0xC "EN,SPI n Enable Register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
|
|
line.long 0x10 "LR,SPI n Delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
|
|
tree.end
|
|
tree.end
|
|
tree "TIMER (16-bit Timer)"
|
|
base ad:0x0
|
|
tree "TIMER0"
|
|
base ad:0x40003000
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER1"
|
|
base ad:0x40003040
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER2"
|
|
base ad:0x40003080
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER3"
|
|
base ad:0x400030C0
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER4"
|
|
base ad:0x40003100
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER5"
|
|
base ad:0x40003140
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER6"
|
|
base ad:0x40003180
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER7"
|
|
base ad:0x400031C0
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER8"
|
|
base ad:0x40003200
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree "TIMER9"
|
|
base ad:0x40003240
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CR1,Timer Control Register1"
|
|
bitfld.long 0x0 14.--15. "TRGMOD,Timer ADC Trigger Mode Selection Bit" "0: GRA Value Trigger Mode (Normal Mode),?,2: TRGPNT Value Trigger Mode,3: GRA TRGPNT Value Both Trigger Mode"
|
|
bitfld.long 0x0 13. "UAO,GRA GRB Update Mode Selection bit" "0: Write Value Apply to next period,1: Write value apply to current period"
|
|
bitfld.long 0x0 12. "OUTPOL,TIMER Output Polarity Selection Bit" "0: Normal Output,1: Polairty Output"
|
|
newline
|
|
bitfld.long 0x0 11. "IOSEL,TIMER Input/Output Selection Bit" "0: Timer Input Port Setting,1: Timer Output Port Setting"
|
|
bitfld.long 0x0 8. "ADCTRGEN,ADC Trigger Source Enable Bit" "0: No Used,1: Used"
|
|
bitfld.long 0x0 7. "STARTLVL,Interval/PWM/One-shot Mode Initial output value setting" "0: Output Start Low,1: Output Start High"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CKSEL,Timer Clock Source Selection bit" "0: Counter Clock is PCLK/2,1: Counter Clock is PCLK/4,2: Counter Clock is PCLK/16,3: Counter Clock is PCLK/64,4: Counter Clock is EXT0(MCCR3),?,6: Counter Clock is TnC (input pin),?"
|
|
bitfld.long 0x0 2.--3. "CLRMOD,Capture Mode Clear Selection bit" "0: Rising Edge Clear Mode,1: Falling Edge Clear Mode,2: Rising/Falling Edge Clear Mode,3: Not Clear Mode"
|
|
bitfld.long 0x0 0.--1. "MODE,TIMER Operating Mode Control Bit" "0: Timer is Interval Mode,1: Timer is PWM Mode,2: Timer is One-Shot Mode,3: Timer is Capture Mode"
|
|
line.long 0x4 "CR2,Timer Control Register2"
|
|
bitfld.long 0x4 1. "TCLR,Timer Counter Register Clear Bit" "0,1"
|
|
bitfld.long 0x4 0. "TEN,Timer Counter" "0: Timer Disable,1: Timer Enable"
|
|
line.long 0x8 "PRS,Timer Prescaler Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "PRS,Counter Clock Prescaler Value TCLK=CLOCK_IN/(PRS+1)"
|
|
line.long 0xC "GRA,Timer General Data Register A"
|
|
hexmask.long.word 0xC 0.--15. 1. "GRA,GRA Value Bit"
|
|
line.long 0x10 "GRB,Timer General Data Register B"
|
|
hexmask.long.word 0x10 0.--15. 1. "GRB,GRB Balue Bit"
|
|
line.long 0x14 "CNT,Timer Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Timer Counter bits."
|
|
line.long 0x18 "SR,Timer Status Register"
|
|
bitfld.long 0x18 2. "MFA,GRA Match Flag" "0,1"
|
|
bitfld.long 0x18 1. "MFB,GRB Match Flag" "0,1"
|
|
bitfld.long 0x18 0. "OVF,Counter Overflow Flag" "0,1"
|
|
line.long 0x1C "IER,Timer Interrupt Enable Register"
|
|
bitfld.long 0x1C 2. "MAIE,GRA Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "MBIE,GRB Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "OVIE,Counter Overflow Interrupt Enable bit" "0,1"
|
|
line.long 0x20 "TRGPNT,Timer Trigger Point Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TRGPNT,Timer Trigger Point Value Bit"
|
|
line.long 0x24 "SYNC,Timer Sync Setting Register"
|
|
bitfld.long 0x24 29. "T9SYNCB,Timer 9 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 28. "T8SYNCB,Timer 8 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 27. "T7SYNCB,Timer 7 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 26. "T6SYNCB,Timer 6 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 25. "T5SYNCB,Timer 5 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 24. "T4SYNCB,Timer 4 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 23. "T3SYNCB,Timer 3 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 22. "T2SYNCB,Timer 2 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 21. "T1SYNCB,Timer 1 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
bitfld.long 0x24 20. "T0SYNCB,Timer 0 sync enable bit" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 17. "SSYNC,Timer n Counter Start Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
bitfld.long 0x24 16. "CSYNC,Timer n Counter Clear Sync" "0: SYNC Disable,1: SYNC Enable"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "SYNCDLY,SYNC Delay Counter Value Setting Bit"
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x40008000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40008100
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x40008200
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0x40008300
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "UART4"
|
|
base ad:0x40008400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "UART5"
|
|
base ad:0x40008500
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IER,UARTn Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA Transmitter complete interrupt allow" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver over Interrupt allow" "0,1"
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "IIR,UARTn Interrupt ID Register"
|
|
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID bit" "0,1"
|
|
bitfld.long 0x0 1.--3. "IID,UARTn Interrupt ID bits. Note: The UARTn supports 3-priority interrupt generation and the interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below. - Receive line.." "?,?,?,3: priority interrupt generation and the interrupt..,?,?,?,?"
|
|
bitfld.long 0x0 0. "IPEN,Interrupt Pending bit" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LCR,UARTn Line Control Register"
|
|
bitfld.long 0x0 6. "BREAK,Transfer Break Control bit. The TXDn pin will be driven at low state in order to notice" "0,1"
|
|
bitfld.long 0x0 5. "STICKP,Force Parity bit. This bit is effective when the PEN bit is set to '1b'" "0,1"
|
|
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection bit" "0,1"
|
|
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection bits" "0: 5bit data,1: 6bit data,2: 7bit data,3: 8bit data"
|
|
line.long 0x4 "DCR,UARTn Data Control Register"
|
|
bitfld.long 0x4 3. "RXINV,Rx Data Polarity selection" "0,1"
|
|
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection bit" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "LSR,UARTn Line Status Register"
|
|
bitfld.long 0x0 6. "TEMT,Transmit Empty bit" "0,1"
|
|
bitfld.long 0x0 5. "THRE,Transmit Holding Empty bit. Note: This bit will be set to '1b' when it starts transmit." "0,1"
|
|
bitfld.long 0x0 4. "BI,Break Condition Indication bit" "0,1"
|
|
bitfld.long 0x0 3. "FE,Frame Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 2. "PE,Parity Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 1. "OE,Overrun Error Indicator bit" "0,1"
|
|
bitfld.long 0x0 0. "DR,Data Receive Indicator bit" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value. Baud rate = fUARTnCLK/(16 x BDR[15:0] x 2). Note: The UART block won't work if the BDR[15:0] == 0x0000."
|
|
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value. 0 = Disable fraction counter N = Fraction compensation mode is operating. Fraction counter is incremented by FCNT. FCNT = Float * 256 Note: 8-bit fractional counter will count up by FCNT value every (baud rate)/16 period and.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value. Dummy delay can be inserted between 2 Continuous Transmits. Wait Time = WAITVAL[2:0]/(Baud Rate)" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LR,Watch-dog Timer Load Register"
|
|
hexmask.long 0x0 0.--31. 1. "WDTLR,WDT Load Value Bits"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CNT,Watch-dog Timer Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "WDTCNT,Watch-dog Timer Counter Value Bits"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CON,Watch-dog Timer Control Register"
|
|
bitfld.long 0x0 15. "WDBG,Watch-dog Timer Control in debugging mode" "0,1"
|
|
bitfld.long 0x0 8. "WUF,Watch-dog Timer Underflow Flag Bit when write WDTLR register this bit is cleared." "0,1"
|
|
bitfld.long 0x0 7. "WDTIE,Watch-dog Timer Underflow Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "WDTRE,Watch-dog Timer Underflow Reset Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "WDTEN,Watch-dog Timer Counter Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CKSEL,Watch-dog Timer Clock Source Selection Bit" "0,1"
|
|
bitfld.long 0x0 0.--2. "WPRS,Watch-dog Timer Counter Clock Prescaler bit" "0: WDT Input Clock divide by 1,1: WDT Input Clock divide by 4,2: WDT Input Clock divide by 8,3: WDT Input Clock divide by 16,4: WDT Input Clock divide by 32,5: WDT Input Clock divide by 64,6: WDT Input Clock divide by 128,7: WDT Input Clock divide by 256"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "AEN,Watch-dog Timer Master Lock/Reload Register"
|
|
rbitfld.long 0x0 16. "ENS,Enable status bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "AEN,WDT Master Lock Enable Register (Access = 0xA55A Reload = 0x555A)"
|
|
tree.end
|
|
AUTOINDENT.OFF
|