532 lines
23 KiB
Plaintext
532 lines
23 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: S32R41 Specific Menu
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; @Props: Released
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; @Author: KWI, JON, NEJ
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; @Changelog: 2020-10-16 KWI
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; 2021-07-29 KWI
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; 2022-01-20 JON
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; 2022-07-20 NEJ
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; 2022-10-27 NEJ
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; 2022-11-25 NEJ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A53, Cortex-M7F
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; @Chip: S32R41-A53, S32R41-M7-0, S32R41-M7-1, S32R41-M7-HSE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mens32r41.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA53")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-M7F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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popup "IVT Table (QSPI)"
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(
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menuitem "IVT (QSPI)" "per , ""IVT Table,IVT (QSPI)"""
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menuitem "DCD" "per , ""IVT Table,IVT (QSPI),DCD Registers"""
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menuitem "DCD Self-Test" "per , ""IVT Table,IVT (QSPI),DCD Self-Test Registers"""
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menuitem "BOOT" "per , ""IVT Table,IVT (QSPI),BOOT Registers"""
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)
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menuitem "A53_GPR" "per , ""A53_GPR"""
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menuitem "ADC;SAR_ADC" "per , ""ADC (SAR_ADC)"""
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menuitem "ATP" "per , ""ATP"""
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popup "BOOT;Boot_BMR"
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(
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menuitem "BOOT_BMR" "per , ""BOOT (Boot_BMR),BOOT_BMR"""
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menuitem "BOOT_POR" "per , ""BOOT (Boot_BMR),BOOT_POR"""
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)
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popup "CM7_GPR"
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(
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menuitem "CM7_GPR_0" "per , ""CM7_GPR,CM7_GPR_0"""
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menuitem "CM7_GPR_1" "per , ""CM7_GPR,CM7_GPR_1"""
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)
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popup "CMU_FC"
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(
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menuitem "CMU_FC_0" "per , ""CMU_FC,CMU_FC_0"""
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menuitem "CMU_FC_1" "per , ""CMU_FC,CMU_FC_1"""
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menuitem "CMU_FC_3" "per , ""CMU_FC,CMU_FC_3"""
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menuitem "CMU_FC_5" "per , ""CMU_FC,CMU_FC_5"""
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menuitem "CMU_FC_6" "per , ""CMU_FC,CMU_FC_6"""
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menuitem "CMU_FC_7" "per , ""CMU_FC,CMU_FC_7"""
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menuitem "CMU_FC_8" "per , ""CMU_FC,CMU_FC_8"""
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menuitem "CMU_FC_10" "per , ""CMU_FC,CMU_FC_10"""
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menuitem "CMU_FC_11" "per , ""CMU_FC,CMU_FC_11"""
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menuitem "CMU_FC_12" "per , ""CMU_FC,CMU_FC_12"""
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menuitem "CMU_FC_13" "per , ""CMU_FC,CMU_FC_13"""
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menuitem "CMU_FC_14" "per , ""CMU_FC,CMU_FC_14"""
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menuitem "CMU_FC_15" "per , ""CMU_FC,CMU_FC_15"""
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menuitem "CMU_FC_16" "per , ""CMU_FC,CMU_FC_16"""
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menuitem "CMU_FC_17" "per , ""CMU_FC,CMU_FC_17"""
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menuitem "CMU_FC_21" "per , ""CMU_FC,CMU_FC_21"""
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menuitem "CMU_FC_22" "per , ""CMU_FC,CMU_FC_22"""
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menuitem "CMU_FC_23" "per , ""CMU_FC,CMU_FC_23"""
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menuitem "CMU_FC_24" "per , ""CMU_FC,CMU_FC_24"""
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menuitem "CMU_FC_25" "per , ""CMU_FC,CMU_FC_25"""
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menuitem "CMU_FC_26" "per , ""CMU_FC,CMU_FC_26"""
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menuitem "CMU_FC_27" "per , ""CMU_FC,CMU_FC_27"""
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menuitem "CMU_FC_28" "per , ""CMU_FC,CMU_FC_28"""
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menuitem "CMU_FC_29" "per , ""CMU_FC,CMU_FC_29"""
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menuitem "CMU_FC_30" "per , ""CMU_FC,CMU_FC_30"""
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menuitem "CMU_FC_31" "per , ""CMU_FC,CMU_FC_31"""
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)
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menuitem "CRC;CRC" "per , ""CRC"""
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menuitem "CTE" "per , ""CTE"""
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menuitem "CTU" "per , ""CTU"""
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menuitem "PERIPH_DFS;DFS" "per , ""DFS"""
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menuitem "EDMA_0_MP;DMA MP" "per , ""DMA (DMA MP)"""
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menuitem "DMA_CRC_0;DMA_CRC" "per , ""DMA_CRC"""
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menuitem "EDMA_0_TCD" "per , ""DMA_TCD"""
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popup "DMAMUX"
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(
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menuitem "DMAMUX_0" "per , ""DMAMUX,DMAMUX_0"""
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menuitem "DMAMUX_1" "per , ""DMAMUX,DMAMUX_1"""
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)
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popup "EIM"
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(
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menuitem "EIM_A53" "per , ""EIM,EIM_A53"""
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menuitem "EIM_AP1" "per , ""EIM,EIM_AP1"""
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menuitem "EIM_CM7_0" "per , ""EIM,EIM_CM7_0"""
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menuitem "EIM_CM7_1" "per , ""EIM,EIM_CM7_1"""
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menuitem "EIM_DSP" "per , ""EIM,EIM_DSP"""
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menuitem "EIM_RT0" "per , ""EIM,EIM_RT0"""
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menuitem "EIM_RT2" "per , ""EIM,EIM_RT2"""
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)
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popup "ERM"
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(
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menuitem "ERM_AP1" "per , ""ERM,ERM_AP1"""
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menuitem "ERM_CM7_0" "per , ""ERM,ERM_CM7_0"""
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menuitem "ERM_CM7_1" "per , ""ERM,ERM_CM7_1"""
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menuitem "ERM_RT0" "per , ""ERM,ERM_RT0"""
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menuitem "ERM_RT1" "per , ""ERM,ERM_RT1"""
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menuitem "ERM_RT2" "per , ""ERM,ERM_RT2"""
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menuitem "ERM_SPT" "per , ""ERM,ERM_SPT"""
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)
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menuitem "FCCU" "per , ""FCCU"""
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popup "FLEXCAN;CAN"
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(
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menuitem "CAN_0" "per , ""FLEXCAN (CAN),CAN_0"""
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menuitem "CAN_1" "per , ""FLEXCAN (CAN),CAN_1"""
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)
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menuitem "FTM_0;FTM" "per , ""FLEXTIMER (FTM)"""
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menuitem "FXOSC" "per , ""FXOSC"""
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popup "GMAC;Realtime GMAC"
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(
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menuitem "GMAC_0" "per , ""GMAC (Realtime GMAC),GMAC_0"""
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menuitem "GMAC_1" "per , ""GMAC (Realtime GMAC),GMAC_1"""
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)
|
|
popup "I2C;Inter-Integrated Circuit"
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|
(
|
|
menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0"""
|
|
menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1"""
|
|
)
|
|
menuitem "JDC" "per , ""JDC"""
|
|
menuitem "LINFLEXD_0" "per , ""LINFLEXD"""
|
|
popup "MC_CGM"
|
|
(
|
|
menuitem "MC_CGM_0" "per , ""MC_CGM,MC_CGM_0"""
|
|
menuitem "MC_CGM_1" "per , ""MC_CGM,MC_CGM_1"""
|
|
menuitem "MC_CGM_2" "per , ""MC_CGM,MC_CGM_2"""
|
|
menuitem "MC_CGM_3" "per , ""MC_CGM,MC_CGM_3"""
|
|
)
|
|
menuitem "MC_ME" "per , ""MC_ME"""
|
|
menuitem "MC_RGM" "per , ""MC_RGM"""
|
|
menuitem "MCM" "per , ""MCM"""
|
|
menuitem "MDM_AP" "per , ""MDM_AP"""
|
|
popup "MIPICSI2"
|
|
(
|
|
menuitem "MIPICSI2_0" "per , ""MIPICSI2,MIPICSI2_0"""
|
|
menuitem "MIPICSI2_1" "per , ""MIPICSI2,MIPICSI2_1"""
|
|
)
|
|
menuitem "MSCM" "per , ""MSCM"""
|
|
popup "MU;MUA"
|
|
(
|
|
menuitem "MU0__MUA" "per , ""MU (MUA),MU0__MUA"""
|
|
menuitem "MU0__MUB" "per , ""MU (MUA),MU0__MUB"""
|
|
menuitem "MU1__MUA" "per , ""MU (MUA),MU1__MUA"""
|
|
menuitem "MU1__MUB" "per , ""MU (MUA),MU1__MUB"""
|
|
)
|
|
menuitem "OCOTP" "per , ""OCOTP"""
|
|
popup "PIT"
|
|
(
|
|
menuitem "PIT_0" "per , ""PIT,PIT_0"""
|
|
menuitem "PIT_2" "per , ""PIT,PIT_2"""
|
|
)
|
|
popup "PLLDIG"
|
|
(
|
|
menuitem "CORE_PLL" "per , ""PLLDIG,CORE_PLL"""
|
|
menuitem "PERIPH_PLL" "per , ""PLLDIG,PERIPH_PLL"""
|
|
)
|
|
menuitem "PMC" "per , ""PMC"""
|
|
menuitem "PMUEVENTOBSERVER;PMUEVENT observer" "per , ""PMUEVENTOBSERVER (PMUEVENT observer)"""
|
|
menuitem "QUADSPI;QuadSPI" "per , ""QUADSPI (QuadSPI)"""
|
|
menuitem "QUADSPI_ARDB;ARDB" "per , ""QUADSPI_ARDB (ARDB)"""
|
|
menuitem "RDC;Reset domain controller (RDC)" "per , ""RESET (Reset Control)"""
|
|
menuitem "SDA_AP" "per , ""SDA_AP"""
|
|
menuitem "SECURITY;Security subsystem" "per , ""SECURITY (Security subsystem)"""
|
|
popup "SELFTEST_GPR"
|
|
(
|
|
menuitem "SELFTEST_GPR_APP_MAIN_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_MAIN_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_APP_MEM_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_MEM_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_APP_NOC_REST_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_APP_NOC_REST_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0"""
|
|
menuitem "SELFTEST_GPR_CM7_0_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_0_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_CM7_1_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_1_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_CORE_NIU_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_CORE_NIU_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_HSE_RUN_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSE_RUN_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_MIPICSI2_SS_1" "per , ""SELFTEST_GPR,SELFTEST_GPR_MIPICSI2_SS_1"""
|
|
menuitem "SELFTEST_GPR_RADAR_NIU_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_NIU_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_RADAR_SS" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_SS"""
|
|
menuitem "SELFTEST_GPR_RADAR_SS_SPT_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RADAR_SS_SPT_PARTITION"""
|
|
menuitem "SELFTEST_GPR_RT_AXBS0_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RT_AXBS0_LBIST_PARTITION"""
|
|
menuitem "SELFTEST_GPR_RT_AXBS1_LBIST_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_RT_AXBS1_LBIST_PARTITION"""
|
|
)
|
|
menuitem "SELFTEST_GPR_TOP" "per , ""SELFTEST_GPR_TOP"""
|
|
popup "SEMA42"
|
|
(
|
|
menuitem "SEMA42_0" "per , ""SEMA42,SEMA42_0"""
|
|
menuitem "SEMA42_1" "per , ""SEMA42,SEMA42_1"""
|
|
)
|
|
menuitem "SIUL2;SIUL2" "per , ""SIUL2"""
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI_0" "per , ""SPI,SPI_0"""
|
|
menuitem "SPI_1" "per , ""SPI,SPI_1"""
|
|
menuitem "SPI_2" "per , ""SPI,SPI_2"""
|
|
menuitem "SPI_3" "per , ""SPI,SPI_3"""
|
|
)
|
|
menuitem "SPT" "per , ""SPT"""
|
|
popup "SRAM_CTL"
|
|
(
|
|
menuitem "RETENTION_RAM" "per , ""SRAM_CTL,RETENTION_RAM"""
|
|
menuitem "SRAM_CTRL_1" "per , ""SRAM_CTL,SRAM_CTRL_1"""
|
|
menuitem "SRAM_CTRL_2" "per , ""SRAM_CTL,SRAM_CTRL_2"""
|
|
menuitem "SRAM_CTRL_3" "per , ""SRAM_CTL,SRAM_CTRL_3"""
|
|
menuitem "SRAM_CTRL_4" "per , ""SRAM_CTL,SRAM_CTRL_4"""
|
|
menuitem "SRAM_CTRL_5" "per , ""SRAM_CTL,SRAM_CTRL_5"""
|
|
menuitem "SRAM_CTRL_6" "per , ""SRAM_CTL,SRAM_CTRL_6"""
|
|
menuitem "SRAM_CTRL_7" "per , ""SRAM_CTL,SRAM_CTRL_7"""
|
|
menuitem "SRAM_CTRL_8" "per , ""SRAM_CTL,SRAM_CTRL_8"""
|
|
)
|
|
menuitem "SRAMC" "per , ""SRAMC"""
|
|
menuitem "SRC" "per , ""SRC (System Reset Controller)"""
|
|
menuitem "SRC_GPR_TOP" "per , ""SRC_GPR_TOP"""
|
|
menuitem "STCU2" "per , ""STCU2"""
|
|
popup "STM;System Timer"
|
|
(
|
|
menuitem "STM_0" "per , ""STM (System Timer),STM_0"""
|
|
menuitem "STM_1" "per , ""STM (System Timer),STM_1"""
|
|
menuitem "STM_2" "per , ""STM (System Timer),STM_2"""
|
|
)
|
|
popup "SWT"
|
|
(
|
|
menuitem "SWT_0" "per , ""SWT,SWT_0"""
|
|
menuitem "SWT_1" "per , ""SWT,SWT_1"""
|
|
menuitem "SWT_2" "per , ""SWT,SWT_2"""
|
|
menuitem "SWT_3" "per , ""SWT,SWT_3"""
|
|
)
|
|
menuitem "TMU" "per , ""TMU (Thermal Monitoring Unit)"""
|
|
menuitem "WKPU" "per , ""WKPU"""
|
|
popup "XBIC"
|
|
(
|
|
menuitem "XBIC_0" "per , ""XBIC,XBIC_0"""
|
|
menuitem "XBIC_1" "per , ""XBIC,XBIC_1"""
|
|
menuitem "XBIC_2" "per , ""XBIC,XBIC_2"""
|
|
menuitem "XBIC_3" "per , ""XBIC,XBIC_3"""
|
|
menuitem "XBIC_4" "per , ""XBIC,XBIC_4"""
|
|
menuitem "XBIC_5" "per , ""XBIC,XBIC_5"""
|
|
)
|
|
popup "XRDC"
|
|
(
|
|
menuitem "XRDC_0" "per , ""XRDC,XRDC_0"""
|
|
menuitem "XRDC_1" "per , ""XRDC,XRDC_1"""
|
|
)
|
|
)
|
|
)
|