woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
27bce98882c2bc04593a1c1b54504631662dad37
Gen4_R-Car_Trace32/2_Trunk/menr7fs3.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

395 lines
13 KiB
Plaintext
Raw Blame History

; --------------------------------------------------------------------------------
; @Title: R7FS3 Specific Menu
; @Props: Released
; @Author: KOL
; @Changelog: 2016-11-07 KOL
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-M4
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menr7fs3.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "DBGREG" "per , ""DBGREG (Debug Register)"""
menuitem "OCDREG" "per , ""OCDREG (On-Chip Debug Register)"""
menuitem "MMF" "per , ""MMF (Memory Mirror Function)"""
menuitem "Resets" "per , ""Resets"""
menuitem "Option-Setting Memory" "per , ""OSM (Option-Setting Memory)"""
menuitem "LVD" "per , ""LVD (Low Voltage Detection)"""
menuitem "Clock Generation Circuit" "per , ""CGC (Clock Generation Circuit)"""
menuitem "CAC" "per , ""CAC (Clock Frequency Accuracy Measurement Circuit)"""
menuitem "Low Power Mode" "per , ""LPM (Low Power Mode)"""
menuitem "Battery Backup Function" "per , ""BBF (Battery Backup Function)"""
menuitem "Register Write Protection" "per , ""RWP (Register Write Protection)"""
menuitem "ICU" "per , ""ICU (Interrupt Controller Unit)"""
if (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "Buses" "per , ""Buses"""
)
menuitem "MPU" "per , ""MPU (Memory Protection Unit)"""
popup "DMAC"
(
menuitem "DMAC 0" "per , ""DMAC (DMA Controller),DMAC 0"""
menuitem "DMAC 1" "per , ""DMAC (DMA Controller),DMAC 1"""
menuitem "DMAC 2" "per , ""DMAC (DMA Controller),DMAC 2"""
menuitem "DMAC 3" "per , ""DMAC (DMA Controller),DMAC 3"""
)
menuitem "DTC" "per , ""DTC (Data Transfer Controller)"""
menuitem "ELC" "per , ""ELC (Event Link Controller)"""
popup "I/O Ports"
(
menuitem "Port 0" "per , ""I/O Ports,Port 0"""
menuitem "Port 1" "per , ""I/O Ports,Port 1"""
menuitem "Port 2" "per , ""I/O Ports,Port 2"""
menuitem "Port 3" "per , ""I/O Ports,Port 3"""
menuitem "Port 4" "per , ""I/O Ports,Port 4"""
menuitem "Port 5" "per , ""I/O Ports,Port 5"""
menuitem "Port 6" "per , ""I/O Ports,Port 6"""
menuitem "Port 7" "per , ""I/O Ports,Port 7"""
menuitem "Port 8" "per , ""I/O Ports,Port 8"""
menuitem "Port 9" "per , ""I/O Ports,Port 9"""
)
menuitem "KINT" "per , ""KINT (Key Interrupt Function)"""
menuitem "POEG" "per , ""POEG (Port Output Enable for GPT)"""
popup "GPT"
(
menuitem "Channel 0" "per , ""GPT (General PWM Timer),Channel 0"""
menuitem "Channel 1" "per , ""GPT (General PWM Timer),Channel 1"""
menuitem "Channel 2" "per , ""GPT (General PWM Timer),Channel 2"""
menuitem "Channel 3" "per , ""GPT (General PWM Timer),Channel 3"""
menuitem "Channel 4" "per , ""GPT (General PWM Timer),Channel 4"""
menuitem "Channel 5" "per , ""GPT (General PWM Timer),Channel 5"""
menuitem "Channel 6" "per , ""GPT (General PWM Timer),Channel 6"""
menuitem "Channel 7" "per , ""GPT (General PWM Timer),Channel 7"""
menuitem "Channel 8" "per , ""GPT (General PWM Timer),Channel 8"""
if (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "Channel 9" "per , ""GPT (General PWM Timer),Channel 9"""
)
)
popup "AGT"
(
menuitem "Channel 0" "per , ""AGT (Asynchronous General Purpose Timer),Channel 0"""
menuitem "Channel 1" "per , ""AGT (Asynchronous General Purpose Timer),Channel 1"""
)
menuitem "RTC" "per , ""RTC (Realtime Clock)"""
menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
menuitem "IWDT" "per , ""IWDT (Independent Watchdog Timer)"""
menuitem "USBFS" "per , ""USBFS (USB 2.0 Full-Speed Module)"""
popup "SCI"
(
menuitem "SCI0" "per , ""SCI (Serial Communications Interface),SCI0"""
menuitem "SCI1" "per , ""SCI (Serial Communications Interface),SCI1"""
menuitem "SCI2" "per , ""SCI (Serial Communications Interface),SCI2"""
menuitem "SCI3" "per , ""SCI (Serial Communications Interface),SCI3"""
menuitem "SCI4" "per , ""SCI (Serial Communications Interface),SCI4"""
menuitem "SCI9" "per , ""SCI (Serial Communications Interface),SCI9"""
)
menuitem "IrDA Interface" "per , ""IrDA Interface"""
popup "IIC"
(
menuitem "Channel 0" "per , ""IIC (I2C Bus Interface),Channel 0"""
menuitem "Channel 1" "per , ""IIC (I2C Bus Interface),Channel 1"""
if (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "Channel 2" "per , ""IIC (I2C Bus Interface),Channel 2"""
)
)
menuitem "CAN" "per , ""CAN (Controller Area Network)"""
popup "SPI"
(
menuitem "Channel 0" "per , ""SPI (Serial Peripheral Interface),Channel 0"""
menuitem "Channel 1" "per , ""SPI (Serial Peripheral Interface),Channel 1"""
)
if (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "QSPI" "per , ""QSPI (Quad Serial Peripheral Interface)"""
)
menuitem "CRC" "per , ""CRC (Cyclic Redundancy Check)"""
popup "SSI"
(
menuitem "Channel 0" "per , ""SSI (Serial Sound Interface),Channel 0"""
menuitem "Channel 1" "per , ""SSI (Serial Sound Interface),Channel 1"""
)
if (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "SDHI" "per , ""SDHI (SD/MMC Host Interface)"""
)
menuitem "ADC14" "per , ""ADC14 (14-Bit A/D Converter)"""
popup "DAC12"
(
menuitem "Channel 0" "per , ""DAC12 (12-Bit D/A Converter),Channel 0"""
menuitem "Channel 1" "per , ""DAC12 (12-Bit D/A Converter),Channel 1"""
)
menuitem "TSN" "per , ""TSN (Temperature Sensor)"""
menuitem "OPAMP" "per , ""OPAMP (Operational Amplifier)"""
popup "ACMPHS"
(
menuitem "Channel 0" "per , ""ACMPHS (High-Speed Analog Comparator),Channel 0"""
menuitem "Channel 1" "per , ""ACMPHS (High-Speed Analog Comparator),Channel 1"""
)
menuitem "ACMPLP" "per , ""ACMPLP (Low-Power Analog Comparator)"""
menuitem "CTSU" "per , ""CTSU (Capacitive Touch Sensing Unit)"""
menuitem "DOC" "per , ""DOC (Data Operation Circuit)"""
menuitem "SRAM" "per , ""SRAM"""
menuitem "Flash Memory" "per , ""Flash Memory"""
if (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
(
menuitem "SLCDC" "per , ""SLCDC (Segment LCD Controller/Driver)"""
)
)
)
Reference in New Issue View Git Blame Copy Permalink