336 lines
9.4 KiB
Plaintext
336 lines
9.4 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: MAX32655 Specific Menu
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; @Props: Released
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; @Author: PIW
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; @Changelog: 2022-05-11 PIW
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; @Manufacturer: MAXIM - Maxim Integrated Products, Inc.
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; @Core: Cortex-M4F
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; @Chip: MAX32655GXG+, MAX32655GXG+T, MAX32655GWY+, MAX32655GWY+T
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menmax32655.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "ADC" "per , ""ADC (Inter-Integrated Circuit)"""
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menuitem "AES" "per , ""AES (AES Keys)"""
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menuitem "AES_KEY" "per , ""AES_KEY (AES Key Registers)"""
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menuitem "CRC" "per , ""CRC (CRC Registers)"""
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menuitem "DMA" "per , ""DMA (DMA Controller Fully programmable chaining capable DMA channels)"""
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menuitem "FCR" "per , ""FCR (Function Control Register)"""
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menuitem "FLC" "per , ""FLC (Flash Memory Control)"""
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menuitem "GCR" "per , ""GCR (Global Control Registers)"""
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popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
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(
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menuitem "GPIO0" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO0"""
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menuitem "GPIO1" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO1"""
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)
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popup "I2C (Inter-Integrated Circuit)"
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(
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menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
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menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
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menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2"""
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)
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menuitem "I2S" "per , ""I2S (Inter-Integrated Sound Bus Controller)"""
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menuitem "ICC0" "per , ""ICC0 (Instruction Cache Controller Registers)"""
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menuitem "LPGCR" "per , ""LPGCR (Low Power Global Control)"""
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menuitem "MCR" "per , ""MCR (Misc Control)"""
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menuitem "OWM" "per , ""OWM (1-Wire Master Interface)"""
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popup "PULSE_TRAIN (Pulse Train)"
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(
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menuitem "PT" "per , ""PULSE_TRAIN (Pulse Train),PT"""
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menuitem "PT1" "per , ""PULSE_TRAIN (Pulse Train),PT1"""
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menuitem "PT2" "per , ""PULSE_TRAIN (Pulse Train),PT2"""
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menuitem "PT3" "per , ""PULSE_TRAIN (Pulse Train),PT3"""
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menuitem "PTG" "per , ""PULSE_TRAIN (Pulse Train),PTG"""
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)
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menuitem "PWRSEQ" "per , ""PWRSEQ (Power Sequencer / Low Power Control Register)"""
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menuitem "RTC" "per , ""RTC (Real-time Counter)"""
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menuitem "SEMA" "per , ""SEMA"""
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menuitem "SIMO" "per , ""SIMO (Single Inductor Multiple Output Switching Converter)"""
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menuitem "SIR" "per , ""SIR (System Initialization Registers)"""
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popup "SPI (SPI peripheral)"
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(
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menuitem "SPI0" "per , ""SPI (SPI peripheral),SPI0"""
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menuitem "SPI1" "per , ""SPI (SPI peripheral),SPI1"""
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menuitem "SPI2" "per , ""SPI (SPI peripheral),SPI2"""
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)
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popup "TMR (Low-Power Configurable Timer)"
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(
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menuitem "TMR" "per , ""TMR (Low-Power Configurable Timer),TMR"""
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menuitem "TMR1" "per , ""TMR (Low-Power Configurable Timer),TMR1"""
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menuitem "TMR2" "per , ""TMR (Low-Power Configurable Timer),TMR2"""
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menuitem "TMR3" "per , ""TMR (Low-Power Configurable Timer),TMR3"""
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menuitem "TMR4" "per , ""TMR (Low-Power Configurable Timer),TMR4"""
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menuitem "TMR5" "per , ""TMR (Low-Power Configurable Timer),TMR5"""
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)
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menuitem "TRIMSIR" "per , ""TRIMSIR (Trim System Initialization Registers)"""
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menuitem "TRNG" "per , ""TRNG (Random Number Generator)"""
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popup "UART (Universal Asynchronous Receiver/Transmitter)"
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(
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menuitem "UART" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART"""
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menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
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menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
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menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
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)
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popup "WDT (Watchdog Timer Unit)"
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(
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menuitem "WDT" "per , ""WDT (Watchdog Timer Unit),WDT"""
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menuitem "WDT1" "per , ""WDT (Watchdog Timer Unit),WDT1"""
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)
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menuitem "WUT" "per , ""WUT (32-bit reloadable timer)"""
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)
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)
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