woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
27bce98882c2bc04593a1c1b54504631662dad37
Gen4_R-Car_Trace32/2_Trunk/menkinetisk32l.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

809 lines
25 KiB
Plaintext
Raw Blame History

; --------------------------------------------------------------------------------
; @Title: K32L Specific Menu
; @Props: Released
; @Author: KMB, PIW
; @Changelog: 2021-09-10 KMB
; 2022-02-23 PIW
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-M4, Cortex-M0+
; @Chip: K32L2A31VLH1A, K32L2A31VLL1A, K32L2A41VLH1A, K32L2A41VLL1A,
; K32L2B11VFM0A ,K32L2B11VFT0A, K32L2B11VLH0A, K32L2B11VMP0A,
; K32L2B21VFM0A, K32L2B21VFT0A, K32L2B21VLH0A, K32L2B21VMP0A,
; K32L2B31VFM0A, K32L2B31VFT0A, K32L2B31VLH0A, K32L2B31VMP0A,
; K32L3A60VPJ1A-CM0+, K32L3A60VPJ1A-CM4
; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menkinetisk32l.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXM0+")
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else if (CORENAME()=="CORTEXM4")
(
popup "[:chip]Core Registers (Cortex-M4)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "ADC0" "per , ""ADC0 (Analog-to-Digital Converter),ADC0"""
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "AXBS0" "per , ""AXBS,AXBS0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU))"
(
menuitem "CAU0" "per , ""CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU)),CAU0"""
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "CAU3" "per , ""CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU)),CAU3"""
)
)
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "CMP0" "per , ""CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX)),CMP0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
menuitem "CMP1" "per , ""CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX)),CMP1"""
)
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "COREDEBUG" "per , ""COREDEBUG (Core Debug Registers),COREDEBUG"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "CRC" "per , ""CRC,CRC"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "DAC0" "per , ""DAC0 (12-Bit Digital-to-Analog Converter),DAC0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "DMA (DMA Controller)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "DMA" "per , ""DMA (DMA Controller),DMA"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4"))
(
menuitem "DMA0" "per , ""DMA (DMA Controller),DMA0"""
)
if (cpuis("K32L3A*-CM0+"))
(
menuitem "DMA1" "per , ""DMA (DMA Controller),DMA1"""
)
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "DMAMUX (DMA_CH_MUX)"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM4"))
(
menuitem "DMAMUX0" "per , ""DMAMUX (DMA_CH_MUX),DMAMUX0"""
)
if (cpuis("K32L3A*-CM0+"))
(
menuitem "DMAMUX1" "per , ""DMAMUX (DMA_CH_MUX),DMAMUX1"""
)
)
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "DWT" "per , ""DWT (Data Watchpoint and Trace Unit Registers),DWT"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "EMVSIM"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "EMVSIM0" "per , ""EMVSIM,EMVSIM0"""
)
)
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "ETM" "per , ""ETM (Embedded Trace Macrocell Registers),ETM"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "EWM" "per , ""EWM,EWM"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
(
popup "FGPIO (General Purpose Input/Output)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "FGPIOA" "per , ""FGPIO (General Purpose Input/Output),FGPIOA"""
menuitem "FGPIOB" "per , ""FGPIO (General Purpose Input/Output),FGPIOB"""
menuitem "FGPIOC" "per , ""FGPIO (General Purpose Input/Output),FGPIOC"""
menuitem "FGPIOD" "per , ""FGPIO (General Purpose Input/Output),FGPIOD"""
)
menuitem "FGPIOE" "per , ""FGPIO (General Purpose Input/Output),FGPIOE"""
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
menuitem "FGPIOA" "per , ""FGPIOA (General Purpose Input/Output),FGPIOA"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "FB" "per , ""FLEXBUS (FB),FB"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "FLEXIO" "per , ""FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.),FLEXIO"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "FLEXIO0" "per , ""FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.),FLEXIO0"""
)
)
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "FPB" "per , ""FPB (Flash Patch and Breakpoint Unit Registers),FPB"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "FTFA" "per , ""FTFA (Flash Memory Interface),FTFA"""
menuitem "FTFA_FLASHCONFIG" "per , ""FTFA_FLASHCONFIG (Flash configuration field),FTFA_FLASHCONFIG"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "FTFE" "per , ""FTFE (Flash),FTFE"""
)
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
(
menuitem "GPIOA" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOA"""
menuitem "GPIOB" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOB"""
menuitem "GPIOC" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOC"""
menuitem "GPIOD" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOD"""
menuitem "GPIOE" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOE"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "I2C (Inter-Integrated Circuit)"
(
menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "INTMUX (Interrupt Multiplexer)"
(
menuitem "INTMUX0" "per , ""INTMUX (Interrupt Multiplexer),INTMUX0"""
if (cpuis("K32L3A*-CM0+"))
(
menuitem "INTMUX1" "per , ""INTMUX (Interrupt Multiplexer),INTMUX1"""
)
)
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "ITM" "per , ""ITM (Instrumentation Trace Macrocell Registers),ITM"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B31*"))
(
menuitem "LCD" "per , ""LCD (Segment Liquid Crystal Display),LCD"""
)
popup "LLWU (Low leakage wakeup unit)"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "LLWU" "per , ""LLWU (Low leakage wakeup unit),LLWU"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LLWU0" "per , ""LLWU (Low leakage wakeup unit),LLWU0"""
menuitem "LLWU1" "per , ""LLWU (Low leakage wakeup unit),LLWU1"""
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPADC0" "per , ""LPADC,LPADC0"""
popup "LPCMP"
(
menuitem "LPCMP0" "per , ""LPCMP,LPCMP0"""
menuitem "LPCMP1" "per , ""LPCMP,LPCMP1"""
)
menuitem "LPDAC0" "per , ""LPDAC,LPDAC0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "LPI2C (The LPI2C Memory Map/Register Definition can be found here.)"
(
menuitem "LPI2C0" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C0"""
menuitem "LPI2C1" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C1"""
menuitem "LPI2C2" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C2"""
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPI2C3" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C3"""
)
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "LPIT"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPIT0" "per , ""LPIT,LPIT0"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPIT1" "per , ""LPIT,LPIT1"""
)
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "LPSPI (The LPSPI Memory Map/Register Definition can be found here.)"
(
menuitem "LPSPI0" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI0"""
menuitem "LPSPI1" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI1"""
menuitem "LPSPI2" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI2"""
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPSPI3" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI3"""
)
)
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "LPTMR (Low Power Timer)"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPTMR0" "per , ""LPTMR (Low Power Timer),LPTMR0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPTMR1" "per , ""LPTMR (Low Power Timer),LPTMR1"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPTMR2" "per , ""LPTMR (Low Power Timer),LPTMR2"""
)
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "LPTPM (TPM)"
(
menuitem "TPM0" "per , ""LPTPM (TPM),TPM0"""
menuitem "TPM1" "per , ""LPTPM (TPM),TPM1"""
menuitem "TPM2" "per , ""LPTPM (TPM),TPM2"""
menuitem "TPM3" "per , ""LPTPM (TPM),TPM3"""
)
)
popup "LPUART"
(
menuitem "LPUART0" "per , ""LPUART,LPUART0"""
menuitem "LPUART1" "per , ""LPUART,LPUART1"""
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPUART2" "per , ""LPUART,LPUART2"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "LPUART3" "per , ""LPUART,LPUART3"""
)
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "MCG" "per , ""MCG (Multipurpose Clock Generator Lite),MCG"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "MCM (Core Platform Miscellaneous Control Module)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "MCM" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4"))
(
menuitem "MCM0" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM0"""
)
if (cpuis("K32L3A*-CM0+"))
(
menuitem "MCM1" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM1"""
)
)
popup "MMDVSQ (Divide and Square Root)"
(
menuitem "MMDVSQ0" "per , ""MMDVSQ (Divide and Square Root),MMDVSQ0"""
if (cpuis("K32L3A*-CM0+"))
(
menuitem "MMDVSQ1" "per , ""MMDVSQ (Divide and Square Root),MMDVSQ1"""
)
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "MSCM" "per , ""MSCM,MSCM"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "MSMC (crr_cmc0)"
(
menuitem "SMC0" "per , ""MSMC (crr_cmc0),SMC0"""
menuitem "SMC1" "per , ""MSMC (crr_cmc0),SMC1"""
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "MTB (Micro Trace Buffer)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
(
menuitem "MTB" "per , ""MTB (Micro Trace Buffer),MTB"""
)
menuitem "MTB0" "per , ""MTB (Micro Trace Buffer),MTB0"""
)
menuitem "MTB0_DWT" "per , ""MTB0_DWT (MTB data watchpoint and trace),MTB0_DWT"""
menuitem "MTB0_ROM" "per , ""MTB0_ROM (System ROM),MTB0_ROM"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
(
menuitem "MTBDWT" "per , ""MTBDWT (DWT),MTBDWT"""
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "MUA" "per , ""MUA (Messaging Unit Processor A-side),MUA"""
)
if (cpuis("K32L3A*-CM0+"))
(
menuitem "MUB" "per , ""MUB (Messaging Unit Processor B-side),MUB"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "NVIC (Nested Vectored Interrupt Controller)"
(
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "NVIC" "per , ""NVIC (Nested Vectored Interrupt Controller),NVIC"""
)
menuitem "NVIC0" "per , ""NVIC (Nested Vectored Interrupt Controller),NVIC0"""
)
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "OSC0" "per , ""OSC0 (Oscillator),OSC0"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "PCC"
(
menuitem "PCC0" "per , ""PCC,PCC0"""
menuitem "PCC1" "per , ""PCC,PCC1"""
)
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "PIT" "per , ""PIT (Periodic Interrupt Timer),PIT"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "PMC" "per , ""PMC (Power Management Controller),PMC"""
)
popup "PORT (Pin Control and Interrupts)"
(
menuitem "PORTA" "per , ""PORT (Pin Control and Interrupts),PORTA"""
menuitem "PORTB" "per , ""PORT (Pin Control and Interrupts),PORTB"""
menuitem "PORTC" "per , ""PORT (Pin Control and Interrupts),PORTC"""
menuitem "PORTD" "per , ""PORT (Pin Control and Interrupts),PORTD"""
menuitem "PORTE" "per , ""PORT (Pin Control and Interrupts),PORTE"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "RCM" "per , ""RCM (Reset Control Module),RCM"""
menuitem "RFSYS" "per , ""RFSYS (System register file),RFSYS"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+"))
(
menuitem "ROM" "per , ""ROM,ROM"""
)
menuitem "RTC" "per , ""RTC (Real-time Counter),RTC"""
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "SYSTEMCONTROL" "per , ""SCB (System Control Block),SYSTEMCONTROL"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "SCG" "per , ""SCG,SCG"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "SEMA42 (sema42_ips)"
(
menuitem "SEMA420" "per , ""SEMA42 (sema42_ips),SEMA420"""
menuitem "SEMA421" "per , ""SEMA42 (sema42_ips),SEMA421"""
)
)
menuitem "SIM" "per , ""SIM,SIM"""
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "SMC" "per , ""SMC (System Mode Controller),SMC"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "SPI (Serial Peripheral Interface)"
(
menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "SPM" "per , ""SPM,SPM"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "SYSTEMCONTROL" "per , ""SYSTEMCONTROL (System Control Block),SYSTEMCONTROL"""
)
menuitem "SYSTICK" "per , ""SYSTICK (System timer)"""
if (cpuis("K32L3A*-CM4"))
(
menuitem "TPIU" "per , ""TPIU (Trace Port Interface Unit Registers),TPIU"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
popup "TPM (Timer/PWM Module)"
(
menuitem "TPM0" "per , ""TPM (Timer/PWM Module),TPM0"""
menuitem "TPM1" "per , ""TPM (Timer/PWM Module),TPM1"""
menuitem "TPM2" "per , ""TPM (Timer/PWM Module),TPM2"""
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
popup "TRGMUX"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "TRGMUX0" "per , ""TRGMUX,TRGMUX0"""
menuitem "TRGMUX1" "per , ""TRGMUX,TRGMUX1"""
)
)
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "TRNG" "per , ""TRNG,TRNG"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
menuitem "TSI0" "per , ""TSI0 (Touch sense input),TSI0"""
menuitem "TSTMR0" "per , ""TSTMR0 (Timestamp Timer),TSTMR0"""
)
if (cpuis("K32L3A*-CM4"))
(
menuitem "TSTMRA" "per , ""TSTMRA,TSTMRA"""
)
if (cpuis("K32L3A*-CM0+"))
(
menuitem "TSTMRB" "per , ""TSTMRB,TSTMRB"""
)
if (cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "UART2" "per , ""UART2 (Serial Communication Interface),UART2"""
)
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*"))
(
menuitem "USB0" "per , ""USB0 (Universal Serial Bus OTG Capable Controller),USB0"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "USB0" "per , ""USBFSOTG (USB),USB0"""
menuitem "USBVREG" "per , ""USBVREG,USBVREG"""
menuitem "USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC0"""
)
menuitem "VREF" "per , ""VREF,VREF"""
if (cpuis("K32L2A31*")||cpuis("K32L2A41*"))
(
popup "WDOG (Watchdog Timer Unit)"
(
if (cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "WDOG0" "per , ""WDOG (Watchdog Timer Unit),WDOG0"""
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "WDOG1" "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
)
)
)
if (cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4"))
(
menuitem "XRDC" "per , ""XRDC,XRDC"""
)
)
)
Reference in New Issue View Git Blame Copy Permalink