18037 lines
1.5 MiB
18037 lines
1.5 MiB
; --------------------------------------------------------------------------------
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; @Title: UCD3xxx On-Chip Peripherals
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; @Props: Released
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; @Author: LSD JRK
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; @Changelog: 2015-08-10 LSD
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; @Manufacturer: TI - Texas Instruments
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; @Doc:
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; ucd3020.pdf(rev. 2013-10),
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; ucd3020a.pdf(rev. 2015-03-25),
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; ucd3028.pdf(rev. 2013-10),
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; ucd3040.pdf(rev. 2013-10),
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; ucd3138.pdf(rev. 2013-11),
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; ucd3138a64.pdf(rev. 2014-09)
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; ucd3138a64_ucd3138128_programming_manual_sluub54a.pdf(rev. 2014-09),
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; ucd3138128.pdf(rev. 2014-09)
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; ucd3138_programming_manual_sluu995a.pdf(rev. 2013-05),
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; sluu996a.pdf (rev. 2013-05),
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; @Core: ARM7TDMI-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perucd3xxx.per 12528 2020-11-12 13:57:39Z bschroefel $
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; known problems
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; DPWM module: In registers (DPWMRESDUTY,DPWMADAPTIVE,DPWMCBCLOCATION) are inconsistency bitmap width description of bits
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; GPIO module: no registers for UCD3020,UCD3028,UCD3020A,UCD3028,UCD3040PFC,UCD3040RGC,SLUU996A.pdf
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; PSA module: No registers description
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; Miscellaneous Analog Control module: Lack of document with registers description to MCU: UCD30*
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; UCD30* lack of register description documents
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; SPI module: In register SPISTAT is inconsistent bitmap width description of bits FRMCNT
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config 16. 8.
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width 0x0B
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tree "ICEBreaker"
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width 0x0B
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tree "ICEBreaker"
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group ice:0x8--0x8 "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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group ice:0x9--0x9
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line.long 0x0 "AM,Address Mask"
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group ice:0x0a--0x0a
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line.long 0x0 "DV,Data Value"
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group ice:0x0b--0x0b
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line.long 0x0 "DM,Data Mask"
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group ice:0x0c--0x0c
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line.long 0x0 "CV,Control Value"
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bitfld.long 0x0 08. " ENABLE ,Global Enable for Watchpoint 1" "Disabled,Enabled"
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bitfld.long 0x0 07. " RANGE ,Assert RANGEOUT Signal" "0,1"
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bitfld.long 0x0 06. " CHAIN ,Connect to Watchpoint 0" "0,1"
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bitfld.long 0x0 05. " EXTERN ,Depentend from EXTERN Signal" "0,1"
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textline " "
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bitfld.long 0x0 04. " nTRANS ,CPU Mode" "User,Not user"
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bitfld.long 0x0 03. " nOPC ,Op Fetch" "Instruction,Data"
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bitfld.long 0x0 01.--02. " MAS ,Access Size" "Byte,Word,Long,?..."
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bitfld.long 0x0 00. " nRW ,Read/Write" "Read,Write"
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group ice:0x0d--0x0d
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line.long 0x0 "CM,Control Mask"
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bitfld.long 0x0 07. " RANGE ,Assert RANGEOUT Signal" "Enabled,Disabled"
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bitfld.long 0x0 06. " CHAIN ,Connect to Watchpoint 0" "Enabled,Disabled"
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bitfld.long 0x0 05. " EXTERN ,Depentend from EXTERN Signal" "Enabled,Disabled"
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bitfld.long 0x0 04. " nTRANS ,CPU Mode" "Enabled,Disabled"
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textline " "
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bitfld.long 0x0 03. " nOPC ,Op Fetch" "Enabled,Disabled"
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bitfld.long 0x0 01.--02. " MAS ,Access Size" "Enabled,Reserved,Reserved,Disabled"
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bitfld.long 0x0 00. " nRW ,Read/Write" "Enabled,Disabled"
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group ice:0x10--0x10 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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group ice:0x11--0x11
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line.long 0x0 "AM,Address Mask"
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group ice:0x12--0x12
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line.long 0x0 "DV,Data Value"
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group ice:0x13--0x13
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line.long 0x0 "DM,Data Mask"
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group ice:0x14--0x14
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line.long 0x0 "CV,Control Value"
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bitfld.long 0x0 08. " ENABLE ,Global Enable for Watchpoint 1" "Disabled,Enabled"
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bitfld.long 0x0 07. " RANGE ,Assert RANGEOUT Signal" "0,1"
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bitfld.long 0x0 06. " CHAIN ,Connect to Watchpoint 0" "0,1"
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bitfld.long 0x0 05. " EXTERN ,Depentend from EXTERN Signal" "0,1"
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textline " "
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bitfld.long 0x0 04. " nTRANS ,CPU Mode" "User,Not user"
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bitfld.long 0x0 03. " nOPC ,Op Fetch" "Instruction,Data"
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bitfld.long 0x0 01.--02. " MAS ,Access Size" "Byte,Word,Long,?..."
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bitfld.long 0x0 00. " nRW ,Read/Write" "Read,Write"
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group ice:0x15--0x15
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line.long 0x00 "CM,Control Mask"
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bitfld.long 0x0 07. " RANGE ,Assert RANGEOUT Signal" "Enabled,Disabled"
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bitfld.long 0x0 06. " CHAIN ,Connect to Watchpoint 0" "Enabled,Disabled"
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bitfld.long 0x0 05. " EXTERN ,Depentend from EXTERN Signal" "Enabled,Disabled"
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bitfld.long 0x0 04. " nTRANS ,CPU Mode" "Enabled,Disabled"
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textline " "
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bitfld.long 0x0 03. " nOPC ,Op Fetch" "Enabled,Disabled"
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bitfld.long 0x0 01.--02. " MAS ,Access Size" "Enabled,Reserved,Reserved,Disabled"
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bitfld.long 0x0 00. " nRW ,Read/Write" "Enabled,Disabled"
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tree.end
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tree.end
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sif (cpuis("UCD3138*"))
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tree "Loop Mux"
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sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
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base ad:0x00120000
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width 14.
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group.word 0x00++0x01
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line.word 0x00 "FECTRL0MUX,Front End Control 0 Mux Register"
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bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
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bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
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group.word 0x04++0x01
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line.word 0x00 "FECTRL1MUX,Front End Control 1 Mux Register"
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bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
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bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
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group.word 0x08++0x01
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line.word 0x00 "FECTRL2MUX,Front End Control 2 Mux Register"
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bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
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bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
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bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
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group.word 0x0C++0x01
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line.word 0x00 "SAMPTRIGCTRL,Sample Trigger Control Register"
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bitfld.word 0x00 11. " FE2_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 2" "Disabled,Enabled"
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bitfld.word 0x00 10. " FE2_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 2" "Disabled,Enabled"
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bitfld.word 0x00 9. " FE2_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 2" "Disabled,Enabled"
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bitfld.word 0x00 8. " FE2_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 2" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 7. " FE1_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 1" "Disabled,Enabled"
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bitfld.word 0x00 6. " FE1_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 1" "Disabled,Enabled"
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bitfld.word 0x00 5. " FE1_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 1" "Disabled,Enabled"
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bitfld.word 0x00 4. " FE1_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 1" "Disabled,Enabled"
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textline " "
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bitfld.word 0x00 3. " FE0_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 0" "Disabled,Enabled"
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bitfld.word 0x00 2. " FE0_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 0" "Disabled,Enabled"
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bitfld.word 0x00 1. " FE0_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 0" "Disabled,Enabled"
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bitfld.word 0x00 0. " FE0_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 0" "Disabled,Enabled"
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textline " "
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group.long 0x10++0x0B
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line.long 0x00 "EXTDACCTRL,External DAC Control Register"
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bitfld.long 0x00 24.--26. " DAC2_SEL ,Configures DAC 2 setpoint in External DAC Mode" "DAC 0,DAC 1,,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
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bitfld.long 0x00 16.--18. " DAC1_SEL ,Configures DAC 1 setpoint in External DAC Mode" "DAC 0,,DAC 2,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
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bitfld.long 0x00 8.--10. " DAC0_SEL ,Configures DAC 0 setpoint in External DAC Mode" ",DAC 1,DAC 2,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
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textline " "
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bitfld.long 0x00 2. " EXT_DAC2_EN ,External DAC 2 Mode Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " EXT_DAC1_EN ,External DAC 1 Mode Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " EXT_DAC0_EN ,External DAC 0 Mode Enable" "Disabled,Enabled"
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line.long 0x04 "FILTERMUX,Filter Mux Register"
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bitfld.long 0x04 28.--29. " FILTER2_KCOMP_SEL ,Selects KComp value routed to Filter 2 Module" "KComp0,KComp1,KComp2,?..."
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bitfld.long 0x04 26.--27. " FILTER1_KCOMP_SEL ,Selects KComp value routed to Filter 1 Module" "KComp0,KComp1,KComp2,?..."
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bitfld.long 0x04 24.--25. " FILTER0_KCOMP_SEL ,Selects KComp value routed to Filter 0 Module" "KComp0,KComp1,KComp2,?..."
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textline " "
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bitfld.long 0x04 18. " FILTER2_FFWD_SEL ,Configures Feedforward value routed to Filter 2 Module" "Filter 0,Filter 1"
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bitfld.long 0x04 17. " FILTER1_FFWD_SEL ,Configures Feedforward value routed to Filter 1 Module" "Filter 0,Filter 2"
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bitfld.long 0x04 16. " FILTER0_FFWD_SEL ,Configures Feedforward value routed to Filter 0 Module" "Filter 1,Filter 2"
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textline " "
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bitfld.long 0x04 12.--13. " FILTER2_PER_SEL ,Selects source of switching cycle period for Filter 2 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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bitfld.long 0x04 10.--11. " FILTER1_PER_SEL ,Selects source of switching cycle period for Filter 1 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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bitfld.long 0x04 8.--9. " FILTER0_PER_SEL ,Selects source of switching cycle period for Filter 0 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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textline " "
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bitfld.long 0x04 4.--5. " FILTER2_FE_SEL ,Selects which Front End Module provides data for Filter 2 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
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bitfld.long 0x04 2.--3. " FILTER1_FE_SEL ,Selects which Front End Module provides data for Filter 1 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
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bitfld.long 0x04 0.--1. " FILTER0_FE_SEL ,Selects which Front End Module provides data for Filter 0 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
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line.long 0x08 "FILTERKCOMPA,Filter KComp A Register"
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hexmask.long.word 0x08 16.--29. 1. " KCOMP1 ,Value used in filter output calculations replacing the DPWM switching period value"
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hexmask.long.word 0x08 0.--13. 1. " KCOMP0 ,Value used in filter output calculations replacing the DPWM switching period value"
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textline " "
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group.word 0x1C++0x01
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line.word 0x00 "FILTERKCOMPB,Filter KComp B Register"
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hexmask.word 0x00 0.--13. 1. " KCOMP2 ,Value used in filter output calculations replacing the DPWM switching period value"
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group.long 0x20++0x03
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line.long 0x00 "DPWMMUX,DPWM Mux Register"
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bitfld.long 0x00 30.--31. " DPWM3_SYNC_FET_SEL ,Selects Ramp source for DPWM3 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
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bitfld.long 0x00 28.--29. " DPWM2_SYNC_FET_SEL ,Selects Ramp source for DPWM2 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
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bitfld.long 0x00 26.--27. " DPWM1_SYNC_FET_SEL ,Selects Ramp source for DPWM1 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
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textline " "
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bitfld.long 0x00 24.--25. " DPWM0_SYNC_FET_SEL ,Selects Ramp source for DPWM0 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
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bitfld.long 0x00 18.--19. " DPWM3_SYNC_SEL ,Selects Master Sync for DPWM3 when DPWM3 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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bitfld.long 0x00 16.--17. " DPWM2_SYNC_SEL ,Selects Master Sync for DPWM2 when DPWM2 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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textline " "
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bitfld.long 0x00 14.--15. " DPWM1_SYNC_SEL ,Selects Master Sync for DPWM1 when DPWM1 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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bitfld.long 0x00 12.--13. " DPWM0_SYNC_SEL ,Selects Master Sync for DPWM0 when DPWM0 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
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bitfld.long 0x00 9.--11. " DPWM3_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 3" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
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textline " "
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bitfld.long 0x00 6.--8. " DPWM2_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 2" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
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bitfld.long 0x00 3.--5. " DPWM1_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 1" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
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bitfld.long 0x00 0.--2. " DPWM0_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 0" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
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textline " "
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sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
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group.long 0x24++0x03
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line.long 0x00 "CPCTRL,Constant Power Control Register"
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bitfld.long 0x00 16. " CPCC_INT_EN ,Constant Power/Constant Current Interrupt Enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " DAC_COMP_EN ,Enables comparison of DAC Setpoint and quotient of Max Power/Sense Current in Loop Switching Mode" "Disabled,Enabled"
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bitfld.long 0x00 14. " FW_DIVISOR_EN ,Enables Firmware value for divisor in Constant Power calculations" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 13. " LOWER_COMP_EN ,Enables output of lowest duty from current or voltage loop when Constant Power/Constant Current module controls loop output" "Disabled,Enabled"
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bitfld.long 0x00 12. " VLOOP_FREEZE_EN ,Enables freezing of Voltage Loop Integrator when current loop selected in Loop Switching configuration" "Disabled,Enabled"
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bitfld.long 0x00 10.--11. " VLOOP_SEL ,Configures voltage loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
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textline " "
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bitfld.long 0x00 8.--9. " CLOOP_SEL ,Configures current loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
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bitfld.long 0x00 5.--7. " THRESH_SEL ,Configures input threshold selected for use in Constant Power comparison" "Filter 0,Filter 1,Filter 2,Front End 0,Front End 1,Front End 2,?..."
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bitfld.long 0x00 3.--4. " DIVISOR_SEL ,Configures value used for divisor in Constant Power calculations" "Filter 0,Filter 1,Filter 2,?..."
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textline " "
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|
bitfld.long 0x00 1.--2. " CPCC_CONFIG ,Controls Constant Power/Constant Current module configuration" "Average Current Mode,Constant Power Module controls selection of loop,Constant Power Module error switching,?..."
|
|
bitfld.long 0x00 0. " CPCC_EN ,Constant Power Constant/Current Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CPCTRL,Constant Power Control Register"
|
|
bitfld.word 0x00 15. " DAC_COMP_EN ,Enables comparison of DAC Setpoint and quotient of Max Power/Sense Current in Loop Switching Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FW_DIVISOR_EN ,Enables Firmware value for divisor in Constant Power calculations" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " LOWER_COMP_EN ,Enables output of lowest duty from current or voltage loop when Constant Power/Constant Current module controls loop output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " VLOOP_FREEZE_EN ,Enables freezing of Voltage Loop Integrator when current loop selected in Loop Switching configuration" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--11. " VLOOP_SEL ,Configures voltage loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 8.--9. " CLOOP_SEL ,Configures current loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 5.--7. " THRESH_SEL ,Configures input threshold selected for use in Constant Power comparison" "Filter 0,Filter 1,Filter 2,Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.word 0x00 3.--4. " DIVISOR_SEL ,Configures value used for divisor in Constant Power calculations" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 2. " CPCC_INT_EN ,Constant Power/Constant Current Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPCC_CONFIG ,Constant Power/Constant Current module configuration" "Average Current,Constant Power Module controls selection of loop"
|
|
bitfld.word 0x00 0. " CPCC_EN ,Constant Power Constant/Current Module Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x28++0x13
|
|
line.long 0x00 "CPNOM,Constant Power Nominal Threshold Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " NOM_CURRENT_UPPER ,Configures INOM value used in Constant Power/Constant Current Calculations"
|
|
hexmask.long.word 0x00 0.--9. 1. " NOM_CURRENT_LOWER ,Configures INOM value used in Constant Power/Constant Current Calculations"
|
|
line.long 0x04 "CPMAX,Constant Power Max Threshold Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " MAX_CURRENT_UPPER ,Configures IMAX value used in Constant Power/Constant Current Calculations"
|
|
hexmask.long.word 0x04 0.--9. 1. " MAX_CURRENT_LOWER ,Configures IMAX value used in Constant Power/Constant Current Calculations"
|
|
line.long 0x08 "CPCONFIG,Constant Power Configuration Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " MAX_CURRENT ,Configures IMAX setpoint used in Constant Power/Constant Current Calculations in Max Current mode"
|
|
hexmask.long.word 0x08 0.--9. 1. " NOM_VOLTAGE ,Configures VNOM setpoint used in Constant Power/Constant Current Calculations in Constant Voltage mode"
|
|
line.long 0x0C "CPMAXPWR,Constant Power Max Power Register"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " MAX_POWER ,Configures PMAX value used in Constant Power/Constant Current calculations in Constant Power mode"
|
|
line.long 0x10 "CPINTTHRESH,Constant Power Integrator Threshold Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " INT_THRESH ,Signed value added to Current Loop Duty value to determine when to freeze Current Loop Integrator"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CPFWDIVISOR,Constant Power Firmware Divisor Register"
|
|
hexmask.word 0x00 0.--9. 1. " FW_DIVISOR ,Value used in Constant Power calculation when firmware value is selected"
|
|
hgroup.word 0x40++0x01
|
|
hide.word 0x00 "CPSTAT,Constant Power Status Register"
|
|
in
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CYCADJCTRL,Cycle Adjustment Control Register"
|
|
bitfld.word 0x00 7.--9. " CYC_ADJ_GAIN ,Configures gain of Cycle Adjustment calculation" "1,2,3,8,16,32,64,128"
|
|
bitfld.word 0x00 5.--6. " CYC_ADJ_SYNC ,Selects which DPWM trigger synchronizes cycle adjustment calculation" "DPWM-0,DPWM-1,DPWM-2,DPWM-3"
|
|
bitfld.word 0x00 3.--4. " SECOND_SAMPLE_SEL ,Configures Front End Module Data used for Second Sample of Cycle Adjustment Calculation" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
bitfld.word 0x00 1.--2. " FIRST_SAMPLE_SEL ,Configures Front End Module Data used for First Sample of Cycle Adjustment Calculation" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " CYC_ADJ_EN ,Cycle Adjustment Calculation Enable" "Disabled,Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CYCADJLIM,Cycle Adjustment Limit Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CYC_ADJ_UPPER_LIMIT ,Cycle Adjustment Calculation signed upper limit value"
|
|
hexmask.long.word 0x00 0.--12. 1. " CYC_ADJ_LOWER_LIM ,Cycle Adjustment Calculation signed lower limit value"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CYCADJSTAT,Cycle Adjustment Status Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CYC_ADJ_CALC ,Signed value representing calculated Cycle Adjustment provided to DPWM module"
|
|
hexmask.long.word 0x00 0.--9. 1. " CYC_ADJ_ERROR ,Signed value representing calculated error"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "GLBEN,Global Enable Register"
|
|
bitfld.word 0x00 10. " FE_CTRL2_EN ,Global Firmware Enable for Front End Control 2 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FE_CTRL1_EN ,Global Firmware Enable for Front End Control 1 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FE_CTRL0_EN ,Global Firmware Enable for Front End Control 0 Module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DPWM3_EN ,Global Firmware Enable for DPWM 3 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DPWM2_EN ,Global Firmware Enable for DPWM 2 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DPWM1_EN ,Global Firmware Enable for DPWM 1 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " DPWM0_EN ,Global Firmware Enable for DPWM 0 Module" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PWMGLBPRD,PWM Global Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,Global PWM Period value"
|
|
if (((d.b(ad:0x00120000+0x58))&0x01)==0x00)
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "SYNCCTRL,Sync Control Register"
|
|
rbitfld.byte 0x00 5. " SYNC_IN ,Value of Sync pin" "Low,High"
|
|
bitfld.byte 0x00 2.--4. " SYNC_MUX_SEL ,Selects which module controls Sync pin output" "DPWM 0,DPWM 1,DPWM 2,DPWM 3,SYNC_OUT,CLKOUT,Oscillator Clock,Driven low"
|
|
bitfld.byte 0x00 1. " SYNC_OUT ,Configure output value for Sync pin" "Low,High"
|
|
bitfld.byte 0x00 0. " SYNC_DIR ,Configure direction of Sync pin" "Output,Input"
|
|
else
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "SYNCCTRL,Sync Control Register"
|
|
rbitfld.byte 0x00 5. " SYNC_IN ,Value of Sync pin" "Low,High"
|
|
bitfld.byte 0x00 2.--4. " SYNC_MUX_SEL ,Selects which module controls Sync pin output" "DPWM 0,DPWM 1,DPWM 2,DPWM 3,SYNC_OUT,CLKOUT,Oscillator Clock,Driven low"
|
|
bitfld.byte 0x00 0. " SYNC_DIR ,Configure direction of Sync pin" "Output,Input"
|
|
endif
|
|
group.long 0x5C++0x0B
|
|
line.long 0x00 "LLCTRL,Light Load Control Register"
|
|
hexmask.long.tbyte 0x00 8.--25. 1. " DPWM_ON_TIME ,DPWM pulse width used for EADC-based light load mode operation"
|
|
bitfld.long 0x00 3. " CYCLE_CNT_EN ,Enables Switching Cycle Counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " LL_FILTER_SEL ,Configures source of filter data for Light Load comparisons" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 0. " LL_EN ,Light Load Mode Enable" "Disabled,Enabled"
|
|
line.long 0x04 "LLENTHRESH,Light Load Enable Threshold Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CYCLE_CNT_THRESH ,Switching Cycle threshold"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " TURN_ON_THRESH ,Filter data threshold where constant width DPWM pulses are enabled when filter data exceeds threshold"
|
|
line.long 0x08 "LLDISTHRESH,Light Load Disable Threshold Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " TURN_OFF_THRESH ,Filter data threshold where constant width DPWM pulses are disabled when filter data falls below threshold"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "APCMCTRL,Analog Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
bitfld.byte 0x00 3. " PCM_LATCH_EN ,Enables latching of Peak Current Flag to end of frame" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " PCM_FE_SEL ,Selects source of Front End Comparator output for Analog Peak Current Mode Control" "Front End Control 0,Front End Control 1,Front End Control 2,?..."
|
|
bitfld.byte 0x00 0. " PCM_EN ,Analog Peak Current Mode Control Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "PCMCTRL,Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
endif
|
|
sif (!cpuis("UCD3138A64")||!cpuis("UCD3138128"))
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "APCMCTRL,Analog Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
bitfld.byte 0x00 3. " PCM_LATCH_EN ,Enables latching of Peak Current Flag to end of frame" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " PCM_FE_SEL ,Selects source of Front End Comparator output for Analog Peak Current Mode Control" "Front End Control 0,Front End Control 1,Front End Control 2,?..."
|
|
bitfld.byte 0x00 0. " PCM_EN ,Analog Peak Current Mode Control Module Enable" "Disabled,Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "LOOPMUXTEST,Loop Mux Test Register (Test Use Only"
|
|
rbitfld.long 0x00 18. " BIST_COMP ,High Speed Loop BIST Complete Status" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " BIST_EN ,High-Speed Loop BIST Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EADC_TRIM_TEST_EN ,EADC Trim Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--7. " GAIN_TRIM ,Sets trim for EADC Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. " AFE_GAIN ,AFE Front End Gain Setting" "1x Gain 8mV/LSB,2x Gain 4mV/LSB,4x Gain 2mV/LSB,8x Gain 1mV/LSB"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x00020000
|
|
width 14.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "FECTRL0MUX,Front End Control 0 Mux Register"
|
|
bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FECTRL1MUX,Front End Control 1 Mux Register"
|
|
bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "FECTRL2MUX,Front End Control 2 Mux Register"
|
|
bitfld.word 0x00 12.--13. " NL_SEL ,Configures source of Non-Linear (NL) comparison results used in Automatic Gain Shifting" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 11. " DPWM3_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DPWM2_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DPWM1_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DPWM0_FRAME_SYNC_EN ,Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DPWM3_B_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DPWM2_B_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DPWM1_B_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-B to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DPWM0_B_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-B to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DPWM3_A_TRIG_EN ,Enables DPWM Trigger from DPWM 3 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DPWM2_A_TRIG_EN ,Enables DPWM Trigger from DPWM 2 PWM-A to Front End Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DPWM1_A_TRIG_EN ,Enables DPWM Trigger from DPWM 1 PWM-A to Front End Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DPWM0_A_TRIG_EN ,Enables DPWM Trigger from DPWM 0 PWM-A to Front End Control" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SAMPTRIGCTRL,Sample Trigger Control Register"
|
|
bitfld.word 0x00 11. " FE2_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FE2_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FE2_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FE2_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FE1_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " FE1_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " FE1_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " FE1_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FE0_TRIG_DPWM3_EN ,Enables Sample Trigger from DPWM 3 to Front End Control 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " FE0_TRIG_DPWM2_EN ,Enables Sample Trigger from DPWM 2 to Front End Control 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " FE0_TRIG_DPWM1_EN ,Enables Sample Trigger from DPWM 1 to Front End Control 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " FE0_TRIG_DPWM0_EN ,Enables Sample Trigger from DPWM 0 to Front End Control 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "EXTDACCTRL,External DAC Control Register"
|
|
bitfld.long 0x00 24.--26. " DAC2_SEL ,Configures DAC 2 setpoint in External DAC Mode" "DAC 0,DAC 1,,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
|
|
bitfld.long 0x00 16.--18. " DAC1_SEL ,Configures DAC 1 setpoint in External DAC Mode" "DAC 0,,DAC 2,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
|
|
bitfld.long 0x00 8.--10. " DAC0_SEL ,Configures DAC 0 setpoint in External DAC Mode" ",DAC 1,DAC 2,Output of Constant Power Module,Filter 0 Output,Filter 1 Output,Filter 2 Output,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " EXT_DAC2_EN ,External DAC 2 Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXT_DAC1_EN ,External DAC 1 Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXT_DAC0_EN ,External DAC 0 Mode Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FILTERMUX,Filter Mux Register"
|
|
bitfld.long 0x04 28.--29. " FILTER2_KCOMP_SEL ,Selects KComp value routed to Filter 2 Module" "KComp0,KComp1,KComp2,?..."
|
|
bitfld.long 0x04 26.--27. " FILTER1_KCOMP_SEL ,Selects KComp value routed to Filter 1 Module" "KComp0,KComp1,KComp2,?..."
|
|
bitfld.long 0x04 24.--25. " FILTER0_KCOMP_SEL ,Selects KComp value routed to Filter 0 Module" "KComp0,KComp1,KComp2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18. " FILTER2_FFWD_SEL ,Configures Feedforward value routed to Filter 2 Module" "Filter 0,Filter 1"
|
|
bitfld.long 0x04 17. " FILTER1_FFWD_SEL ,Configures Feedforward value routed to Filter 1 Module" "Filter 0,Filter 2"
|
|
bitfld.long 0x04 16. " FILTER0_FFWD_SEL ,Configures Feedforward value routed to Filter 0 Module" "Filter 1,Filter 2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " FILTER2_PER_SEL ,Selects source of switching cycle period for Filter 2 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
bitfld.long 0x04 10.--11. " FILTER1_PER_SEL ,Selects source of switching cycle period for Filter 1 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
bitfld.long 0x04 8.--9. " FILTER0_PER_SEL ,Selects source of switching cycle period for Filter 0 Module" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " FILTER2_FE_SEL ,Selects which Front End Module provides data for Filter 2 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
bitfld.long 0x04 2.--3. " FILTER1_FE_SEL ,Selects which Front End Module provides data for Filter 1 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
bitfld.long 0x04 0.--1. " FILTER0_FE_SEL ,Selects which Front End Module provides data for Filter 0 Module" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
line.long 0x08 "FILTERKCOMPA,Filter KComp A Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " KCOMP1 ,Value used in filter output calculations replacing the DPWM switching period value"
|
|
hexmask.long.word 0x08 0.--13. 1. " KCOMP0 ,Value used in filter output calculations replacing the DPWM switching period value"
|
|
textline " "
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "FILTERKCOMPB,Filter KComp B Register"
|
|
hexmask.word 0x00 0.--13. 1. " KCOMP2 ,Value used in filter output calculations replacing the DPWM switching period value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DPWMMUX,DPWM Mux Register"
|
|
bitfld.long 0x00 30.--31. " DPWM3_SYNC_FET_SEL ,Selects Ramp source for DPWM3 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.long 0x00 28.--29. " DPWM2_SYNC_FET_SEL ,Selects Ramp source for DPWM2 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.long 0x00 26.--27. " DPWM1_SYNC_FET_SEL ,Selects Ramp source for DPWM1 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " DPWM0_SYNC_FET_SEL ,Selects Ramp source for DPWM0 PWM-B SyncFET soft on/off" "Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.long 0x00 18.--19. " DPWM3_SYNC_SEL ,Selects Master Sync for DPWM3 when DPWM3 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
bitfld.long 0x00 16.--17. " DPWM2_SYNC_SEL ,Selects Master Sync for DPWM2 when DPWM2 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DPWM1_SYNC_SEL ,Selects Master Sync for DPWM1 when DPWM1 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
bitfld.long 0x00 12.--13. " DPWM0_SYNC_SEL ,Selects Master Sync for DPWM0 when DPWM0 configured in slave mode" "DPWM 0,DPWM 1,DPWM 2,DPWM 3"
|
|
bitfld.long 0x00 9.--11. " DPWM3_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 3" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DPWM2_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 2" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
|
|
bitfld.long 0x00 3.--5. " DPWM1_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 1" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
|
|
bitfld.long 0x00 0.--2. " DPWM0_FILTER_SEL ,Selects source of duty cycle/resonant period for DPWM Module 0" "Filter 0,Filter 1,Filter 2,Constant Power Module,DPWM_ON_TIME,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CPCTRL,Constant Power Control Register"
|
|
bitfld.long 0x00 16. " CPCC_INT_EN ,Constant Power/Constant Current Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_COMP_EN ,Enables comparison of DAC Setpoint and quotient of Max Power/Sense Current in Loop Switching Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FW_DIVISOR_EN ,Enables Firmware value for divisor in Constant Power calculations" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LOWER_COMP_EN ,Enables output of lowest duty from current or voltage loop when Constant Power/Constant Current module controls loop output" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VLOOP_FREEZE_EN ,Enables freezing of Voltage Loop Integrator when current loop selected in Loop Switching configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " VLOOP_SEL ,Configures voltage loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLOOP_SEL ,Configures current loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 5.--7. " THRESH_SEL ,Configures input threshold selected for use in Constant Power comparison" "Filter 0,Filter 1,Filter 2,Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.long 0x00 3.--4. " DIVISOR_SEL ,Configures value used for divisor in Constant Power calculations" "Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CPCC_CONFIG ,Controls Constant Power/Constant Current module configuration" "Average Current Mode,Constant Power Module controls selection of loop,Constant Power Module error switching,?..."
|
|
bitfld.long 0x00 0. " CPCC_EN ,Constant Power Constant/Current Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CPCTRL,Constant Power Control Register"
|
|
bitfld.word 0x00 15. " DAC_COMP_EN ,Enables comparison of DAC Setpoint and quotient of Max Power/Sense Current in Loop Switching Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FW_DIVISOR_EN ,Enables Firmware value for divisor in Constant Power calculations" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " LOWER_COMP_EN ,Enables output of lowest duty from current or voltage loop when Constant Power/Constant Current module controls loop output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " VLOOP_FREEZE_EN ,Enables freezing of Voltage Loop Integrator when current loop selected in Loop Switching configuration" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--11. " VLOOP_SEL ,Configures voltage loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 8.--9. " CLOOP_SEL ,Configures current loop for loop switching mode" "Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 5.--7. " THRESH_SEL ,Configures input threshold selected for use in Constant Power comparison" "Filter 0,Filter 1,Filter 2,Front End 0,Front End 1,Front End 2,?..."
|
|
bitfld.word 0x00 3.--4. " DIVISOR_SEL ,Configures value used for divisor in Constant Power calculations" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.word 0x00 2. " CPCC_INT_EN ,Constant Power/Constant Current Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPCC_CONFIG ,Constant Power/Constant Current module configuration" "Average Current,Constant Power Module controls selection of loop"
|
|
bitfld.word 0x00 0. " CPCC_EN ,Constant Power Constant/Current Module Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x28++0x13
|
|
line.long 0x00 "CPNOM,Constant Power Nominal Threshold Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " NOM_CURRENT_UPPER ,Configures INOM value used in Constant Power/Constant Current Calculations"
|
|
hexmask.long.word 0x00 0.--9. 1. " NOM_CURRENT_LOWER ,Configures INOM value used in Constant Power/Constant Current Calculations"
|
|
line.long 0x04 "CPMAX,Constant Power Max Threshold Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " MAX_CURRENT_UPPER ,Configures IMAX value used in Constant Power/Constant Current Calculations"
|
|
hexmask.long.word 0x04 0.--9. 1. " MAX_CURRENT_LOWER ,Configures IMAX value used in Constant Power/Constant Current Calculations"
|
|
line.long 0x08 "CPCONFIG,Constant Power Configuration Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " MAX_CURRENT ,Configures IMAX setpoint used in Constant Power/Constant Current Calculations in Max Current mode"
|
|
hexmask.long.word 0x08 0.--9. 1. " NOM_VOLTAGE ,Configures VNOM setpoint used in Constant Power/Constant Current Calculations in Constant Voltage mode"
|
|
line.long 0x0C "CPMAXPWR,Constant Power Max Power Register"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " MAX_POWER ,Configures PMAX value used in Constant Power/Constant Current calculations in Constant Power mode"
|
|
line.long 0x10 "CPINTTHRESH,Constant Power Integrator Threshold Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " INT_THRESH ,Signed value added to Current Loop Duty value to determine when to freeze Current Loop Integrator"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CPFWDIVISOR,Constant Power Firmware Divisor Register"
|
|
hexmask.word 0x00 0.--9. 1. " FW_DIVISOR ,Value used in Constant Power calculation when firmware value is selected"
|
|
hgroup.word 0x40++0x01
|
|
hide.word 0x00 "CPSTAT,Constant Power Status Register"
|
|
in
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CYCADJCTRL,Cycle Adjustment Control Register"
|
|
bitfld.word 0x00 7.--9. " CYC_ADJ_GAIN ,Configures gain of Cycle Adjustment calculation" "1,2,3,8,16,32,64,128"
|
|
bitfld.word 0x00 5.--6. " CYC_ADJ_SYNC ,Selects which DPWM trigger synchronizes cycle adjustment calculation" "DPWM-0,DPWM-1,DPWM-2,DPWM-3"
|
|
bitfld.word 0x00 3.--4. " SECOND_SAMPLE_SEL ,Configures Front End Module Data used for Second Sample of Cycle Adjustment Calculation" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
bitfld.word 0x00 1.--2. " FIRST_SAMPLE_SEL ,Configures Front End Module Data used for First Sample of Cycle Adjustment Calculation" "Front End Module 0,Front End Module 1,Front End Module 2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " CYC_ADJ_EN ,Cycle Adjustment Calculation Enable" "Disabled,Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CYCADJLIM,Cycle Adjustment Limit Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CYC_ADJ_UPPER_LIMIT ,Cycle Adjustment Calculation signed upper limit value"
|
|
hexmask.long.word 0x00 0.--12. 1. " CYC_ADJ_LOWER_LIM ,Cycle Adjustment Calculation signed lower limit value"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CYCADJSTAT,Cycle Adjustment Status Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CYC_ADJ_CALC ,Signed value representing calculated Cycle Adjustment provided to DPWM module"
|
|
hexmask.long.word 0x00 0.--9. 1. " CYC_ADJ_ERROR ,Signed value representing calculated error"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "GLBEN,Global Enable Register"
|
|
bitfld.word 0x00 10. " FE_CTRL2_EN ,Global Firmware Enable for Front End Control 2 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FE_CTRL1_EN ,Global Firmware Enable for Front End Control 1 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FE_CTRL0_EN ,Global Firmware Enable for Front End Control 0 Module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DPWM3_EN ,Global Firmware Enable for DPWM 3 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DPWM2_EN ,Global Firmware Enable for DPWM 2 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DPWM1_EN ,Global Firmware Enable for DPWM 1 Module" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " DPWM0_EN ,Global Firmware Enable for DPWM 0 Module" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PWMGLBPRD,PWM Global Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,Global PWM Period value"
|
|
if (((d.b(ad:0x00020000+0x58))&0x01)==0x00)
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "SYNCCTRL,Sync Control Register"
|
|
rbitfld.byte 0x00 5. " SYNC_IN ,Value of Sync pin" "Low,High"
|
|
bitfld.byte 0x00 2.--4. " SYNC_MUX_SEL ,Selects which module controls Sync pin output" "DPWM 0,DPWM 1,DPWM 2,DPWM 3,SYNC_OUT,CLKOUT,Oscillator Clock,Driven low"
|
|
bitfld.byte 0x00 1. " SYNC_OUT ,Configure output value for Sync pin" "Low,High"
|
|
bitfld.byte 0x00 0. " SYNC_DIR ,Configure direction of Sync pin" "Output,Input"
|
|
else
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "SYNCCTRL,Sync Control Register"
|
|
rbitfld.byte 0x00 5. " SYNC_IN ,Value of Sync pin" "Low,High"
|
|
bitfld.byte 0x00 2.--4. " SYNC_MUX_SEL ,Selects which module controls Sync pin output" "DPWM 0,DPWM 1,DPWM 2,DPWM 3,SYNC_OUT,CLKOUT,Oscillator Clock,Driven low"
|
|
bitfld.byte 0x00 0. " SYNC_DIR ,Configure direction of Sync pin" "Output,Input"
|
|
endif
|
|
group.long 0x5C++0x0B
|
|
line.long 0x00 "LLCTRL,Light Load Control Register"
|
|
hexmask.long.tbyte 0x00 8.--25. 1. " DPWM_ON_TIME ,DPWM pulse width used for EADC-based light load mode operation"
|
|
bitfld.long 0x00 3. " CYCLE_CNT_EN ,Enables Switching Cycle Counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " LL_FILTER_SEL ,Configures source of filter data for Light Load comparisons" "Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 0. " LL_EN ,Light Load Mode Enable" "Disabled,Enabled"
|
|
line.long 0x04 "LLENTHRESH,Light Load Enable Threshold Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CYCLE_CNT_THRESH ,Switching Cycle threshold"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " TURN_ON_THRESH ,Filter data threshold where constant width DPWM pulses are enabled when filter data exceeds threshold"
|
|
line.long 0x08 "LLDISTHRESH,Light Load Disable Threshold Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " TURN_OFF_THRESH ,Filter data threshold where constant width DPWM pulses are disabled when filter data falls below threshold"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "APCMCTRL,Analog Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
bitfld.byte 0x00 3. " PCM_LATCH_EN ,Enables latching of Peak Current Flag to end of frame" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " PCM_FE_SEL ,Selects source of Front End Comparator output for Analog Peak Current Mode Control" "Front End Control 0,Front End Control 1,Front End Control 2,?..."
|
|
bitfld.byte 0x00 0. " PCM_EN ,Analog Peak Current Mode Control Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "PCMCTRL,Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
endif
|
|
sif (!cpuis("UCD3138A64")||!cpuis("UCD3138128"))
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "APCMCTRL,Analog Peak Current Mode Control Register"
|
|
bitfld.byte 0x00 4.--5. " PCM_FILTER_SEL ,Selects source of Peak Current Slope Compensation Ramp Start" "Filter 0,Filter 1,Filter 2,Constant Power/Constant Current data"
|
|
bitfld.byte 0x00 3. " PCM_LATCH_EN ,Enables latching of Peak Current Flag to end of frame" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " PCM_FE_SEL ,Selects source of Front End Comparator output for Analog Peak Current Mode Control" "Front End Control 0,Front End Control 1,Front End Control 2,?..."
|
|
bitfld.byte 0x00 0. " PCM_EN ,Analog Peak Current Mode Control Module Enable" "Disabled,Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "LOOPMUXTEST,Loop Mux Test Register (Test Use Only"
|
|
rbitfld.long 0x00 18. " BIST_COMP ,High Speed Loop BIST Complete Status" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " BIST_EN ,High-Speed Loop BIST Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EADC_TRIM_TEST_EN ,EADC Trim Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--7. " GAIN_TRIM ,Sets trim for EADC Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. " AFE_GAIN ,AFE Front End Gain Setting" "1x Gain 8mV/LSB,2x Gain 4mV/LSB,4x Gain 2mV/LSB,8x Gain 1mV/LSB"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "Fault Mux"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
base ad:0x00130000
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ACOMPCTRL0,Analog Comparator Control 0 Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " ACOMP_B_THRESH ,Configures Analog Comparator B Threshold Value"
|
|
bitfld.long 0x00 19.--21. " ACOMP_B_SEL ,Configures Analog Comparator B Threshold" "ACOMP_B_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 18. " ACOMP_B_POL ,Analog Comparator B Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 17. " ACOMP_B_INT_EN ,Analog Comparator B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " ACOMP_A_THRESH ,Configures Analog Comparator A Threshold"
|
|
bitfld.long 0x00 3.--5. " ACOMP_A_SEL ,Configures Analog Comparator A Threshold" "ACOMP_A_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 2. " ACOMP_A_POL ,Analog Comparator A Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 1. " ACOMP_A_INT_EN ,Analog Comparator A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACOMP_EN ,Analog Comparators Enable" "Disabled,Enabled"
|
|
line.long 0x04 "ACOMPCTRL1,Analog Comparator Control 1 Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " ACOMP_D_THRESH ,Configures Analog Comparator D Threshold Value"
|
|
bitfld.long 0x04 19.--21. " ACOMP_D_SEL ,Configures Analog Comparator D Threshold" "ACOMP_D_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x04 18. " ACOMP_D_POL ,Analog Comparator D Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x04 17. " ACOMP_D_INT_EN ,Analog Comparator D Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ACOMP_D_OUT_EN ,Analog Comparator D DAC Output Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 8.--14. 1. " ACOMP_C_THRESH ,Configures Analog Comparator C Threshold"
|
|
bitfld.long 0x04 3.--5. " ACOMP_C_SEL ,Configures Analog Comparator C Threshold" "ACOMP_C_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x04 2. " ACOMP_C_POL ,Analog Comparator C Polarity" "Below treshold,Above treshold"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACOMP_C_INT_EN ,Analog Comparator C Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "ACOMPCTRL2,Analog Comparator Control 2 Register"
|
|
hexmask.long.byte 0x08 24.--30. 1. " ACOMP_F_THRESH ,Configures Analog Comparator F Threshold Value"
|
|
bitfld.long 0x08 22. " ACOMP_F_REF_SEL ,Analog Comparator F Reference Select" "Internal DAC,AD-07"
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|
bitfld.long 0x08 19.--21. " ACOMP_F_SEL ,Configures Analog Comparator F Threshold" "ACOMP_F_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
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|
bitfld.long 0x08 18. " ACOMP_F_POL ,Analog Comparator F Polarity" "Below treshold,Above treshold"
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|
textline " "
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|
bitfld.long 0x08 17. " ACOMP_F_INT_EN ,Analog Comparator F Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " ACOMP_F_OUT_EN ,Analog Comparator F DAC Output Enable" "Disabled,Enabled"
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|
hexmask.long.byte 0x08 8.--14. 1. " ACOMP_E_THRESH ,Configures Analog Comparator E Threshold"
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|
bitfld.long 0x08 3.--5. " ACOMP_E_SEL ,Configures Analog Comparator E Threshold" "ACOMP_E_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
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bitfld.long 0x08 2. " ACOMP_E_POL ,Analog Comparator E Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x08 1. " ACOMP_E_INT_EN ,Analog Comparator E Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ACOMP_E_OUT_EN ,Analog Comparator E DAC Output Enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
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|
line.word 0x00 "ACOMPCTRL3,Analog Comparator Control 3 Register"
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|
hexmask.word.byte 0x00 8.--14. 1. " ACOMP_G_THRESH ,Configures Analog Comparator G Threshold"
|
|
bitfld.word 0x00 3.--5. " ACOMP_G_SEL ,Configures Analog Comparator G Threshold" "ACOMP_G_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
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|
bitfld.word 0x00 2. " ACOMP_G_POL ,Analog Comparator G Polarity" "Below treshold,Above treshold"
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|
bitfld.word 0x00 1. " ACOMP_G_INT_EN ,Analog Comparator G Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.word 0x00 0. " ACOMP_G_OUT_EN ,Analog Comparator G DAC Output Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
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|
line.word 0x00 "EXTFAULTCTRL,External Fault Control Register"
|
|
bitfld.word 0x00 11. " FAULT3_POL ,Polarity configuration for FAULT[3] pin" "Falling edge,Rising edge"
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|
bitfld.word 0x00 10. " FAULT2_POL ,Polarity configuration for FAULT[2] pin" "Falling edge,Rising edge"
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|
bitfld.word 0x00 9. " FAULT1_POL ,Polarity configuration for FAULT[1] pin" "Falling edge,Rising edge"
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|
bitfld.word 0x00 8. " FAULT0_POL ,Polarity configuration for FAULT[0] pin" "Falling edge,Rising edge"
|
|
textline " "
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bitfld.word 0x00 7. " FAULT3_INT_EN ,FAULT[3] Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " FAULT2_INT_EN ,FAULT[2] Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " FAULT1_INT_EN ,FAULT[1] Pin Interrupt Enable" "Disabled,Enabled"
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|
bitfld.word 0x00 4. " FAULT0_INT_EN ,FAULT[0] Pin Interrupt Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.word 0x00 3. " FAULT3_DET_EN ,FAULT[3] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " FAULT2_DET_EN ,FAULT[2] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " FAULT1_DET_EN ,FAULT[1] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " FAULT0_DET_EN ,FAULT[0] Pin Detection Enable" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FAULTMUXINTSTAT,Fault Mux Interrupt Status Register"
|
|
in
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|
rgroup.long 0x18++0x03
|
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line.long 0x00 "FAULTMUXRAWSTAT,Fault Mux Raw Status Register"
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bitfld.long 0x00 16. " DCOMP3 ,Digital Comparator 3 Raw Status" "Not exceeded,Exceeded"
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|
bitfld.long 0x00 15. " DCOMP2 ,Digital Comparator 2 Raw Status" "Not exceeded,Exceeded"
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|
bitfld.long 0x00 14. " DCOMP1 ,Digital Comparator 1 Raw Status" "Not exceeded,Exceeded"
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|
bitfld.long 0x00 13. " DCOMP0 ,Digital Comparator 0 Raw Status" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LFO_FAIL ,Low Frequency Oscillator Failure Raw Status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " FAULT3 ,External Fault Detection on FAULT[3] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 10. " FAULT2 ,External Fault Detection on FAULT[2] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 9. " FAULT1 ,External Fault Detection on FAULT[1] pin" "Not dtedected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FAULT0 ,External Fault Detection on FAULT[0] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 7. " DCM_DETECT ,Discontinuous Conduction Mode Raw Status" "Detected,Not dtedected"
|
|
bitfld.long 0x00 6. " ACOMP_G ,Analog Comparator G Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 5. " ACOMP_F ,Analog Comparator F Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACOMP_E ,Analog Comparator E Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 3. " ACOMP_D ,Analog Comparator D Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 2. " ACOMP_C ,Analog Comparator C Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 1. " ACOMP_B ,Analog Comparator B Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACOMP_A ,Analog Comparator A Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMPRAMP0,Comparator Ramp Control 0 Register"
|
|
bitfld.long 0x00 28.--31. " START_VALUE_SEL ,Configures comparator ramp starting value" "Filter 0,Filter 1,Filter 2,Analog Comparator Threshold A,Analog Comparator Threshold B,Analog Comparator Threshold C,Analog Comparator Threshold D,Analog Comparator Threshold E,Analog Comparator Threshold F,Analog Comparator Threshold G,?..."
|
|
hexmask.long.tbyte 0x00 10.--27. 1. " STEP_SIZE ,Programmable 18-bit unsigned comparator step"
|
|
bitfld.long 0x00 5.--9. " CLKS_PER_STEP ,Selects number of MCLK (HFO_OSC/8) clock cycles per comparator step" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 4. " DPWM3_TRIG_EN ,Enables DPWM Trigger from DPWM 3 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DPWM2_TRIG_EN ,Enables DPWM Trigger from DPWM 2 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DPWM1_TRIG_EN ,Enables DPWM Trigger from DPWM 1 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DPWM0_TRIG_EN ,Enables DPWM Trigger from DPWM 0 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable for Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DCOMPCTRL0,Digital Comparator Control 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 0 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DCOMPCTRL1,Digital Comparator Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 1 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCOMPCTRL2,Digital Comparator Control 2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 2 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCOMPCTRL3,Digital Comparator Control 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 3 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCOMPCNTSTAT,Digital Comparator Counter Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCOMP3_CNT ,Current value of Digital Comparator 3 detection counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCOMP2_CNT ,Current value of Digital Comparator 2 detection counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DCOMP1_CNT ,Current value of Digital Comparator 1 detection counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DCOMP0_CNT ,Current value of Digital Comparator 0 detection counter"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWM0CLIM,DPWM 0 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DPWM0CLIM,DPWM 0 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x34+0x04)++0x01
|
|
line.word 0x00 "DPWM0FLTABDET,DPWM 0 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x34+0x08)++0x03
|
|
line.long 0x00 "DPWM0FAULTDET,DPWM 0 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x34+0x0C)++0x00
|
|
line.byte 0x00 "DPWM0IDEDET,DPWM 0 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "DPWM1CLIM,DPWM 1 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DPWM1CLIM,DPWM 1 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x44+0x04)++0x01
|
|
line.word 0x00 "DPWM1FLTABDET,DPWM 1 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x44+0x08)++0x03
|
|
line.long 0x00 "DPWM1FAULTDET,DPWM 1 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x44+0x0C)++0x00
|
|
line.byte 0x00 "DPWM1IDEDET,DPWM 1 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "DPWM2CLIM,DPWM 2 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DPWM2CLIM,DPWM 2 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x54+0x04)++0x01
|
|
line.word 0x00 "DPWM2FLTABDET,DPWM 2 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x54+0x08)++0x03
|
|
line.long 0x00 "DPWM2FAULTDET,DPWM 2 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x54+0x0C)++0x00
|
|
line.byte 0x00 "DPWM2IDEDET,DPWM 2 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DPWM3CLIM,DPWM 3 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DPWM3CLIM,DPWM 3 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x64+0x04)++0x01
|
|
line.word 0x00 "DPWM3FLTABDET,DPWM 3 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x64+0x08)++0x03
|
|
line.long 0x00 "DPWM3FAULTDET,DPWM 3 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x64+0x0C)++0x00
|
|
line.byte 0x00 "DPWM3IDEDET,DPWM 3 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "HFOFAILDET,HFO Fail Detect Register"
|
|
hexmask.long.tbyte 0x00 1.--17. 1. " HFO_FAIL_THRESH ,Configures threshold where a clear flag is used to clear a counter in the Low Frequency Oscillator domain"
|
|
bitfld.long 0x00 0. " HFO_DETECT_EN ,Enables High Frequency Oscillator Failure Detection logic" "Disabled,Enabled"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "LFOFAILDET,LFO Fail Detect Register"
|
|
bitfld.byte 0x00 2.--6. " LFO_FAIL_THRESH ,Configures threshold where a clear flag is used to clear a counter in the High Frequency Oscillator domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x00 1. " LFO_FAIL_INT_EN ,Low Frequency Oscillator Fail Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LFO_DETECT_EN ,Enables Low Frequency Oscillator Failure Detection logic" "Disabled,Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IDECTRL,IDE Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCM_LIMIT_H ,Value added to 1-Da value to provide hysteresis for exiting DCM mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCM_LIMIT_L ,Value subtracted from 1-Da value to provide hysteresis for entering DCM mode"
|
|
bitfld.long 0x00 13. " DCM_INT_EN ,Enables Discontinuous Conduction Mode (DCM) interrupt generation based on selected Filter output" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--12. 1. " IDE_KD ,Unsigned value used to calculate the DPWM B Pulse width when configured in IDE Mode"
|
|
width 0x0B
|
|
else
|
|
base ad:0x00030000
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ACOMPCTRL0,Analog Comparator Control 0 Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " ACOMP_B_THRESH ,Configures Analog Comparator B Threshold Value"
|
|
bitfld.long 0x00 19.--21. " ACOMP_B_SEL ,Configures Analog Comparator B Threshold" "ACOMP_B_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 18. " ACOMP_B_POL ,Analog Comparator B Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 17. " ACOMP_B_INT_EN ,Analog Comparator B Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " ACOMP_A_THRESH ,Configures Analog Comparator A Threshold"
|
|
bitfld.long 0x00 3.--5. " ACOMP_A_SEL ,Configures Analog Comparator A Threshold" "ACOMP_A_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x00 2. " ACOMP_A_POL ,Analog Comparator A Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 1. " ACOMP_A_INT_EN ,Analog Comparator A Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACOMP_EN ,Analog Comparators Enable" "Disabled,Enabled"
|
|
line.long 0x04 "ACOMPCTRL1,Analog Comparator Control 1 Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " ACOMP_D_THRESH ,Configures Analog Comparator D Threshold Value"
|
|
bitfld.long 0x04 19.--21. " ACOMP_D_SEL ,Configures Analog Comparator D Threshold" "ACOMP_D_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x04 18. " ACOMP_D_POL ,Analog Comparator D Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x04 17. " ACOMP_D_INT_EN ,Analog Comparator D Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ACOMP_D_OUT_EN ,Analog Comparator D DAC Output Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 8.--14. 1. " ACOMP_C_THRESH ,Configures Analog Comparator C Threshold"
|
|
bitfld.long 0x04 3.--5. " ACOMP_C_SEL ,Configures Analog Comparator C Threshold" "ACOMP_C_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
bitfld.long 0x04 2. " ACOMP_C_POL ,Analog Comparator C Polarity" "Below treshold,Above treshold"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACOMP_C_INT_EN ,Analog Comparator C Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "ACOMPCTRL2,Analog Comparator Control 2 Register"
|
|
hexmask.long.byte 0x08 24.--30. 1. " ACOMP_F_THRESH ,Configures Analog Comparator F Threshold Value"
|
|
bitfld.long 0x08 22. " ACOMP_F_REF_SEL ,Analog Comparator F Reference Select" "Internal DAC,AD-07"
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|
bitfld.long 0x08 19.--21. " ACOMP_F_SEL ,Configures Analog Comparator F Threshold" "ACOMP_F_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
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|
bitfld.long 0x08 18. " ACOMP_F_POL ,Analog Comparator F Polarity" "Below treshold,Above treshold"
|
|
textline " "
|
|
bitfld.long 0x08 17. " ACOMP_F_INT_EN ,Analog Comparator F Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " ACOMP_F_OUT_EN ,Analog Comparator F DAC Output Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 8.--14. 1. " ACOMP_E_THRESH ,Configures Analog Comparator E Threshold"
|
|
bitfld.long 0x08 3.--5. " ACOMP_E_SEL ,Configures Analog Comparator E Threshold" "ACOMP_E_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACOMP_E_POL ,Analog Comparator E Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x08 1. " ACOMP_E_INT_EN ,Analog Comparator E Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ACOMP_E_OUT_EN ,Analog Comparator E DAC Output Enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "ACOMPCTRL3,Analog Comparator Control 3 Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " ACOMP_G_THRESH ,Configures Analog Comparator G Threshold"
|
|
bitfld.word 0x00 3.--5. " ACOMP_G_SEL ,Configures Analog Comparator G Threshold" "ACOMP_G_THRESH,Comparator Ramp 0,Filter 0,Filter 1,Filter 2,?..."
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|
bitfld.word 0x00 2. " ACOMP_G_POL ,Analog Comparator G Polarity" "Below treshold,Above treshold"
|
|
bitfld.word 0x00 1. " ACOMP_G_INT_EN ,Analog Comparator G Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " ACOMP_G_OUT_EN ,Analog Comparator G DAC Output Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "EXTFAULTCTRL,External Fault Control Register"
|
|
bitfld.word 0x00 11. " FAULT3_POL ,Polarity configuration for FAULT[3] pin" "Falling edge,Rising edge"
|
|
bitfld.word 0x00 10. " FAULT2_POL ,Polarity configuration for FAULT[2] pin" "Falling edge,Rising edge"
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|
bitfld.word 0x00 9. " FAULT1_POL ,Polarity configuration for FAULT[1] pin" "Falling edge,Rising edge"
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|
bitfld.word 0x00 8. " FAULT0_POL ,Polarity configuration for FAULT[0] pin" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT3_INT_EN ,FAULT[3] Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " FAULT2_INT_EN ,FAULT[2] Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " FAULT1_INT_EN ,FAULT[1] Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " FAULT0_INT_EN ,FAULT[0] Pin Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FAULT3_DET_EN ,FAULT[3] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " FAULT2_DET_EN ,FAULT[2] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " FAULT1_DET_EN ,FAULT[1] Pin Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " FAULT0_DET_EN ,FAULT[0] Pin Detection Enable" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FAULTMUXINTSTAT,Fault Mux Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FAULTMUXRAWSTAT,Fault Mux Raw Status Register"
|
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bitfld.long 0x00 16. " DCOMP3 ,Digital Comparator 3 Raw Status" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 15. " DCOMP2 ,Digital Comparator 2 Raw Status" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 14. " DCOMP1 ,Digital Comparator 1 Raw Status" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 13. " DCOMP0 ,Digital Comparator 0 Raw Status" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LFO_FAIL ,Low Frequency Oscillator Failure Raw Status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " FAULT3 ,External Fault Detection on FAULT[3] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 10. " FAULT2 ,External Fault Detection on FAULT[2] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 9. " FAULT1 ,External Fault Detection on FAULT[1] pin" "Not dtedected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FAULT0 ,External Fault Detection on FAULT[0] pin" "Not dtedected,Detected"
|
|
bitfld.long 0x00 7. " DCM_DETECT ,Discontinuous Conduction Mode Raw Status" "Detected,Not dtedected"
|
|
bitfld.long 0x00 6. " ACOMP_G ,Analog Comparator G Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 5. " ACOMP_F ,Analog Comparator F Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACOMP_E ,Analog Comparator E Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 3. " ACOMP_D ,Analog Comparator D Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 2. " ACOMP_C ,Analog Comparator C Raw Result" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 1. " ACOMP_B ,Analog Comparator B Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACOMP_A ,Analog Comparator A Raw Result" "Not exceeded,Exceeded"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMPRAMP0,Comparator Ramp Control 0 Register"
|
|
bitfld.long 0x00 28.--31. " START_VALUE_SEL ,Configures comparator ramp starting value" "Filter 0,Filter 1,Filter 2,Analog Comparator Threshold A,Analog Comparator Threshold B,Analog Comparator Threshold C,Analog Comparator Threshold D,Analog Comparator Threshold E,Analog Comparator Threshold F,Analog Comparator Threshold G,?..."
|
|
hexmask.long.tbyte 0x00 10.--27. 1. " STEP_SIZE ,Programmable 18-bit unsigned comparator step"
|
|
bitfld.long 0x00 5.--9. " CLKS_PER_STEP ,Selects number of MCLK (HFO_OSC/8) clock cycles per comparator step" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 4. " DPWM3_TRIG_EN ,Enables DPWM Trigger from DPWM 3 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DPWM2_TRIG_EN ,Enables DPWM Trigger from DPWM 2 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DPWM1_TRIG_EN ,Enables DPWM Trigger from DPWM 1 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DPWM0_TRIG_EN ,Enables DPWM Trigger from DPWM 0 to Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable for Analog Comparator Ramp 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DCOMPCTRL0,Digital Comparator Control 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 0 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DCOMPCTRL1,Digital Comparator Control 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 1 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCOMPCTRL2,Digital Comparator Control 2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 2 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCOMPCTRL3,Digital Comparator Control 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CNT_THRESH ,Sets the number of received comparator events before declaring a fault"
|
|
bitfld.long 0x00 18. " COMP_POL ,Digital Comparator 3 Polarity" "Below treshold,Above treshold"
|
|
bitfld.long 0x00 15.--17. " FE_SEL ,Selects which Front End absolute data is used for Digital Comparison with threshold" "Front End 0 absolute data,Front End 1 absolute data,Front End 2 absolute data,Front End 0 error data,Front End 1 error data,Front End 2 error data,?..."
|
|
bitfld.long 0x00 14. " CNT_CLR ,Comparator detection counter clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_CONFIG ,Comparator Detection Counter configuration" "Cleared,Decremeted"
|
|
bitfld.long 0x00 12. " INT_EN ,Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " COMP_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--10. 1. " THRESH ,Sets the digital comparator threshold"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCOMPCNTSTAT,Digital Comparator Counter Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCOMP3_CNT ,Current value of Digital Comparator 3 detection counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCOMP2_CNT ,Current value of Digital Comparator 2 detection counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DCOMP1_CNT ,Current value of Digital Comparator 1 detection counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DCOMP0_CNT ,Current value of Digital Comparator 0 detection counter"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWM0CLIM,DPWM 0 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DPWM0CLIM,DPWM 0 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x34+0x04)++0x01
|
|
line.word 0x00 "DPWM0FLTABDET,DPWM 0 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x34+0x08)++0x03
|
|
line.long 0x00 "DPWM0FAULTDET,DPWM 0 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 0 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x34+0x0C)++0x00
|
|
line.byte 0x00 "DPWM0IDEDET,DPWM 0 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 0 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "DPWM1CLIM,DPWM 1 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DPWM1CLIM,DPWM 1 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x44+0x04)++0x01
|
|
line.word 0x00 "DPWM1FLTABDET,DPWM 1 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x44+0x08)++0x03
|
|
line.long 0x00 "DPWM1FAULTDET,DPWM 1 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 1 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x44+0x0C)++0x00
|
|
line.byte 0x00 "DPWM1IDEDET,DPWM 1 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 1 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "DPWM2CLIM,DPWM 2 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DPWM2CLIM,DPWM 2 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x54+0x04)++0x01
|
|
line.word 0x00 "DPWM2FLTABDET,DPWM 2 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x54+0x08)++0x03
|
|
line.long 0x00 "DPWM2FAULTDET,DPWM 2 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 2 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x54+0x0C)++0x00
|
|
line.byte 0x00 "DPWM2IDEDET,DPWM 2 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 2 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DPWM3CLIM,DPWM 3 Current Limit Control Register"
|
|
bitfld.word 0x00 15. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DPWM3CLIM,DPWM 3 Current Limit Control Register"
|
|
bitfld.long 0x00 16. " ANALOG_PCM_EN ,Enables Analog Peak Current detection result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FAULT0_EN ,Enables FAULT[3] pin for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Current Limit" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x64+0x04)++0x01
|
|
line.word 0x00 "DPWM3FLTABDET,DPWM 3 Fault AB Detection Register"
|
|
bitfld.word 0x00 14. " DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 Fault AB Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 Fault AB detection" "Disabled,Enabled"
|
|
group.long (0x64+0x08)++0x03
|
|
line.long 0x00 "DPWM3FAULTDET,DPWM 3 Fault Detection Register"
|
|
bitfld.long 0x00 30. " PWMB_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PWMB_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PWMB_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PWMB_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PWMB_FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PWMB_FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PWMB_FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PWMB_FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 PWM-B Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 PWM-B Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMA_DCOMP3_EN ,Enables Digital Comparator 3 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PWMA_DCOMP2_EN ,Enables Digital Comparator 2 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMA_DCOMP1_EN ,Enables Digital Comparator 1 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PWMA_DCOMP0_EN ,Enables Digital Comparator 0 result for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWMA_FAULT3_EN ,Enables FAULT[3] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWMA_FAULT2_EN ,Enables FAULT[2] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWMA_FAULT1_EN ,Enables FAULT[1] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWMA_FAULT0_EN ,Enables FAULT[0] pin for DPWM 3 PWM-A Fault Detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWMB_ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PWMB_ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWMB_ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMB_ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWMB_ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMB_ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMB_ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 PWM-A Fault detection" "Disabled,Enabled"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte (0x64+0x0C)++0x00
|
|
line.byte 0x00 "DPWM3IDEDET,DPWM 3 IDE Detection Register"
|
|
bitfld.byte 0x00 6. " ACOMP_G_EN ,Enables Analog Comparator G result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ACOMP_F_EN ,Enables Analog Comparator F result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ACOMP_E_EN ,Enables Analog Comparator E result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ACOMP_D_EN ,Enables Analog Comparator D result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ACOMP_C_EN ,Enables Analog Comparator C result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ACOMP_B_EN ,Enables Analog Comparator B result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ACOMP_A_EN ,Enables Analog Comparator A result for DPWM 3 IDE detection" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "HFOFAILDET,HFO Fail Detect Register"
|
|
hexmask.long.tbyte 0x00 1.--17. 1. " HFO_FAIL_THRESH ,Configures threshold where a clear flag is used to clear a counter in the Low Frequency Oscillator domain"
|
|
bitfld.long 0x00 0. " HFO_DETECT_EN ,Enables High Frequency Oscillator Failure Detection logic" "Disabled,Enabled"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "LFOFAILDET,LFO Fail Detect Register"
|
|
bitfld.byte 0x00 2.--6. " LFO_FAIL_THRESH ,Configures threshold where a clear flag is used to clear a counter in the High Frequency Oscillator domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x00 1. " LFO_FAIL_INT_EN ,Low Frequency Oscillator Fail Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LFO_DETECT_EN ,Enables Low Frequency Oscillator Failure Detection logic" "Disabled,Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IDECTRL,IDE Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCM_LIMIT_H ,Value added to 1-Da value to provide hysteresis for exiting DCM mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCM_LIMIT_L ,Value subtracted from 1-Da value to provide hysteresis for entering DCM mode"
|
|
bitfld.long 0x00 13. " DCM_INT_EN ,Enables Discontinuous Conduction Mode (DCM) interrupt generation based on selected Filter output" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--12. 1. " IDE_KD ,Unsigned value used to calculate the DPWM B Pulse width when configured in IDE Mode"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
tree "RTC (Real Time Clock Interface)"
|
|
base ad:0xFFF7E400
|
|
width 13.
|
|
if (((d.b(ad:0xFFF7F030))&0x02)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "RTCCTRL,RTC Control Register"
|
|
bitfld.byte 0x00 2.--3. " CONFIG_INCL ,Input XTAL clock configuration (analog only)" ",,1.8V Clock Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " PRESET_EN ,Counter preset enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "RTCCTRL,RTC Control Register"
|
|
bitfld.byte 0x00 2.--3. " CONFIG_INCL ,Input XTAL clock configuration (analog only)" ",,3.3V Clock Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " PRESET_EN ,Counter preset enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RTCCOUNT,RTC Counter Register"
|
|
hexmask.long.word 0x00 17.--27. 1. " DAYS ,Current count of days"
|
|
bitfld.long 0x00 12.--16. " HOURS ,Current count of hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 6.--11. " MINS ,Current count of minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SECS ,Current count of seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTCPRESET,RTC Counter Register"
|
|
hexmask.long.word 0x00 17.--27. 1. " DAYS ,Preset value of days"
|
|
bitfld.long 0x00 12.--16. " HOURS ,Preset value of hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 6.--11. " MINS ,Preset value of minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SECS ,Preset value of seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "RTCINTEN,RTC Interrupt Enable Register"
|
|
bitfld.byte 0x00 3. " SEC60 ,Enable interrupts every 60 seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SEC30 ,Enable interrupts every 30 seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SEC10 ,Enable interrupts every 10 seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SEC ,Enable interrupts every 1 seconds" "Disabled,Enabled"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "RTCINTSTAT,RTC Interrupt Status Register"
|
|
bitfld.byte 0x00 3. " SEC60 ,Interrupt flag for 60 seconds" "Not set,Set"
|
|
bitfld.byte 0x00 2. " SEC30 ,Interrupt flag for 30 seconds" "Not set,Set"
|
|
bitfld.byte 0x00 3. " SEC10 ,Interrupt flag for 10 seconds" "Not set,Set"
|
|
bitfld.byte 0x00 3. " SEC ,Interrupt flag for 1 seconds" "Not set,Set"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "RTCPRESCALE,RTC Prescale Register"
|
|
hexmask.word 0x00 0.--9. 1. " PRESCALE ,Prescaler value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("UCD3020*")||cpuis("UCD3040*")||cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
sif (cpuis("UCD3020*")||cpuis("UCD3040*"))
|
|
base ad:0xFFF7F800
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPICTRL,SPI Control Register"
|
|
bitfld.long 0x00 21.--23. " CLKRATE ,Master clock rate relative to ICLK" "/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 16.--20. " FRMLEN ,Sets the number of messages (TXCNT + RXCNT) to hold CS low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11.--15. " RXCNT ,Sets the number bytes to receive after TXCNT bytes have been transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7.--10. " TXCNT ,Sets the bytes to transmit from the SPITX registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WRSTORE ,Places or discards data received during TXCNT" "Discarded,Placed"
|
|
bitfld.long 0x00 5. " WRSTART ,Sets which WRREG initiates transfer" "SPITX-0,SPITX-1"
|
|
bitfld.long 0x00 4. " POL ,Polarity" "0,1"
|
|
bitfld.long 0x00 3. " PHA ,Phase" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Enable interrupt generation to the CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MODE ,Configures SPI mode" "Master,Slave"
|
|
bitfld.long 0x00 0. " MODE ,Enable for SPI Module" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SPISTAT,SPI Status Register"
|
|
bitfld.word 0x00 4.--7. " FRMCNT ,Indicates the number of messages remaining in the FRMLEN before SCS will go inactive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " WCOL ,SPI Write collision" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " BUSY ,SPI interface is busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " SPIF ,SPI Flag" "Not set,Set"
|
|
textline " "
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "SPIFUNC,SPI Pin Function Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin Function" "0,1"
|
|
group.byte 0x0C++0x01
|
|
line.byte 0x00 "SPIDIR,SPI Pin Direction Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin Direction" "0,1"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "SPIGPOUT,SPI Pin GP Out Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin GP Out" "0,1"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "SPIGPIN,SPI Pin GP In Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin GP In" "0,1"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SPITX0,SPI TX Buffer Register"
|
|
line.long 0x04 "SPITX1,SPI TX Buffer Register"
|
|
line.long 0x08 "SPIRX0,SPI RX Buffer Register"
|
|
line.long 0x0C "SPIRX1,SPI RX Buffer Register"
|
|
line.long 0x10 "SPIRX2,SPI RX Buffer Register"
|
|
line.long 0x14 "SPIRX3,SPI RX Buffer Register"
|
|
width 0x0B
|
|
else
|
|
base ad:0xFFF7E800
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPICTRL,SPI Control Register"
|
|
bitfld.long 0x00 21.--23. " CLKRATE ,Master clock rate relative to ICLK" "/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 16.--20. " FRMLEN ,Sets the number of messages (TXCNT + RXCNT) to hold CS low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11.--15. " RXCNT ,Sets the number bytes to receive after TXCNT bytes have been transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7.--10. " TXCNT ,Sets the bytes to transmit from the SPITX registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WRSTORE ,Places or discards data received during TXCNT" "Discarded,Placed"
|
|
bitfld.long 0x00 5. " WRSTART ,Sets which WRREG initiates transfer" "SPITX-0,SPITX-1"
|
|
bitfld.long 0x00 4. " POL ,Polarity" "0,1"
|
|
bitfld.long 0x00 3. " PHA ,Phase" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Enable interrupt generation to the CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MODE ,Configures SPI mode" "Master,Slave"
|
|
bitfld.long 0x00 0. " MODE ,Enable for SPI Module" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SPISTAT,SPI Status Register"
|
|
bitfld.word 0x00 4.--7. " FRMCNT ,Indicates the number of messages remaining in the FRMLEN before SCS will go inactive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " WCOL ,SPI Write collision" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " BUSY ,SPI interface is busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " SPIF ,SPI Flag" "Not set,Set"
|
|
textline " "
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "SPIFUNC,SPI Pin Function Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin Function" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin Function" "0,1"
|
|
group.byte 0x0C++0x01
|
|
line.byte 0x00 "SPIDIR,SPI Pin Direction Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin Direction" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin Direction" "0,1"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "SPIGPOUT,SPI Pin GP Out Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin GP Out" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin GP Out" "0,1"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "SPIGPIN,SPI Pin GP In Register"
|
|
bitfld.byte 0x00 3. " MISO ,MISO Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " MOSI ,MOSI Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " SCS ,SCS Pin GP In" "0,1"
|
|
bitfld.byte 0x00 3. " SCK ,SCK Pin GP In" "0,1"
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SPITX0,SPI TX Buffer Register"
|
|
line.long 0x04 "SPITX1,SPI TX Buffer Register"
|
|
line.long 0x08 "SPIRX0,SPI RX Buffer Register"
|
|
line.long 0x0C "SPIRX1,SPI RX Buffer Register"
|
|
line.long 0x10 "SPIRX2,SPI RX Buffer Register"
|
|
line.long 0x14 "SPIRX3,SPI RX Buffer Register"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "UART (Universal Asynchronous Receiver and Transmitter)"
|
|
sif (cpuis("UCD3138R*")||cpuis("UCD3138A*")||cpuis("UCD3138128"))
|
|
tree "UART0"
|
|
base ad:0xFFF7EC00
|
|
width 16.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "UARTCTRL0,UART Control Register 0"
|
|
bitfld.byte 0x00 7. " STOP ,Configures stop bits for each frame" "1,2"
|
|
bitfld.byte 0x00 6. " PARITY ,Sets odd or even parity" "Odd,Even"
|
|
bitfld.byte 0x00 5. " PARITY_ENA ,Enables parity transmission" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SYNC_MODE ,Selects between Synchronous mode and Asynchronous mode" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ADDR_MODE ,Selects between Idle and Address Bit Mode" "Idle mode,Address mode"
|
|
bitfld.byte 0x00 0.--2. " DATA_SIZE ,Determines the TX and RX byte size" "No data,1-bit,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UARTRXST,UART Receive Status Register"
|
|
rbitfld.byte 0x00 4. " RX_IDLE ,RX Idle status" "Not detected,Detected"
|
|
bitfld.byte 0x00 3. " SLEEP ,Sleep Mode Configuration" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " RX_RDY ,UART Receiver ready status" "Not ready,Ready"
|
|
rbitfld.byte 0x00 1. " RX_WAKE ,UART Receiver wakeup status" "Not entered,Entered"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RX_ENA ,Turns on UART Receiver" "Disabled,Enabled"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "UARTTXST,UART Transmit Status Register"
|
|
bitfld.byte 0x00 7. " CONTINUE ,Configure operation in suspend mode" "Stopped,Continuous"
|
|
bitfld.byte 0x00 6. " LOOPBACK ,Loopback Mode Configuration" "Normal,Loopback"
|
|
rbitfld.byte 0x00 3. " TX_EMPTY ,Transmit buffer status" "Not empty,Empty"
|
|
rbitfld.byte 0x00 2. " TX_RDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_WAKE ,TX wakeup control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TX_ENA ,Turns on TX module" "Disabled,Enabled"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "UARTCTRL3,UART Control Register 3"
|
|
bitfld.byte 0x00 7. " SW_RESET ,Software reset for UART Transmitter/Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " POWERDOWN ,Power-down Transmitter/Receiver Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " CLOCK ,UART Clock Select" "External,Internal"
|
|
bitfld.byte 0x00 4. " RX_INT_ENA ,Enables the interrupts from UART Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TX_INT_ENA ,Enables the interrupts from UART Transmitter" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WAKEUP_INT_ENA ,Enables the wakeup interrupt from UART" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BRKDT_INT_ENA ,Enables the Broken Circuit interrupt from UART Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ERR_INT_ENA ,Enables UART Receiver Error Interrupt" "Disabled,Enabled"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "UARTINTST,UART Interrupt Status Register"
|
|
bitfld.byte 0x00 7. " BUS_BUSY ,UART Receiver Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 5. " FRAME_ERR ,UART Receiver Framing Error" "No error,Error"
|
|
bitfld.byte 0x00 4. " OVERRUN_ERR ,UART Receiver Buffer Overflow" "No error,Error"
|
|
bitfld.byte 0x00 3. " PARITY_ERR ,UART Receiver Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " WAKEUP_INT ,UART Receiver Wakeup Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " BRKDT_INT ,UART Receiver Broken Circuit Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " RX_ERR ,UART Receiver Error" "No error,Error"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "UARTHBAUD_H,UART Baud Divisor High Byte Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "UARTMBAUD_M,UART Baud Divisor Middle Byte Register"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "UARTHBAUD_L,UART Baud Divisor Low Byte Register"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "UARTRXBUF,UART Receive Buffer Register"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "UARTTXBUF,UART Transmit Buffer Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "UARTIOCTRLSCLK,UART I/O SCLK Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Baud Clock"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "UARTIOCTRLRX,UART I/O RX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "UARTIOCTRLTX,UART I/O TX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("UCD3138RGC")||cpuis("UCD3138A*")||cpuis("UCD3138128"))
|
|
tree "UART1"
|
|
base ad:0xFFF7ED00
|
|
width 16.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "UARTCTRL0,UART Control Register 0"
|
|
bitfld.byte 0x00 7. " STOP ,Configures stop bits for each frame" "1,2"
|
|
bitfld.byte 0x00 6. " PARITY ,Sets odd or even parity" "Odd,Even"
|
|
bitfld.byte 0x00 5. " PARITY_ENA ,Enables parity transmission" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SYNC_MODE ,Selects between Synchronous mode and Asynchronous mode" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ADDR_MODE ,Selects between Idle and Address Bit Mode" "Idle mode,Address mode"
|
|
bitfld.byte 0x00 0.--2. " DATA_SIZE ,Determines the TX and RX byte size" "No data,1-bit,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UARTRXST,UART Receive Status Register"
|
|
rbitfld.byte 0x00 4. " RX_IDLE ,RX Idle status" "Not detected,Detected"
|
|
bitfld.byte 0x00 3. " SLEEP ,Sleep Mode Configuration" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " RX_RDY ,UART Receiver ready status" "Not ready,Ready"
|
|
rbitfld.byte 0x00 1. " RX_WAKE ,UART Receiver wakeup status" "Not entered,Entered"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RX_ENA ,Turns on UART Receiver" "Disabled,Enabled"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "UARTTXST,UART Transmit Status Register"
|
|
bitfld.byte 0x00 7. " CONTINUE ,Configure operation in suspend mode" "Stopped,Continuous"
|
|
bitfld.byte 0x00 6. " LOOPBACK ,Loopback Mode Configuration" "Normal,Loopback"
|
|
rbitfld.byte 0x00 3. " TX_EMPTY ,Transmit buffer status" "Not empty,Empty"
|
|
rbitfld.byte 0x00 2. " TX_RDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_WAKE ,TX wakeup control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TX_ENA ,Turns on TX module" "Disabled,Enabled"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "UARTCTRL3,UART Control Register 3"
|
|
bitfld.byte 0x00 7. " SW_RESET ,Software reset for UART Transmitter/Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " POWERDOWN ,Power-down Transmitter/Receiver Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " CLOCK ,UART Clock Select" "External,Internal"
|
|
bitfld.byte 0x00 4. " RX_INT_ENA ,Enables the interrupts from UART Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TX_INT_ENA ,Enables the interrupts from UART Transmitter" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WAKEUP_INT_ENA ,Enables the wakeup interrupt from UART" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BRKDT_INT_ENA ,Enables the Broken Circuit interrupt from UART Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ERR_INT_ENA ,Enables UART Receiver Error Interrupt" "Disabled,Enabled"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "UARTINTST,UART Interrupt Status Register"
|
|
bitfld.byte 0x00 7. " BUS_BUSY ,UART Receiver Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 5. " FRAME_ERR ,UART Receiver Framing Error" "No error,Error"
|
|
bitfld.byte 0x00 4. " OVERRUN_ERR ,UART Receiver Buffer Overflow" "No error,Error"
|
|
bitfld.byte 0x00 3. " PARITY_ERR ,UART Receiver Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " WAKEUP_INT ,UART Receiver Wakeup Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " BRKDT_INT ,UART Receiver Broken Circuit Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " RX_ERR ,UART Receiver Error" "No error,Error"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "UARTHBAUD_H,UART Baud Divisor High Byte Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "UARTMBAUD_M,UART Baud Divisor Middle Byte Register"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "UARTHBAUD_L,UART Baud Divisor Low Byte Register"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "UARTRXBUF,UART Receive Buffer Register"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "UARTTXBUF,UART Transmit Buffer Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "UARTIOCTRLSCLK,UART I/O SCLK Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Baud Clock"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "UARTIOCTRLRX,UART I/O RX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "UARTIOCTRLTX,UART I/O TX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
else
|
|
base ad:0xFFF7D800
|
|
width 16.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "UARTCTRL0,UART Control Register 0"
|
|
bitfld.byte 0x00 7. " STOP ,Configures stop bits for each frame" "1,2"
|
|
bitfld.byte 0x00 6. " PARITY ,Sets odd or even parity" "Odd,Even"
|
|
bitfld.byte 0x00 5. " PARITY_ENA ,Enables parity transmission" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SYNC_MODE ,Selects between Synchronous mode and Asynchronous mode" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ADDR_MODE ,Selects between Idle and Address Bit Mode" "Idle mode,Address mode"
|
|
bitfld.byte 0x00 0.--2. " DATA_SIZE ,Determines the TX and RX byte size" "No data,1-bit,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UARTRXST,UART Receive Status Register"
|
|
rbitfld.byte 0x00 4. " RX_IDLE ,RX Idle status" "Not detected,Detected"
|
|
bitfld.byte 0x00 3. " SLEEP ,Sleep Mode Configuration" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " RX_RDY ,UART Receiver ready status" "Not ready,Ready"
|
|
rbitfld.byte 0x00 1. " RX_WAKE ,UART Receiver wakeup status" "Not entered,Entered"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RX_ENA ,Turns on UART Receiver" "Disabled,Enabled"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "UARTTXST,UART Transmit Status Register"
|
|
bitfld.byte 0x00 7. " CONTINUE ,Configure operation in suspend mode" "Stopped,Continuous"
|
|
bitfld.byte 0x00 6. " LOOPBACK ,Loopback Mode Configuration" "Normal,Loopback"
|
|
rbitfld.byte 0x00 3. " TX_EMPTY ,Transmit buffer status" "Not empty,Empty"
|
|
rbitfld.byte 0x00 2. " TX_RDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TX_WAKE ,TX wakeup control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TX_ENA ,Turns on TX module" "Disabled,Enabled"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "UARTCTRL3,UART Control Register 3"
|
|
bitfld.byte 0x00 7. " SW_RESET ,Software reset for UART Transmitter/Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " POWERDOWN ,Power-down Transmitter/Receiver Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " CLOCK ,UART Clock Select" "External,Internal"
|
|
bitfld.byte 0x00 4. " RX_INT_ENA ,Enables the interrupts from UART Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TX_INT_ENA ,Enables the interrupts from UART Transmitter" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WAKEUP_INT_ENA ,Enables the wakeup interrupt from UART" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BRKDT_INT_ENA ,Enables the Broken Circuit interrupt from UART Receiver" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " ERR_INT_ENA ,Enables UART Receiver Error Interrupt" "Disabled,Enabled"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "UARTINTST,UART Interrupt Status Register"
|
|
bitfld.byte 0x00 7. " BUS_BUSY ,UART Receiver Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 5. " FRAME_ERR ,UART Receiver Framing Error" "No error,Error"
|
|
bitfld.byte 0x00 4. " OVERRUN_ERR ,UART Receiver Buffer Overflow" "No error,Error"
|
|
bitfld.byte 0x00 3. " PARITY_ERR ,UART Receiver Parity Error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " WAKEUP_INT ,UART Receiver Wakeup Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " BRKDT_INT ,UART Receiver Broken Circuit Interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " RX_ERR ,UART Receiver Error" "No error,Error"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "UARTHBAUD_H,UART Baud Divisor High Byte Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "UARTMBAUD_M,UART Baud Divisor Middle Byte Register"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "UARTHBAUD_L,UART Baud Divisor Low Byte Register"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "UARTRXBUF,UART Receive Buffer Register"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "UARTTXBUF,UART Transmit Buffer Register"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "UARTIOCTRLSCLK,UART I/O SCLK Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Baud Clock"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "UARTIOCTRLRX,UART I/O RX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "UARTIOCTRLTX,UART I/O TX Control Register"
|
|
rbitfld.byte 0x00 3. " DATA_IN ,Data received from pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 2. " DATA_OUT ,Data transmitted to pin when configured as GPIO" "0,1"
|
|
bitfld.byte 0x00 1. " IO_FUNC ,Selects the function for UART pins" "GPIO,Normal operation"
|
|
bitfld.byte 0x00 0. " IO_DIR ,Pin direction when configured as GPIO" "Input,Output"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "A/D Converter (Analog/Digital Converter)"
|
|
sif (cpuis("UCD30*"))
|
|
base ad:0xFFF7DC00
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADCCTRL,ADC Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXT_TRIG_DLY ,External ADC Trigger Delay configuration"
|
|
bitfld.long 0x00 23. " EXT_TRIG_GPIO_VAL ,Output value of ADC_EXT_TRIG pin" "Low,High"
|
|
bitfld.long 0x00 22. " EXT_TRIG_GPIO_DIR ,Direction of ADC_EXT_TRIG pin" "Input,Output"
|
|
bitfld.long 0x00 21. " EXT_TRIG_GPIO_EN ,Mode configuration of ADC_EXT_TRIG pin" "Functional,GPIO"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
elif (cpuis("UCD3138RMH")||cpuis("UCD3138RHA"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
else
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,Analog Comparator G"
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADC_ROUND ,Enables rounding of ADC Result to 10 bits" "Not rounded,Rounded"
|
|
bitfld.long 0x00 8.--10. " BYPASS_EN ,Enables dual sample/hold for specific channels" "Enabled channel 2,Enabled channel 1,Enabled channel 0,Disabled,?..."
|
|
bitfld.long 0x00 4.--7. " MAX_CONV ,Maximum number of conversion done in one conversion loop" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 3. " SINGLE_SWEEP ,ADC Conversion Mode" "Continuoues,Single"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_START ,Firmware ADC Conversion Start" "Not initiated,Initiated"
|
|
bitfld.long 0x00 1. " ADC_INT_EN ,End-of-conversion Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC_EN ,ADC12 Enable Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "ADCSTAT,ADC Status Register"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
else
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.byte 0x00 2. " ADC_EXT_TRIG_VAL ,ADC_EXT_TRIG pin value" "Low,High"
|
|
bitfld.byte 0x00 1. " ADC_INT_RAW ,End-of-conversion interrupt flag raw version" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ADC_INT ,End-of-conversion interrupt flag latched version" "No interrupt,Interrupt"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD302*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3040RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "ADCSEQSEL0,ADC Sequence Select Register 0"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADCSEQSEL1,ADC Sequence Select Register 1"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADCSEQSEL2,ADC Sequence Select Register 2"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADCSEQSEL3,ADC Sequence Select Register 3"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 results"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 results"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 results"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 results"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 results"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 results"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result Registers 6"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 6 results"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result Registers 7"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 7 results"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result Registers 8"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 8 results"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result Registers 9"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 9 results"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result Registers 10"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 10 results"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result Registers 11"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 11 results"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result Registers 12"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 12 results"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result Registers 13"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 13 results"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result Registers 14"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 14 results"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result Registers 15"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 15 results"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "ADCAVGRESULT0,ADC Averaged Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 averaged results"
|
|
rgroup.word 0x60++0x01
|
|
line.word 0x00 "ADCAVGRESULT1,ADC Averaged Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 averaged results"
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "ADCAVGRESULT2,ADC Averaged Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 averaged results"
|
|
rgroup.word 0x68++0x01
|
|
line.word 0x00 "ADCAVGRESULT3,ADC Averaged Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 averaged results"
|
|
rgroup.word 0x6C++0x01
|
|
line.word 0x00 "ADCAVGRESULT4,ADC Averaged Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 averaged results"
|
|
rgroup.word 0x70++0x01
|
|
line.word 0x00 "ADCAVGRESULT5,ADC Averaged Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 averaged results"
|
|
sif (cpuis("UCD31*"))
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCCOMPLIM4,ADC Digital Compare Limits Registers 4"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ADCCOMPLIM5,ADC Digital Compare Limits Registers 5"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
endif
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ADCCOMPEN,ADC Digital Compare Enable Register"
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 27. " COMP5_UP_INT_EN ,Digital Comparator 5 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " COMP5_LO_INT_EN ,Digital Comparator 5 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP4_UP_INT_EN ,Digital Comparator 4 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " COMP4_LO_INT_EN ,Digital Comparator 4 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " COMP3_UP_INT_EN ,Digital Comparator 3 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " COMP3_LO_INT_EN ,Digital Comparator 3 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " COMP2_UP_INT_EN ,Digital Comparator 2 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " COMP2_LO_INT_EN ,Digital Comparator 2 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COMP1_UP_INT_EN ,Digital Comparator 1 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " COMP1_LO_INT_EN ,Digital Comparator 1 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP0_UP_INT_EN ,Digital Comparator 0 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " COMP0_LO_INT_EN ,Digital Comparator 0 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 13. " COMP5_DATA_SEL ,Digital Comparator 5 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 12. " COMP4_DATA_SEL ,Digital Comparator 4 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 5. " COMP5_EN ,Digital Comparator 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COMP4_EN ,Digital Comparator 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "ADCCOMPRESULT,ADC Digital Compare Results Register"
|
|
in
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ADCAVGCTRL,ADC Averaging Control Register"
|
|
bitfld.long 0x00 21.--22. " AVG5_CONFIG ,ADC Averaging Module 5 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 20. " AVG5_EN ,ADC Averaging Module 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " AVG4_CONFIG ,ADC Averaging Module 4 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 16. " AVG4_EN ,ADC Averaging Module 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " AVG3_CONFIG ,ADC Averaging Module 3 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 12. " AVG3_EN ,ADC Averaging Module 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " AVG2_CONFIG ,ADC Averaging Module 2 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 8. " AVG2_EN ,ADC Averaging Module 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " AVG1_CONFIG ,ADC Averaging Module 1 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 4. " AVG1_EN ,ADC Averaging Module 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " AVG4_CONFIG ,ADC Averaging Module 0 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 0. " AVG0_EN ,ADC Averaging Module 0 Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
elif (cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
base ad:0x00140000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADCCTRL,ADC Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXT_TRIG_DLY ,External ADC Trigger Delay configuration"
|
|
bitfld.long 0x00 23. " EXT_TRIG_GPIO_VAL ,Output value of ADC_EXT_TRIG pin" "Low,High"
|
|
bitfld.long 0x00 22. " EXT_TRIG_GPIO_DIR ,Direction of ADC_EXT_TRIG pin" "Input,Output"
|
|
bitfld.long 0x00 21. " EXT_TRIG_GPIO_EN ,Mode configuration of ADC_EXT_TRIG pin" "Functional,GPIO"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
elif (cpuis("UCD3138RMH")||cpuis("UCD3138RHA"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
else
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,Analog Comparator G"
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADC_ROUND ,Enables rounding of ADC Result to 10 bits" "Not rounded,Rounded"
|
|
bitfld.long 0x00 8.--10. " BYPASS_EN ,Enables dual sample/hold for specific channels" "Enabled channel 2,Enabled channel 1,Enabled channel 0,Disabled,?..."
|
|
bitfld.long 0x00 4.--7. " MAX_CONV ,Maximum number of conversion done in one conversion loop" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 3. " SINGLE_SWEEP ,ADC Conversion Mode" "Continuoues,Single"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_START ,Firmware ADC Conversion Start" "Not initiated,Initiated"
|
|
bitfld.long 0x00 1. " ADC_INT_EN ,End-of-conversion Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC_EN ,ADC12 Enable Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "ADCSTAT,ADC Status Register"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
else
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.byte 0x00 2. " ADC_EXT_TRIG_VAL ,ADC_EXT_TRIG pin value" "Low,High"
|
|
bitfld.byte 0x00 1. " ADC_INT_RAW ,End-of-conversion interrupt flag raw version" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ADC_INT ,End-of-conversion interrupt flag latched version" "No interrupt,Interrupt"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD302*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3040RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "ADCSEQSEL0,ADC Sequence Select Register 0"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADCSEQSEL1,ADC Sequence Select Register 1"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADCSEQSEL2,ADC Sequence Select Register 2"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADCSEQSEL3,ADC Sequence Select Register 3"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 results"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 results"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 results"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 results"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 results"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 results"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result Registers 6"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 6 results"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result Registers 7"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 7 results"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result Registers 8"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 8 results"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result Registers 9"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 9 results"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result Registers 10"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 10 results"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result Registers 11"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 11 results"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result Registers 12"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 12 results"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result Registers 13"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 13 results"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result Registers 14"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 14 results"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result Registers 15"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 15 results"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "ADCAVGRESULT0,ADC Averaged Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 averaged results"
|
|
rgroup.word 0x60++0x01
|
|
line.word 0x00 "ADCAVGRESULT1,ADC Averaged Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 averaged results"
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "ADCAVGRESULT2,ADC Averaged Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 averaged results"
|
|
rgroup.word 0x68++0x01
|
|
line.word 0x00 "ADCAVGRESULT3,ADC Averaged Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 averaged results"
|
|
rgroup.word 0x6C++0x01
|
|
line.word 0x00 "ADCAVGRESULT4,ADC Averaged Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 averaged results"
|
|
rgroup.word 0x70++0x01
|
|
line.word 0x00 "ADCAVGRESULT5,ADC Averaged Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 averaged results"
|
|
sif (cpuis("UCD31*"))
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCCOMPLIM4,ADC Digital Compare Limits Registers 4"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ADCCOMPLIM5,ADC Digital Compare Limits Registers 5"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
endif
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ADCCOMPEN,ADC Digital Compare Enable Register"
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 27. " COMP5_UP_INT_EN ,Digital Comparator 5 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " COMP5_LO_INT_EN ,Digital Comparator 5 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP4_UP_INT_EN ,Digital Comparator 4 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " COMP4_LO_INT_EN ,Digital Comparator 4 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " COMP3_UP_INT_EN ,Digital Comparator 3 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " COMP3_LO_INT_EN ,Digital Comparator 3 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " COMP2_UP_INT_EN ,Digital Comparator 2 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " COMP2_LO_INT_EN ,Digital Comparator 2 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COMP1_UP_INT_EN ,Digital Comparator 1 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " COMP1_LO_INT_EN ,Digital Comparator 1 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP0_UP_INT_EN ,Digital Comparator 0 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " COMP0_LO_INT_EN ,Digital Comparator 0 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 13. " COMP5_DATA_SEL ,Digital Comparator 5 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 12. " COMP4_DATA_SEL ,Digital Comparator 4 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 5. " COMP5_EN ,Digital Comparator 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COMP4_EN ,Digital Comparator 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "ADCCOMPRESULT,ADC Digital Compare Results Register"
|
|
in
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ADCAVGCTRL,ADC Averaging Control Register"
|
|
bitfld.long 0x00 21.--22. " AVG5_CONFIG ,ADC Averaging Module 5 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 20. " AVG5_EN ,ADC Averaging Module 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " AVG4_CONFIG ,ADC Averaging Module 4 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 16. " AVG4_EN ,ADC Averaging Module 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " AVG3_CONFIG ,ADC Averaging Module 3 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 12. " AVG3_EN ,ADC Averaging Module 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " AVG2_CONFIG ,ADC Averaging Module 2 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 8. " AVG2_EN ,ADC Averaging Module 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " AVG1_CONFIG ,ADC Averaging Module 1 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 4. " AVG1_EN ,ADC Averaging Module 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " AVG4_CONFIG ,ADC Averaging Module 0 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 0. " AVG0_EN ,ADC Averaging Module 0 Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
else
|
|
base ad:0x00040000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADCCTRL,ADC Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXT_TRIG_DLY ,External ADC Trigger Delay configuration"
|
|
bitfld.long 0x00 23. " EXT_TRIG_GPIO_VAL ,Output value of ADC_EXT_TRIG pin" "Low,High"
|
|
bitfld.long 0x00 22. " EXT_TRIG_GPIO_DIR ,Direction of ADC_EXT_TRIG pin" "Input,Output"
|
|
bitfld.long 0x00 21. " EXT_TRIG_GPIO_EN ,Mode configuration of ADC_EXT_TRIG pin" "Functional,GPIO"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
elif (cpuis("UCD3138RMH")||cpuis("UCD3138RHA"))
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,?..."
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
else
|
|
bitfld.long 0x00 20. " EXT_TRIG_EN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " EXT_TRIG_SEL ,Selects which external trigger can start a conversion loop" "HS Loop1 Event 1,HS Loop1 Event 3,HS Loop2 Event 1,HS Loop2 Event 3,HS Loop3 Event 1,HS Loop3 Event 3,HS Loop4 Event 1,HS Loop4 Event 3,ADC_EXT_TRIG,Analog Comparator A,Analog Comparator B,Analog Comparator C,Analog Comparator D,Analog Comparator E,Analog Comparator F,Analog Comparator G"
|
|
bitfld.long 0x00 13.--15. " SAMPLING_SEL ,Defines ADC sampling and hold timing setup" "268KS/s,744KS/s,744KS/s,504KS/s,538KS/s,1008KS/s,268KS/s,1008KS/s"
|
|
bitfld.long 0x00 12. " ADC_SEL_REF ,ADC Voltage Reference Select" "Internal,AVDD"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADC_ROUND ,Enables rounding of ADC Result to 10 bits" "Not rounded,Rounded"
|
|
bitfld.long 0x00 8.--10. " BYPASS_EN ,Enables dual sample/hold for specific channels" "Enabled channel 2,Enabled channel 1,Enabled channel 0,Disabled,?..."
|
|
bitfld.long 0x00 4.--7. " MAX_CONV ,Maximum number of conversion done in one conversion loop" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 3. " SINGLE_SWEEP ,ADC Conversion Mode" "Continuoues,Single"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_START ,Firmware ADC Conversion Start" "Not initiated,Initiated"
|
|
bitfld.long 0x00 1. " ADC_INT_EN ,End-of-conversion Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC_EN ,ADC12 Enable Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "ADCSTAT,ADC Status Register"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
else
|
|
bitfld.byte 0x00 3.--6. " CURRENT_CH ,Shows the currently converting channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.byte 0x00 2. " ADC_EXT_TRIG_VAL ,ADC_EXT_TRIG pin value" "Low,High"
|
|
bitfld.byte 0x00 1. " ADC_INT_RAW ,End-of-conversion interrupt flag raw version" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " ADC_INT ,End-of-conversion interrupt flag latched version" "No interrupt,Interrupt"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD302*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3040RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADCTSTCTRL,ADC Test Control Register"
|
|
bitfld.word 0x00 1. " ADC_SH_BUFFER_EN ,ADC Sample and Hold Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "ADCSEQSEL0,ADC Sequence Select Register 0"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ3_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ3 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ2_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ2 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ1_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ1 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ0_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ0 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADCSEQSEL1,ADC Sequence Select Register 1"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ7_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ7 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ6_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ6 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ5_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ5 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ4_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ4 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADCSEQSEL2,ADC Sequence Select Register 2"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ11_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ11 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ10_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ10 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ9_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ9 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ8_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ8 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADCSEQSEL3,ADC Sequence Select Register 3"
|
|
sif (cpuis("UCD3138RHA")||cpuis("UCD3138RMH"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,,6,,,,,,,13,,15"
|
|
elif (cpuis("UCD302*"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,,,,,,,15"
|
|
elif (cpuis("UCD3040RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,,,,,15"
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,15"
|
|
else
|
|
bitfld.long 0x00 28. " SEQ15_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 24.--27. " SEQ15 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20. " SEQ14_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 16.--19. " SEQ14 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEQ13_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 8.--11. " SEQ13 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " SEQ12_SH ,Dual channel sequence select" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--3. " SEQ12 ,Channel to be converted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 results"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 results"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 results"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 results"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 results"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 results"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result Registers 6"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 6 results"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result Registers 7"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 7 results"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result Registers 8"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 8 results"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result Registers 9"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 9 results"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result Registers 10"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 10 results"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result Registers 11"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 11 results"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result Registers 12"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 12 results"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result Registers 13"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 13 results"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result Registers 14"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 14 results"
|
|
rgroup.word 0x58++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result Registers 15"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 15 results"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "ADCAVGRESULT0,ADC Averaged Result Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 0 averaged results"
|
|
rgroup.word 0x60++0x01
|
|
line.word 0x00 "ADCAVGRESULT1,ADC Averaged Result Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 1 averaged results"
|
|
rgroup.word 0x64++0x01
|
|
line.word 0x00 "ADCAVGRESULT2,ADC Averaged Result Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 2 averaged results"
|
|
rgroup.word 0x68++0x01
|
|
line.word 0x00 "ADCAVGRESULT3,ADC Averaged Result Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 3 averaged results"
|
|
rgroup.word 0x6C++0x01
|
|
line.word 0x00 "ADCAVGRESULT4,ADC Averaged Result Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 4 averaged results"
|
|
rgroup.word 0x70++0x01
|
|
line.word 0x00 "ADCAVGRESULT5,ADC Averaged Result Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " RESULT ,Sequence 5 averaged results"
|
|
sif (cpuis("UCD31*"))
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADCCOMPLIM0,ADC Digital Compare Limits Registers 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADCCOMPLIM1,ADC Digital Compare Limits Registers 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADCCOMPLIM2,ADC Digital Compare Limits Registers 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADCCOMPLIM3,ADC Digital Compare Limits Registers 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCCOMPLIM4,ADC Digital Compare Limits Registers 4"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ADCCOMPLIM5,ADC Digital Compare Limits Registers 5"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPPER_LIMIT ,Configures the upper limit value"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWER_LIMIT ,Configures the lower limit value"
|
|
endif
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ADCCOMPEN,ADC Digital Compare Enable Register"
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 27. " COMP5_UP_INT_EN ,Digital Comparator 5 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " COMP5_LO_INT_EN ,Digital Comparator 5 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP4_UP_INT_EN ,Digital Comparator 4 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " COMP4_LO_INT_EN ,Digital Comparator 4 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " COMP3_UP_INT_EN ,Digital Comparator 3 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " COMP3_LO_INT_EN ,Digital Comparator 3 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " COMP2_UP_INT_EN ,Digital Comparator 2 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " COMP2_LO_INT_EN ,Digital Comparator 2 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COMP1_UP_INT_EN ,Digital Comparator 1 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " COMP1_LO_INT_EN ,Digital Comparator 1 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP0_UP_INT_EN ,Digital Comparator 0 Upper Limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " COMP0_LO_INT_EN ,Digital Comparator 0 Lower Limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD30*"))
|
|
bitfld.long 0x00 13. " COMP5_DATA_SEL ,Digital Comparator 5 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 12. " COMP4_DATA_SEL ,Digital Comparator 4 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 5. " COMP5_EN ,Digital Comparator 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COMP4_EN ,Digital Comparator 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 11. " COMP3_DATA_SEL ,Digital Comparator 3 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 10. " COMP2_DATA_SEL ,Digital Comparator 2 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 9. " COMP1_DATA_SEL ,Digital Comparator 1 Data Select" "Raw,Averaged"
|
|
bitfld.long 0x00 8. " COMP0_DATA_SEL ,Digital Comparator 0 Data Select" "Raw,Averaged"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COMP3_EN ,Digital Comparator 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COMP2_EN ,Digital Comparator 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP1_EN ,Digital Comparator 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMP0_EN ,Digital Comparator 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "ADCCOMPRESULT,ADC Digital Compare Results Register"
|
|
in
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ADCAVGCTRL,ADC Averaging Control Register"
|
|
bitfld.long 0x00 21.--22. " AVG5_CONFIG ,ADC Averaging Module 5 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 20. " AVG5_EN ,ADC Averaging Module 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " AVG4_CONFIG ,ADC Averaging Module 4 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 16. " AVG4_EN ,ADC Averaging Module 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " AVG3_CONFIG ,ADC Averaging Module 3 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 12. " AVG3_EN ,ADC Averaging Module 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " AVG2_CONFIG ,ADC Averaging Module 2 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 8. " AVG2_EN ,ADC Averaging Module 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " AVG1_CONFIG ,ADC Averaging Module 1 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 4. " AVG1_EN ,ADC Averaging Module 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " AVG4_CONFIG ,ADC Averaging Module 0 Configuration" "4 samples,8 samples,16 samples,32 samples"
|
|
bitfld.long 0x00 0. " AVG0_EN ,ADC Averaging Module 0 Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "DPWM (Digital Pulse Width Modulator)"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
tree "DPWM0"
|
|
base ad:0x001D0000
|
|
width 23.
|
|
if (((d.l(ad:0x001D0000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x001D0000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x001D0000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x001D0000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x001D0000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001D0000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM1"
|
|
base ad:0x001A0000
|
|
width 23.
|
|
if (((d.l(ad:0x001A0000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x001A0000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x001A0000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x001A0000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x001A0000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x001A0000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM2"
|
|
base ad:0x00170000
|
|
width 23.
|
|
if (((d.l(ad:0x00170000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00170000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
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bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x00170000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x00170000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00170000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00170000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM3"
|
|
base ad:0x00150000
|
|
width 23.
|
|
if (((d.l(ad:0x00150000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00150000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
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|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
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|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
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|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
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|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
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bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
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bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
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bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
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|
textline " "
|
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bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
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|
textline " "
|
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bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
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|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
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|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x00150000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x00150000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00150000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00150000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
tree "DPWM3"
|
|
base ad:0x00050000
|
|
width 23.
|
|
if (((d.l(ad:0x00050000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00050000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x00050000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x00050000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00050000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00050000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM2"
|
|
base ad:0x00070000
|
|
width 23.
|
|
if (((d.l(ad:0x00070000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00070000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x00070000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x00070000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x00070000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x00070000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM1"
|
|
base ad:0x000A0000
|
|
width 23.
|
|
if (((d.l(ad:0x000A0000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x000A0000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x000A0000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x000A0000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x000A0000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000A0000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM0"
|
|
base ad:0x000D0000
|
|
width 23.
|
|
if (((d.l(ad:0x000D0000))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x000D0000))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
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|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0x000D0000))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0x000D0000+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x000D0000+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x000D0000+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "DPWM0"
|
|
base ad:0xFFF7ED00
|
|
width 23.
|
|
if (((d.l(ad:0xFFF7ED00))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7ED00))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0xFFF7ED00))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0xFFF7ED00+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7ED00+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7ED00+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM1"
|
|
base ad:0xFFF7E900
|
|
width 23.
|
|
if (((d.l(ad:0xFFF7E900))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E900))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0xFFF7E900))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
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|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
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|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
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|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0xFFF7E900+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E900+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E900+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM2"
|
|
base ad:0xFFF7E500
|
|
width 23.
|
|
if (((d.l(ad:0xFFF7E500))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E500))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0xFFF7E500))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0xFFF7E500+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E500+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E500+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPWM3"
|
|
base ad:0xFFF7E100
|
|
width 23.
|
|
if (((d.l(ad:0xFFF7E100))&0xF2)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100))&0xF2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100))&0xF2)==(0x12||0x22))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100))&0xF2)==(0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPWMCTRL0,DPWM Control Register 0"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MULTI_MODE_CLA_A_OFF ,Configures control of PWM A output in Multi-Output Mode" "Filter Calculation,Event1 and Event2"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MIN_DUTY_MODE ,Minimum Duty Cycle Mode" "Disabled,Zero,MIN_DUTY_LOW,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIMIT_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " MSYNC_SLAVE_EN ,Multi-Sync Slave Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " D_ENABLE ,Converts CLA duty value to DPWM as period-CLA duty value" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 11. " PWM_B_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PWM_A_FLT_POL ,Sets the fault output polarity during a disable condition" "Low,High"
|
|
bitfld.long 0x00 9. " BLANK_B_EN ,Comparator Blanking Window B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BLANK_A_EN ,Comparator Blanking Window A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM_B_INV ,PWM B Output Polarity Control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " PWM_A_INV ,PWM A Output Polarity Control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN ,PWM Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E100))&0xF0)==(0x10||0x20))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_BSIDE_ACTIVE_EN ,CBC responds to Fault CBC when" "PWM-A active,PWM-A or PWM-B active"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPWMCTRL1,DPWM Control Register 1"
|
|
bitfld.long 0x00 31. " PRESET_EN ,Counter Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SYNC_FET_EN ,SyncFET Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " BURST_EN ,Burst (Light Load) Mode Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CLA_DUTY_ADJ_EN ,Enables CLA Duty Adjust from Current/Flux Balancing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SYNC_OUT_DIV_SEL ,The divider for generating the Sync Out pulse" "Every cycle,2 cycle,3 cycle,4 cycle,5 cycle,6 cycle,7 cycle,8 cycle,9 cycle,10 cycle,11 cycle,12 cycle,13 cycle,14 cycle,15 cycle,16 cycle"
|
|
bitfld.long 0x00 21.--23. " CLA_SCALE ,Scaling for CLA Input Data" "CLA,CLA*2,CLA/2,CLA*4,CLA/4,CLA*8,CLA/8,CLA"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EXT_SYNC_EN ,Slave DPWM to external sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period,Count value equal to Sample Trigger 2,End of Period and Sample Trigger 2"
|
|
else
|
|
bitfld.long 0x00 18. " AUTO_MODE_SEL ,Auto Switching Mode Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EVENT_UP_SEL ,Update End Period Mode" "Anytime,End of Period"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHECK_OVERRIDE ,PWM Check Override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 14. " GLOBAL_PERIOD_EN ,Enables event calculations to use Global Period" "DPWM Period,Global Period"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PWM_B_OE ,Direction for PWM B pin" "Output,Input"
|
|
bitfld.long 0x00 12. " PWM_A_OE ,Direction for PWM A pin" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_B_VAL ,Sets value of PWM B output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO_B_EN ,Enables GPIO mode for PWM B output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPIO_A_VAL ,Sets value of PWM A output in GPIO mode" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO_A_EN ,Enables GPIO mode for PWM A output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PWM_HR_MULTI_OUT_EN ,Control bit for Hi-Res Block" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PWM_HR_MULTI_OUT_EN ,PWM Single Step Frame Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PWM_B_PROT_DIS ,PWM B Asynchronous Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PWM_A_PROT_DIS ,PWM A Asynchronous Protection Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
bitfld.long 0x00 1. " ALL_PHASE_CLK_ENA ,High Speed Oscillator Phase Enable" "Required phases,All phases"
|
|
else
|
|
bitfld.long 0x00 2.--3. " HIRES_SCALE ,Determines resolution of high resolution steps" "PCLK/16,PCLK/8,PCLK/4,PCLK/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " HIRES_DIS ,PWM High Resolution Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.word 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 10. " RESON_DEADTIME_COMP_EN ,Sets the method at which High Side CLADuty is used in calculations" "Filter,Filter minus deadtime"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.word 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.word 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " BLANK_PCM_EN ,Comparator Blanking Window B Enable for PCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " SYNC_IN_DIV_RATIO ,Sets the number of syncs to be masked before a resync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FILTER_DUTY_SEL ,Sets which register is sent to the Resonant Duty input of the Filter" "PWM Period,Event2,DPWM Resonant Duty,?..."
|
|
bitfld.long 0x00 7. " IDE_DUTY_B_EN ,IDE Duty Cycle Side B Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SAMPLE_TRIG1_OVERSAMPLE ,Oversample Select for Sample Trigger 1" "1,/2,/4,/8"
|
|
bitfld.long 0x00 2.--3. " SAMPLE_TRIG1_MODE ,Mode select for Sample Trigger 1" "PWM Sample Trig,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Adaptive,EV1+CLA_DUTY/2 + Fixed + Adaptive"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SAMPLE_TRIG_2_EN ,Sample Trigger 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAMPLE_TRIG_1_EN ,Sample Trigger 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "DPWMPRD,DPWM Period Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " PRD ,PWM Period"
|
|
line.long 0x04 "DPWMEV1,DPWM Event 1 Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " EVENT1 ,Configures the location of Event 1"
|
|
line.long 0x08 "DPWMEV2,DPWM Event 2 Register"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " EVENT2 ,Configures the location of Event 2"
|
|
line.long 0x0C "DPWMEV3,DPWM Event 3 Register"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " EVENT3 ,Configures the location of Event 3"
|
|
if (((d.l(ad:0xFFF7E100))&0xF0)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EVENT4 ,Configures the location of Event 4"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DPWMEV4,DPWM Event 4 Register"
|
|
endif
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DPWMSAMPTRIG1,DPWM Sample Trigger 1 Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x04 "DPWMSAMPTRIG2,DPWM Sample Trigger 2 Register"
|
|
hexmask.long.word 0x04 6.--17. 1. " SAMPLE_TRIGGER ,Configures the location of the sample trigger within a PWM period"
|
|
line.long 0x08 "DPWMPHASETRIG,Phase Trigger Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " PHASE_TRIGGER ,Configures the phase trigger delay within multi-output mode"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "DPWMCYCADJA,DPWM Cycle Adjust A Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "DPWMCYCADJB,DPWM Cycle Adjust B Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "DPWMRESDUTY,DPWM Resonant Duty Register"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 31. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AB_MAX_COUNT ,Fault AB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " B_MAX_COUNT ,Fault B Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " A_MAX_COUNT ,Fault A Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DPWMFLTCTRL,DPWM Fault Control Register"
|
|
bitfld.long 0x00 30. " ALL_FAULT_EN ,DPWM Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CBC_FAULT_EN ,CBC Fault Module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CBC_FAULT_MODE ,CBC Fault Mode" "Raw CBC,Output of CBC"
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " CBC_MAX_COUNT ,Cycle-by-Cycle Fault Count"
|
|
hexmask.long.byte 0x00 14.--20. 1. " AB_MAX_COUNT ,Fault AB Count"
|
|
hexmask.long.byte 0x00 7.--13. 1. " B_MAX_COUNT ,Fault B Count"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_MAX_COUNT ,Fault A Count"
|
|
endif
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "DPWMOVERFLOW,DPWM Overflow Register"
|
|
bitfld.byte 0x00 7. " PWM_B_CHECK ,Value of PWM B internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 6. " PWM_A_CHECK ,Value of PWM A internal check" "Passed,Failed"
|
|
bitfld.byte 0x00 5. " GPIO_B_IN ,Value of PWM B input" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " GPIO_A_IN ,Value of PWM A input" "Low,High"
|
|
bitfld.byte 0x00 3. " OVERFLOW ,PWM Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 2. " OVERFLOW[2] ,CLA Event 4 Overflow Status" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVERFLOW[1] ,CLA Event 3 Overflow Status" "Not overflowed,Overflowed"
|
|
bitfld.byte 0x00 0. " OVERFLOW[0] ,CLA Event 2 Overflow Status" "Not overflowed,Overflowed"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "DPWMINT,DPWM Interrupt Register"
|
|
rbitfld.long 0x00 22. " MODE_SWITCH ,Mode Switching Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 21. " FLT_A ,Fault A Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 20. " FLT_B ,Fault B Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " FLT_AB ,Fault AB Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 18. " FLT_CBC ,Fault Cycle-by-Cycle Flag" "Not asserted,Set"
|
|
rbitfld.long 0x00 17. " PRD ,PWM Period Interrupt Flag" "Not asserted,Set"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " INT ,Interrupt Out" "Not asserted,Set"
|
|
bitfld.long 0x00 11. " MODE_SWITCH_FLAG_CLR ,Mode Switching Flag Clear" "0,Risedge clears"
|
|
bitfld.long 0x00 10. " MODE_SWITCH_FLAG_EN ,Mode Switching Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MODE_SWITCH_INT_EN ,Mode Switching Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FLT_A_INT_EN ,Fault A Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FLT_B_INT_EN ,Fault B Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FLT_AB_INT_EN ,Fault AB Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLT_CBC_INT_EN ,Fault Cycle-by-Cycle Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRD_INT_EN ,PWM Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRD_INT_SCALE ,This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles" "Every cycle,2 cycle,4 cycle,6 cycle,8 cycle,16 cycle,32 cycle,48 cycle,64 cycle,80 cycle,96 cycle,128 cycle,160 cycle,192 cycle,224 cycle,256 cycle"
|
|
line.long 0x04 "DPWMCNTPRE,DPWM Counter Preset Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " PRESET ,Counter preset value"
|
|
line.long 0x08 "DPWMBLKABEG,DPWM Blanking A Begin Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " BLANK_A_BEGIN ,Configures start of Comparator Blanking Window for PWM A"
|
|
line.long 0x0C "DPWMBLKAEND,DPWM Blanking A End Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " BLANK_A_END ,Configures end of Comparator Blanking Window for PWM A"
|
|
line.long 0x10 "DPWMBLKBBEG,DPWM Blanking B Begin Register"
|
|
hexmask.long.word 0x10 4.--17. 1. " BLANK_B_BEGIN ,Configures start of Comparator Blanking Window for PWM B"
|
|
line.long 0x14 "DPWMBLKBEND,,DPWM Blanking B End Register"
|
|
hexmask.long.word 0x14 4.--17. 1. " BLANK_B_END ,Configures end of Comparator Blanking Window for PWM B"
|
|
line.long 0x18 "DPWMMINDUTYHI,DPWM Minimum Duty Cycle High Register"
|
|
hexmask.long.word 0x18 4.--17. 1. " MIN_DUTY_HIGH ,Configures upper threshold for minimum duty cycle logic"
|
|
line.long 0x1C "DPWMMINDUTYLO,DPWM Minimum Duty Cycle Low Register"
|
|
hexmask.long.word 0x1C 4.--17. 1. " MIN_DUTY_LOW ,Configures lower threshold for minimum duty cycle logic"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DPWMADAPTIVE,DPWM Adaptive Sample Register"
|
|
hexmask.word 0x00 0.--13. 1. " ADAPT_SAMP ,Configures Adaptive Sample Adjust"
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "DPWMFLTSTAT,DPWM Fault Status"
|
|
bitfld.byte 0x00 5. " BURST ,Burst Mode Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 4. " IDE_DETECT ,IDE Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 3. " FLT_A ,Fault A Detection Status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FLT_B ,Fault B Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 1. " FLT_AB ,Fault AB Detection Status" "Not asserted,Asserted"
|
|
bitfld.byte 0x00 0. " FLT_CBC ,Current Limit Detection Status" "Not asserted,Asserted"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "DPWMAUTOSWHIUPTHRESH,DPWM Auto Switch High Upper Thresh Register"
|
|
hexmask.long.word 0x00 4.--17. 1. " AUTO_SWITCH_HIGH_UPPER ,Configures upper threshold for Auto Switch Mode High operation"
|
|
line.long 0x04 "DPWMAUTOSWHILOWTHRESH,DPWM Auto Switch High Lower Thresh Register"
|
|
hexmask.long.word 0x04 4.--17. 1. " AUTO_SWITCH_HIGH_LOWER ,Configures lower threshold for Auto Switch Mode High operation"
|
|
line.long 0x08 "DPWMAUTOSWLOUPTHRESH,DPWM Auto Switch Low Upper Thresh Register"
|
|
hexmask.long.word 0x08 4.--17. 1. " AUTO_SWITCH_LOW_UPPER ,Configures upper threshold for Auto Switch Mode Low operation"
|
|
line.long 0x0C "DPWMAUTOSWLOLOWTHRESH,DPWM Auto Switch Low Lower Thresh Register"
|
|
hexmask.long.word 0x0C 4.--17. 1. " AUTO_SWITCH_LOW_LOWER ,Configures lower threshold for Auto Switch Mode Low operation"
|
|
textline " "
|
|
if (((d.l(ad:0xFFF7E100+0x78))&0xF2)==0x02)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x78))&0xF2)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x78))&0xF2)==(0x12||0x22))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x78))&0xF2)==(0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x78))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DPWMAUTOMAX,DPWM Auto Config Max Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0xFFF7E100+0x7C))&0xF2)==0x02)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x7C))&0xF2)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation" "CBC disabled,CBC enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x7C))&0xF2)==(0x12||0x22))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x7C))&0xF2)==(0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBC_ADV_CNT_EN ,Selects cycle-by-cycle of operation(PWM-A and PWM-B)" "Independently,Matching enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7E100+0x7C))&0xF2)!=(0x00||0x10||0x20))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DPWMAUTOMID,DPWM Auto Config Mid Register"
|
|
bitfld.long 0x00 28.--31. " PWM_B_INTRA_MUX ,Interchanges DPWM signals post edge generation" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
bitfld.long 0x00 24.--27. " PWM_A_INTRA_MUX ,Combines DPWM signals are prior to HR module" "Pass-through,Edge-gen output,PWM-C,Crossover,Pass-through below A,Pass-through below B,Pass-through below C,Pass-through below level-2 C,Pass-through below level-3 C,?..."
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " MULTI_MODE_CLA_B_OFF ,Configures control of PWM B output in Multi-Output Mode" "Filter Calculation,Event3 and Event4"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " CBC_PWM_C_EN ,Sets if Fault CBC changes output waveform for PWM-C" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CBC_PWM_AB_EN ,Sets if Fault CBC changes output waveform for PWM-A and PWM-B" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.long 0x00 16. " MASTER_SYNC_CNTL_SEL ,Configures master sync location" "Phase Trigger,CLA"
|
|
bitfld.long 0x00 13. " CBC_SYNC_CUR_LIM_EN ,Sets if the current limit affects slave sync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--6. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
else
|
|
bitfld.long 0x00 12. " RESON_MODE_FIXED_DUTY_EN ,Configures how duty cycle is controlled in Resonance Mode" "Filter,Auto Switch High"
|
|
bitfld.long 0x00 4.--7. " PWM_MODE ,DPWM Mode" "Normal,Resontant,Multi-Output,Triangular,Leading,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLA_EN ,CLA Processing Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DPWMCTRL2,DPWM Control Register 2"
|
|
bitfld.long 0x00 16. " EDGE_EN ,Enables edge generate module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " A_ON_EDGE ,Select input edge to trigger A ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " A_OFF_EDGE ,Select input edge to trigger A OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
bitfld.long 0x00 4.--6. " B_ON_EDGE ,Select input edge to trigger B ON output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_OFF_EDGE ,Select input edge to trigger B OFF output edge" "DPWM posedge A,DPWM negedge A,DPWM posedge B,DPWM negedge B,Below (n+1) DPWM posedge A,Below (n+1) DPWM negedge A,Below (n+1) DPWM posedge B,Below (n+1) DPWM negedge B"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPWMFILTERDUTYREAD,DPWM Filter Duty Read Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_DUTY ,Filter Duty value received by DPWM Module"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMBISTSTAT,DPWM BIST Status Register"
|
|
hexmask.word 0x00 0.--14. 1. " BIST_CNT ,BIST Count accumulated during BIST test"
|
|
else
|
|
rgroup.word 0x88++0x01
|
|
line.word 0x00 "DPWMCBCLOCATION,DPWM CBC Location"
|
|
hexmask.word 0x00 0.--13. 1. " CBC_LOCATION ,Holds counter value of last CBC event"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("UCD31*"))
|
|
tree "Filter"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
tree "Filter 0"
|
|
base ad:0x001C0000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Filter 1"
|
|
base ad:0x00190000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Filter 2"
|
|
base ad:0x00160000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Filter 0"
|
|
base ad:0x000C0000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Filter 1"
|
|
base ad:0x00090000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Filter 2"
|
|
base ad:0x00060000
|
|
width 16.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FILTERSTATUS,Filter Status Register"
|
|
bitfld.byte 0x00 4. " FILTER_BUSY ,Filter Busy Indicator" "Not busy,Busy"
|
|
bitfld.byte 0x00 3. " YN_LOW_CLAMP ,PID Output Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 2. " YN_HIGH_CLAMP ,PID Output High Rail Indicator" "Not equal,Equal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " KI_YN_LOW_CLAMP ,KI Feedback Low Rail Indicator" "Not equal,Equal"
|
|
bitfld.byte 0x00 0. " KI_YN_HIGH_CLAMP ,KI Feedback High Rail Indicator" "Not equal,Equal"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FILTERCTRL,Filter Control Register"
|
|
bitfld.word 0x00 15. " KI_ADDER_MODE ,Configures addition of Xn and Xn-1 in Integral branch" "Xn,Xn + Xn - 1"
|
|
bitfld.word 0x00 14. " PERIOD_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Period value in Resonant Mode" "Switching period,KComp"
|
|
bitfld.word 0x00 12.--13. " OUTPUT_MULT_SEL ,Selects output multiplicand used for multiplying with filter output to calculate DPWM Duty value" "KComp,Switching period,Feed-Forward,Resonant Duty"
|
|
bitfld.word 0x00 9.--11. " YN_SCALE ,Controls scaling of Yn value to compensate for filter coefficient scaling" "Not scaled,Right shifted by 1,Right shifted by 2,Right shifted by 3,Left shifted by 4,Left shifted by 3,Left shifted by 2,Left shifted by 1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " NL_MODE ,Sets non-linear gain table configuration" "Non-symmetric,Symmetric"
|
|
bitfld.word 0x00 7. " KD_STALL ,Freezes KD Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 6. " KI_STALL ,Freezes KI Branch" "Recalculated,Stalled"
|
|
bitfld.word 0x00 5. " KP_OFF ,Turns off the KP branch" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " KD_OFF ,Turns off the KD branch" "No,Yes"
|
|
bitfld.word 0x00 3. " KI_OFF ,Turns off the KI branch" "No,Yes"
|
|
bitfld.word 0x00 2. " FORCE_START ,Initiates a filter calculation under firmware control" "Not started,Started"
|
|
bitfld.word 0x00 1. " USE_CPU_SAMPLE ,Forces filter to use error sample from CPU XN" "EADC,CPU XN"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FILTER_EN ,Filter Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CPUXN,CPU XN Register"
|
|
hexmask.word 0x00 0.--8. 1. " CPU_SAMPLE ,Forced Xn value, allows processor to use filter as ALU"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FILTERXNREAD,Filter XN Read Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " XN_M1 ,Signed XN_M1 value"
|
|
hexmask.long.word 0x00 0.--8. 1. " XN ,Signed XN value"
|
|
line.long 0x04 "FILTERKIYNREAD,Filter KI_YN Read Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " KI_YN ,Signed KI_YN value"
|
|
line.long 0x08 "FILTERKDYNREAD,Filter KD_YN Read Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " KD_YN ,Signed KD_YN value"
|
|
line.long 0x0C "FILTERYNREAD,Filter YN Read Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " YN ,Signed YN value"
|
|
group.long 0x1C++0x47
|
|
line.long 0x00 "COEFCONFIG,Coefficient Configuration Register"
|
|
bitfld.long 0x00 27. " BIN6_ALPHA ,Selects which alpha value to use in Bin 6 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 24.--26. " BIN6_CONFIG ,Selects which coefficient set to place in Bin 6 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 23. " BIN5_ALPHA ,Selects which alpha value to use in Bin 5 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 20.--22. " BIN5_CONFIG ,Selects which coefficient set to place in Bin 5 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " BIN4_ALPHA ,Selects which alpha value to use in Bin 4 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 16.--18. " BIN4_CONFIG ,Selects which coefficient set to place in Bin 4 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 15. " BIN3_ALPHA ,Selects which alpha value to use in Bin 3 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 12.--14. " BIN3_CONFIG ,Selects which coefficient set to place in Bin 3 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " BIN2_ALPHA ,Selects which alpha value to use in Bin 2 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 8.--10. " BIN2_CONFIG ,Selects which coefficient set to place in Bin 2 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
bitfld.long 0x00 7. " BIN1_ALPHA ,Selects which alpha value to use in Bin 1 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 4.--6. " BIN1_CONFIG ,Selects which coefficient set to place in Bin 1 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIN0_ALPHA ,Selects which alpha value to use in Bin 0 of Non-Linear Table" "KD_ALPHA_0,KD_ALPHA_1"
|
|
bitfld.long 0x00 0.--2. " BIN0_CONFIG ,Selects which coefficient set to place in Bin 0 of Non-Linear Table" "A,B,C,D,E,F,G,?..."
|
|
line.long 0x04 "FILTERKPCOEF0,Filter KP Coefficient 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " KP_COEF_1 ,KP Coefficient 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " KP_COEF_0 ,KP Coefficient 0"
|
|
line.long 0x08 "FILTERKPCOEF1,Filter KP Coefficient 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " KP_COEF_2 ,KP Coefficient 2"
|
|
line.long 0x0C "FILTERKICOEF0,Filter KI Coefficient 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " KI_COEF_1 ,KI Coefficient 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " KI_COEF_0 ,KI Coefficient 0"
|
|
line.long 0x10 "FILTERKICOEF1,Filter KI Coefficient 1 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " KI_COEF_3 ,KI Coefficient 3"
|
|
hexmask.long.word 0x10 0.--15. 1. " KI_COEF_2 ,KI Coefficient 2"
|
|
line.long 0x14 "FILTERKDCOEF0,Filter KD Coefficient 0 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " KD_COEF_1 ,KD Coefficient 1"
|
|
hexmask.long.word 0x14 0.--15. 1. " KD_COEF_0 ,KD Coefficient 0"
|
|
line.long 0x18 "FILTERKDCOEF0,Filter KD Coefficient 1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " KD_COEF_2 ,KD Coefficient 2"
|
|
line.long 0x1C "FILTERKDALPHA,Filter KD Alpha Register"
|
|
hexmask.long.word 0x1C 16.--24. 1. " KD_ALPHA_1 ,Bank 1 KD Alpha value"
|
|
hexmask.long.word 0x1C 0.--8. 1. " KD_ALPHA_0 ,Bank 0 KD Alpha value"
|
|
line.long 0x20 "FILTERNL0,Filter Nonlinear Limit Register 0"
|
|
hexmask.long.word 0x20 16.--24. 1. " LIMIT1 ,Configures LIMIT1 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x20 0.--8. 1. " LIMIT0 ,Configures LIMIT0 in Nonlinear Coefficient tables"
|
|
line.long 0x24 "FILTERNL1,Filter Nonlinear Limit Register 1"
|
|
hexmask.long.word 0x24 16.--24. 1. " LIMIT3 ,Configures LIMIT3 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x24 0.--8. 1. " LIMIT2 ,Configures LIMIT2 in Nonlinear Coefficient tables"
|
|
line.long 0x28 "FILTERNL2,Filter Nonlinear Limit Register 2"
|
|
hexmask.long.word 0x28 16.--24. 1. " LIMIT5 ,Configures LIMIT5 in Nonlinear Coefficient tables"
|
|
hexmask.long.word 0x28 0.--8. 1. " LIMIT4 ,Configures LIMIT4 in Nonlinear Coefficient tables"
|
|
line.long 0x2C "FILTERKICLPHI,Filter KI Feedback Clamp High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " KI_CLAMP_HIGH ,Sets the upper limit of KI_YN value"
|
|
line.long 0x30 "FILTERKICLPLO,Filter KI Feedback Clamp Low Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " KI_CLAMP_LOW ,Sets the lower limit of KI_YN value"
|
|
line.long 0x34 "FILTERYNCLPHI,Filter YN Clamp High Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " YN_CLAMP_HIGH ,Sets the upper limit of YN value"
|
|
line.long 0x38 "FILTERYNCLPLO,Filter YN Clamp Low Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " YN_CLAMP_LOW ,Sets the lower limit of YN value"
|
|
line.long 0x3C "FILTEROCLPHI,Filter Output Clamp High Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " OUTPUT_CLAMP_HIGH ,Sets the upper limit of filter output value"
|
|
line.long 0x40 "FILTEROCLPHI,Filter Output Clamp Low Register"
|
|
hexmask.long.tbyte 0x40 0.--17. 1. " OUTPUT_CLAMP_LOW ,Sets the lower limit of filter output value"
|
|
line.long 0x44 "FILTERPRESET,Filter Preset Register"
|
|
bitfld.long 0x44 27. " PRESET_EN ,Preset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 24.--26. " PRESET_REG_SEL ,Selects internal filter register to preset by processor" "XN_M1,KI_YN,KD_YN,YN,18-bit Filter Data,?..."
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " PRESET_VALUE ,Value to preset into selected register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("UCD31*"))
|
|
tree "Front End/Ramp Interfaces"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
tree "Front End/Ramp I/F 0"
|
|
base ad:0x001E0000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x001E0000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Front End/Ramp I/F 1"
|
|
base ad:0x001B0000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x001B0000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Front End/Ramp I/F 2"
|
|
base ad:0x00180000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x00180000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Front End/Ramp I/F 0"
|
|
base ad:0x000E0000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x000E0000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Front End/Ramp I/F 1"
|
|
base ad:0x000B0000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x000B0000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Front End/Ramp I/F 2"
|
|
base ad:0x00080000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RAMPCTRL,Ramp Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " SYNC_FET_RAMP_START ,Starting value for the SyncFET Ramp with a resolution of High Frequency Oscillator Period"
|
|
bitfld.long 0x00 12. " RAMP_SAT_EN ,Enables addition or subtraction of DAC Saturation Step when EADC is in saturation" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RAMP_COMP_INT_EN ,Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAMP_DLY_INT_EN ,Enables Ramp I/F Interrupt when ramp delay procedure is complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PREBIAS_INT_EN ,Enables Ramp I/F Interrupt when Pre-Bias procedure is completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PCM_START_SEL ,Peak Current Mode Ramp Start Value Select" "DAC_VALUE,PCM_SEL"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_FET_EN ,Enables SyncFET Ramp Operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " MASTER_SEL ,Selects Master Ramp I/F in slave mode" "Interface 0,Interface 1,Interface 2,?..."
|
|
bitfld.long 0x00 4. " SLAVE_COMP_EN ,Enables syncing of ramp start to Master Ramp I/F Complete pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLAVE_DELAY_EN ,Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CONTROL_EN ,Enables PMBus Control line to initiate ramp" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIRMWARE_START ,Ramp start bit, self-clearing by ramp logic" "Not initited,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAMP_EN ,Enable Ramp Logic" "Disabled,Enabled"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "RAMPSTAT,Ramp Status Register"
|
|
bitfld.word 0x00 11. " EADC_DONE_RAW ,EADC Conversion Done Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 10. " RAMP_COMP_INT_STATUS ,Ramp Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 9. " RAMP_DLY_INT_STATUS ,Ramp Delay Complete latched status" "Not declared,Declared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PREBIAS_INT_STATUS ,Pre-Bias Complete latched status" "Not declared,Declared"
|
|
bitfld.word 0x00 7. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.word 0x00 6. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EADC_EOC ,Indicates EADC end of conversion" "Not ended,Ended"
|
|
bitfld.word 0x00 4. " PREBIAS_BUSY ,Pre-Bias Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 3. " RAMP_BUSY ,Ramp Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RAMP_COMP_STATUS ,Ramp Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 1. " RAMP_DLY_STATUS ,Ramp Delay Complete, Raw Status" "Not completed,Completed"
|
|
bitfld.word 0x00 0. " PREBIAS_STATUS ,Pre-Bias Complete, Raw Status" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RAMPCYCLE,Ramp Cycle Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " DELAY_CYCLES ,Configures the number of delay cycles before an initiation of ramp sequence"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SWITCH_CYC_PER_STEP ,Selects number of switching cycles per DAC step"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.long 0x00 16. " DAC_DITHER_ON_SAMPLE ,DAC Dithering on based on Sample Trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EADCDAC,EADC DAC Value Register"
|
|
bitfld.word 0x00 15. " DAC_DITHER_EN ,DAC Dithering Enable" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_VALUE ,Programmable DAC Value"
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RAMPDACEND,Ramp DAC Ending Value Register"
|
|
hexmask.word 0x00 0.--13. 1. " RAMP_DAC_VALUE ,Programmable Ramp Ending DAC Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DACSTEP,DAC Step Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DAC_STEP ,Unsigned DAC Step"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "DACSATSTEP,DAC Saturation Step Register"
|
|
hexmask.word 0x00 0.--13. 1. " DAC_SAT_STEP ,DAC Saturation Step"
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADCTRIM,EADC Trim Register"
|
|
bitfld.long 0x00 24.--29. " GAIN3_TRIM ,Sets trim for 8X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " GAIN2_TRIM ,Sets trim for 4X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GAIN1_TRIM ,Sets trim for 2X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " GAIN0_TRIM ,Sets trim for 1X AFE Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((d.l(ad:0x00080000+0x20))&0x600)==(0x200||0x400))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AVG_WEIGHT_EN ,Enables weighted averaging in EADC averaging mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADCCTRL,EADC Control Register"
|
|
bitfld.long 0x00 28. " D2S_COMP_EN ,Analog Front End Ramp Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EN_HYST_HIGH ,Increase comparator trip point by ~70mV" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_HYST_LOW ,Decrease comparator trip point by ~70mV" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " SAMP_TRIG_SCALE ,Provides capability to mask incoming sample triggers to Front End Control(EADC conversion initiated)" "Every sample,Every 2 sample,Every 3 sample,Every 4 sample,Every 5 sample,Every 6 sample,Every 7 sample,Every 8 sample,Every 9 sample,Every 10 sample,Every 11 sample,Every 12 sample,Every 13 sample,Every 14 sample,Every 15 sample,Every 16 sample"
|
|
bitfld.long 0x00 21. " FRAME_SYNC_EN ,Enable synchronization of switched cap front end counter to Switching Cycle Frame boundary" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCFE_CNT_RST ,Force reset of Switched Cap Front End Counter" "Operational,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SCFE_CNT_INIT ,Configures initial Switched Cap Front End Counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " EADC_INV ,Enables EADC Data Inversion on data to filter module" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " AUTO_GAIN_SHIFT_MODE ,Configures Automatic Gain Shifting mode" "Fixed mode,NL mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GAIN_SHIFT_EN ,Enables Automatic Gain Shifting mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AVG_SPATIAL_EN ,Enables spatial mode in EADC averaging mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " AVG_MODE_SEL ,Averaging Mode Configuration" "2x,4x,8x,?..."
|
|
bitfld.long 0x00 6.--8. " EADC_MODE ,Selects EADC Mode Operation" "Standard,Averaging,Non-continuous SAR,Continuous SAR,,Peak Current,Constant Power/Constant Current Control,Constant Power/Constant Current Control 2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " AFE_GAIN ,AFE Front End Gain Setting" "8mV/LSB,4mV/LSB,2mV/LSB,1mV/LSB"
|
|
bitfld.long 0x00 3. " SCFE_GAIN_FILTER_SEL ,Switched Cap Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCFE_CLK_DIV_2 ,Switched Cap Front End Clock Divider Select" "/1,/2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCFE_ENA ,Switch Cap Front Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EADC_ENA ,EADC Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "ACTRL,Analog Control Register"
|
|
bitfld.word 0x00 10.--15. " EADC_REF_TRIM ,EADC Reference Trim Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 9. " EADC_REF_RESET ,EADC Reference Reset" "Not reset,Reset"
|
|
bitfld.word 0x00 8. " EADC_REF_EN ,EADC Reference Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EADC_GAIN_CAL ,EADC Gain Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EADC_OFFSET_CAL ,EADC Offset Calibration Mode Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INT_REF_SEL ,EADC Reference Select" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EXT_V_SE_SEL ,EADC Select" "Internal,External"
|
|
bitfld.word 0x00 0. " ANALOG_ENA ,Analog Front End Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PREBIASCTRL0,Pre-Bias Control Register 0"
|
|
bitfld.long 0x00 17. " PRE_BIAS_POL ,Configures polarity of received error voltage" "Vref-Vin,Vin-Vref"
|
|
bitfld.long 0x00 16. " PRE_BIAS_EN ,Enable Pre-Biasing of Error ADC" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRE_BIAS_RANGE ,Sets the acceptable range around the zero error point"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRE_BIAS_LIMIT ,Sets the acceptable number of samples in which the Error ADC value stays in range before asserting PREBIAS_STATUS"
|
|
line.long 0x04 "PREBIASCTRL1,Pre-Bias Control Register 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAMPLES_PER_ADJ ,Configures the number of EADC samples between Pre-Bias DAC setpoint adjustments"
|
|
hexmask.long.word 0x04 0.--13. 1. " MAX_DAC_ADJ ,Configures the maximum DAC setpoint adjustment step"
|
|
line.long 0x08 "SARCTRL,SAR Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " EADC_WINDOW_2 ,Configures acceptable range of error values to transition to AFE Gain of 2 during SAR process"
|
|
hexmask.long.byte 0x08 16.--23. 1. " EADC_WINDOW_1 ,Configures acceptable range of error values to transition to AFE Gain of 1 during SAR process"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SAR_RANGE ,Configures acceptable range of error values before declaring SAR completion"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SAR_RESOLUTION ,Configures the final resolution for SAR Conversions" "8mV,4mV,2mV,1mV"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "SARTIMING,SAR Timing Register"
|
|
bitfld.word 0x00 8.--10. " SAR_TIMING_UPPER ,Configures timing for Bits 9:8 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--6. " SAR_TIMING_MID ,Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " SAR_TIMING_LOWER ,Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EADCVALUE,EADC Value Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " ABS_VALUE ,Absolute Value calculated by Front End Control Module"
|
|
bitfld.long 0x00 15. " EADC_SAT_HIGH ,EADC Saturation High Indicator" "Not saturated,Saturated"
|
|
bitfld.long 0x00 14. " EADC_SAT_LOW ,EADC Saturation Low Indicator" "Not saturated,Saturated"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "EADCRAWVALUE,EADC Raw Value Register"
|
|
hexmask.word 0x00 0.--8. 1. " RAW_ERROR_VALUE ,Signed 9-bit Error value measured by Front End Control Module"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "DACSTAT,DAC Status Register"
|
|
hexmask.word 0x00 0.--9. 1. " DAC_VALUE ,Current 10-bit Value sent to DAC"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("UCD31*"))
|
|
tree "Miscellaneous Analog Control"
|
|
base ad:0xFFF7F000
|
|
width 12.
|
|
sif (cpuis("UCD3138*")&&!cpuis("UCD3138A64")&&!cpuis("UCD3138128"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLKTRIM,Clock Trim Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HFO_CLK_TRIM ,High Frequency Oscillator Clock Trim"
|
|
bitfld.long 0x00 6.--7. " HFO_SEL_RANGE ,High Frequency Oscillator Range Select" "0,1,2,3"
|
|
bitfld.long 0x00 5. " HFO_LN_FILTER_EN ,High Frequency Oscillator Low Noise Filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LFO_DISABLE ,Low Frequency Oscillator Disable" "No,Yes"
|
|
bitfld.long 0x00 1.--3. " HFO_THERM_TRIM ,High Frequency Oscillator Thermal Coefficient Trim" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HFO_ENABLE ,High Frequency Oscillator Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLKTRIM,Clock Trim Register"
|
|
bitfld.long 0x00 16. " RESET_DISABLE ,Firmware disable of RESET pin" "No,Yes"
|
|
bitfld.long 0x00 12.--15. " HFO_FINE_TRIM ,High Frequency Oscillator Clock Fine Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " HFO_COARSE_TRIM ,High Frequency Oscillator Clock Coarse Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "PKGID,Package ID Register"
|
|
bitfld.byte 0x00 0.--1. " PKG_ID ,Represents package type of device" "80-pin,?..."
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "PKGID,Package ID Register"
|
|
bitfld.byte 0x00 0.--1. " PKG_ID ,Represents package type of device" "64-pin,40-pin,?..."
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "BROWNOUT,Brownout Register"
|
|
rbitfld.byte 0x00 2. " INT ,Brownout Interrupt Status" "No brownout,Brownout"
|
|
bitfld.byte 0x00 1. " INT_EN ,Brownout Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " INT_EN ,Brownout Comparator Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "GLBIOEN,Global I/O EN Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 31. " TMR_PWM[2] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TMR_PWM[3] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FAULT[3] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 29. " FAULT[3] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " ADC_EXT_TRIG ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TCK ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TDO ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 25. " TMS ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TDI ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SCI_TX[1] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 25. " TMS ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TDI ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 22. " SCI_TX[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SCI_RX[1] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCI_RX[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 22. " SCI_TX[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SCI_RX[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 19. " TMR_CAP[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TMR_PWM[1] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TMR_PWM[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 19. " TMR_CAP[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TMR_PWM[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 16. " TMR_CAP[1] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " I2C_DATA ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CONTROL ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 16. " PMBUS_CLK ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PMBUS_DATA ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CONTROL ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 13. " ALERT ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EXT_INT ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FAULT[2] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 13. " ALERT ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FAULT[2] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " FAULT[1] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FAULT[0] ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SYNC ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 7. " DPWM3B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DPWM3A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DPWM2B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPWM2A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DPWM1B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DPWM1A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPWM0B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DPWM0A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " DPWM4B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DPWM4A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DPWM3B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPWM3A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DPWM2B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DPWM2A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPWM1B ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DPWM1A ,Enables the global control of digital I/O pin" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "GLBIOOE,Global I/O OE Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x04 31. " TMR_PWM[2] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 30. " TMR_PWM[3] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 29. " FAULT[3] ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
elif (cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x04 29. " FAULT[3] ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " ADC_EXT_TRIG ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 27. " TCK ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 26. " TDO ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x04 25. " TMS ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 24. " TDI ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 23. " SCI_TX[1] ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 25. " TMS ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 24. " TDI ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x04 22. " SCI_TX[0] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 21. " SCI_RX[1] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 20. " SCI_RX[0] ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 22. " SCI_TX[0] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 20. " SCI_RX[0] ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x04 19. " TMR_CAP[0] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 18. " TMR_PWM[1] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 17. " TMR_PWM[0] ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 19. " TMR_CAP[0] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 17. " TMR_PWM[0] ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x04 16. " TMR_CAP[1] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 15. " I2C_DATA ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 14. " CONTROL ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 16. " PMBUS_CLK ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 15. " PMBUS_DATA ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 14. " CONTROL ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x04 13. " ALERT ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 12. " EXT_INT ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 11. " FAULT[2] ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 13. " ALERT ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 11. " FAULT[2] ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 10. " FAULT[1] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 9. " FAULT[0] ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 8. " SYNC ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x04 7. " DPWM3B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 6. " DPWM3A ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 5. " DPWM2B ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DPWM2A ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 3. " DPWM1B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 2. " DPWM1A ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPWM0B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 0. " DPWM0A ,Controls the output enable signals" "Input,Output"
|
|
else
|
|
bitfld.long 0x04 7. " DPWM4B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 6. " DPWM4A ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 5. " DPWM3B ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DPWM3A ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 3. " DPWM2B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 2. " DPWM2A ,Controls the output enable signals" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPWM1B ,Controls the output enable signals" "Input,Output"
|
|
bitfld.long 0x04 0. " DPWM1A ,Controls the output enable signals" "Input,Output"
|
|
endif
|
|
line.long 0x08 "GLBIOOD,Global I/O Open Drain Control Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x08 31. " TMR_PWM[2] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 30. " TMR_PWM[3] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 29. " FAULT[3] ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
elif (cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x08 29. " FAULT[3] ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28. " ADC_EXT_TRIG ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 27. " TCK ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 26. " TDO ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x08 25. " TMS ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 24. " TDI ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 23. " SCI_TX[1] ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 25. " TMS ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 24. " TDI ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x08 22. " SCI_TX[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 21. " SCI_RX[1] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 20. " SCI_RX[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 22. " SCI_TX[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 20. " SCI_RX[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x08 19. " TMR_CAP[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 18. " TMR_PWM[1] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 17. " TMR_PWM[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 19. " TMR_CAP[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 17. " TMR_PWM[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x08 16. " TMR_CAP[1] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 15. " I2C_DATA ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 14. " CONTROL ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 16. " PMBUS_CLK ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 15. " PMBUS_DATA ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 14. " CONTROL ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x08 13. " ALERT ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 12. " EXT_INT ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 11. " FAULT[2] ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 13. " ALERT ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 11. " FAULT[2] ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 10. " FAULT[1] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 9. " FAULT[0] ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 8. " SYNC ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x08 7. " DPWM3B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 6. " DPWM3A ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 5. " DPWM2B ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
bitfld.long 0x08 4. " DPWM2A ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 3. " DPWM1B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 2. " DPWM1A ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DPWM0B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 0. " DPWM0A ,I/O open drain control" "Normal I/O,Open drain"
|
|
else
|
|
bitfld.long 0x08 7. " DPWM4B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 6. " DPWM4A ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 5. " DPWM3B ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
bitfld.long 0x08 4. " DPWM3A ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 3. " DPWM2B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 2. " DPWM2A ,I/O open drain control" "Normal I/O,Open drain"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DPWM1B ,I/O open drain control" "Normal I/O,Open drain"
|
|
bitfld.long 0x08 0. " DPWM1A ,I/O open drain control" "Normal I/O,Open drain"
|
|
endif
|
|
line.long 0x0C "GLBIOVAL,Global I/O Value Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x0C 31. " TMR_PWM[2] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 30. " TMR_PWM[3] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 29. " FAULT[3] ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
elif (cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x0C 29. " FAULT[3] ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28. " ADC_EXT_TRIG ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 27. " TCK ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 26. " TDO ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x0C 25. " TMS ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 24. " TDI ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 23. " SCI_TX[1] ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 25. " TMS ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 24. " TDI ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x0C 22. " SCI_TX[0] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 21. " SCI_RX[1] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 20. " SCI_RX[0] ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 22. " SCI_TX[0] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 20. " SCI_RX[0] ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x0C 19. " TMR_CAP[0] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 18. " TMR_PWM[1] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 17. " TMR_PWM[0] ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 19. " TMR_CAP[0] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 17. " TMR_PWM[0] ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x0C 16. " TMR_CAP[1] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 15. " I2C_DATA ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 14. " CONTROL ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 16. " PMBUS_CLK ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 15. " PMBUS_DATA ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 14. " CONTROL ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x0C 13. " ALERT ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 12. " EXT_INT ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 11. " FAULT[2] ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 13. " ALERT ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 11. " FAULT[2] ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 10. " FAULT[1] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 9. " FAULT[0] ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 8. " SYNC ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x0C 7. " DPWM3B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 6. " DPWM3A ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 5. " DPWM2B ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " DPWM2A ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 3. " DPWM1B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 2. " DPWM1A ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DPWM0B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 0. " DPWM0A ,The output value of pin in output mode" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 7. " DPWM4B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 6. " DPWM4A ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 5. " DPWM3B ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " DPWM3A ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 3. " DPWM2B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 2. " DPWM2A ,The output value of pin in output mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DPWM1B ,The output value of pin in output mode" "Low,High"
|
|
bitfld.long 0x0C 0. " DPWM1A ,The output value of pin in output mode" "Low,High"
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "GLBIOREAD,Global I/O Read Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 31. " TMR_PWM[2] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 30. " TMR_PWM[3] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 29. " FAULT[3] ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
elif (cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 29. " FAULT[3] ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " ADC_EXT_TRIG ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 27. " TCK ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 26. " TDO ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 25. " TMS ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 24. " TDI ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 23. " SCI_TX[1] ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 25. " TMS ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 24. " TDI ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 22. " SCI_TX[0] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 21. " SCI_RX[1] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 20. " SCI_RX[0] ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 22. " SCI_TX[0] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 20. " SCI_RX[0] ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 19. " TMR_CAP[0] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 18. " TMR_PWM[1] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 17. " TMR_PWM[0] ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 19. " TMR_CAP[0] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 17. " TMR_PWM[0] ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 16. " TMR_CAP[1] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 15. " I2C_DATA ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 14. " CONTROL ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 16. " PMBUS_CLK ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 15. " PMBUS_DATA ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 14. " CONTROL ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64")||cpuis("UCD3138RGC")||cpuis("UCD3138A"))
|
|
bitfld.long 0x00 13. " ALERT ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 12. " EXT_INT ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 11. " FAULT[2] ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " ALERT ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 11. " FAULT[2] ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " FAULT[1] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 9. " FAULT[0] ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 8. " SYNC ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.long 0x00 7. " DPWM3B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 6. " DPWM3A ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 5. " DPWM2B ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPWM2A ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 3. " DPWM1B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 2. " DPWM1A ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPWM0B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 0. " DPWM0A ,The value on signal after I/O muxing" "Low,High"
|
|
else
|
|
bitfld.long 0x00 7. " DPWM4B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 6. " DPWM4A ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 5. " DPWM3B ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPWM3A ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 3. " DPWM2B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 2. " DPWM2A ,The value on signal after I/O muxing" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPWM1B ,The value on signal after I/O muxing" "Low,High"
|
|
bitfld.long 0x00 0. " DPWM1A ,The value on signal after I/O muxing" "Low,High"
|
|
endif
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TEMPSENCTRL,Temp Sensor Control Register"
|
|
bitfld.long 0x00 0. " TEMP_SENSE_DIS ,Temperature Sensor Disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "IOMUX,RTCCTRLI/O Mux Control Register"
|
|
bitfld.byte 0x00 6.--7. " TCAP1_MUX_SEL ,Pin Mux Select" "TMR_CAP_1,TDI,TDO,TMR_CAP_0"
|
|
bitfld.byte 0x00 4.--5. " TCAP0_MUX_SEL ,Pin Mux Select" "TMR_CAP_0,TDI,TDO,TMR_CAP_1"
|
|
bitfld.byte 0x00 1. " RTC_CLK_IN_SEL ,Pin Mux Select" "XTAL_CLK_IN,TCK"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RTC_CLK_OUT_SEL ,Pin Mux Select" "Disabled,TCK"
|
|
else
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "IOMUX,RTCCTRLI/O Mux Control Register"
|
|
bitfld.word 0x00 8.--9. " EXT_TRIG_MUX_SEL ,EXT_TRIG Pin Mux Select" "EXT_TRIG,TCAP,SYNC,PWM-0"
|
|
bitfld.word 0x00 6.--7. " JTAG_CLK_MUX_SEL ,TCK Pin Mux Select" "TCK,TCAP,SYNC,PWM-0"
|
|
bitfld.word 0x00 4.--5. " JTAG_DATA_MUX_SEL ,TDO/TDI Pin Mux Select" "TDO/TDI,SCI_TX-0/SCI_RX-0,ALERT/CONTROL,FAULT-0/FAULT-1"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138RGC"))
|
|
bitfld.word 0x00 2.--3. " SYNC_MUX_SEL ,SYNC Pin Mux Select" "SYNC,TCAP,EXT_TRIG,PWM-0"
|
|
bitfld.word 0x00 1. " UART_MUX_SEL ,SCL/SDA Pins Mux Select" "SCI_TX-1/SCI_RX-1,ALERT/CONTROL"
|
|
bitfld.word 0x00 0. " PMBUS_MUX_SEL ,SCL/SDA Pins Mux Select" "SCL/SDA,SCI_TX-0/SCI_RX-0"
|
|
else
|
|
bitfld.word 0x00 2.--3. " SYNC_MUX_SEL ,SYNC Pin Mux Select" "SYNC,TCAP,EXT_TRIG,PWM-0"
|
|
bitfld.word 0x00 1. " UART_MUX_SEL ,SCL/SDA Pins Mux Select" ",ALERT/CONTROL"
|
|
bitfld.word 0x00 0. " PMBUS_MUX_SEL ,SCL/SDA Pins Mux Select" "SCL/SDA,SCI_TX-0/SCI_RX-0"
|
|
endif
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSCTRL,Current Sharing Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DPWM_DUTY ,Configures Pulse Width/Duty Cycle for DPWM output to Current Sharing circuit"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DPMW_PERIOD ,Configures Period for DPWM output to Current Sharing circuit"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE ,Controls Current Sharing Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TEMPREF,Temperature Reference Register"
|
|
hexmask.word 0x00 0.--11. 1. " TEMP_REF ,Reference measurement taken during factory trim"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PWRDISCTRL,Power Disable Control Register"
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
bitfld.long 0x00 20. " RTC_CLK_EN ,Clock Enable for Real Time Clock Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " I2C_CLK_EN ,Clock Enable for Inter-Integrated Circuit Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI_CLK_EN ,Clock Enable for Serial Peripheral Module" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " PCM_CLK_EN ,Clock Enable for Digital Peak Current Control Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CPCC_CLK_EN ,Clock Enable for Constant Power/Constant Current Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FILTER2_CLK_EN ,Clock Enable for Filter 2 Module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FILTER1_CLK_EN ,Clock Enable for Filter 1 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " FILTER1_CLK_EN ,Clock Enable for Filter 0 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FE_CTRL2_CLK_EN ,Clock Enable for Front End Control 2 Module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FE_CTRL1_CLK_EN ,Clock Enable for Front End Control 1 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FE_CTRL0_CLK_EN ,Clock Enable for Front End Control 0 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DPWM3_CLK_EN ,Clock Enable for DPWM 3 Module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DPWM2_CLK_EN ,Clock Enable for DPWM 2 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DPWM1_CLK_EN ,Clock Enable for DPWM 1 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DPWM0_CLK_EN ,Clock Enable for DPWM 0 Module" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("UCD3138A")||cpuis("UCD3138RGC")||cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
bitfld.long 0x00 5. " SCI1_CLK_EN ,Clock Enable for SCI/UART 1 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SCI0_CLK_EN ,Clock Enable for SCI/UART 0 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADC12_CLK_EN ,Clock Enable for ADC12 Control Module" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " SCI0_CLK_EN ,Clock Enable for SCI/UART 0 Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADC12_CLK_EN ,Clock Enable for ADC12 Control Module" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PMBUS_CLK_EN ,Clock Enable for PMBus Interface Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GIO_CLK_EN ,Clock Enable for GIO Module" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMER_CLK_EN ,Clock Enable for Timer Module" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "PMB (PMBus Interface)"
|
|
sif (cpuis("UCD3138128")||cpuis("UCD3138A64"))
|
|
tree "PMB0"
|
|
base ad:0xFFF7F600
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMBCTRL1,PMBUS Control Register 1"
|
|
bitfld.long 0x00 20. " PRC_CALL ,Master process call message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " GRP_CMD ,Master group command message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PEC_ENA ,Master PEC processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EXT_CMD ,Master extended command code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CMD_ENA ,Master command code enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE_COUNT ,Indicates number of data bytes transmitted in current message"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SLAVE_ADDR ,Specifies the address of the slave to which the current message is directed towards"
|
|
bitfld.long 0x00 0. " RW ,Indicates if current Master initiated message is read operation or write operation" "Write,Read"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PMBTXBUF,PMBus Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from transmit data buffer"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMBRXBUF,PMBus Receive Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from receive data buffer"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMBACK,PMBus Acknowledge Register"
|
|
bitfld.long 0x00 20. " ACK ,Allows firmware to acknowledge or not acknowledge received data" "Not acknowledge,Acknowledge"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PMBST,PMBus Status Register"
|
|
bitfld.long 0x00 21. " SCL_RAW ,PMBus clock pin real time status" "Low,High"
|
|
bitfld.long 0x00 20. " SDA_RAW ,PMBus data pin real time status" "Low,High"
|
|
bitfld.long 0x00 19. " CONTROL_RAW ,Control pin real time status" "Low,High"
|
|
bitfld.long 0x00 18. " ALERT_RAW ,Alert pin real time status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONTROL_EDGE ,Control edge detection status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 16. " ALERT_EDGE ,Alert edge detection status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 15. " MASTER ,Master indicator" "Slave/Idle,Master"
|
|
bitfld.long 0x00 14. " LOST_ARB ,Lost arbitration flag" "Attained control,Lost control"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BUS_FREE ,PMBus free indicator" "Processing,Free"
|
|
bitfld.long 0x00 12. " UNIT_BUSY ,PMBus busy indicator" "Idle,Busy"
|
|
bitfld.long 0x00 11. " RPT_START ,Repeated start flag" "Not repeated,Repeated"
|
|
bitfld.long 0x00 10. " SLAVE_ADDR_READY ,Slave address ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_HIGH_DETECTED ,Clock high detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " CLK_LOW_TIMEOUT ,Clock low timeout status" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " PEC_VALID ,PEC valid indicator" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " NACK ,Not acknowledge flag status" "Accepted,Not accepted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOM ,End of message indicator" "In progress,Message end"
|
|
bitfld.long 0x00 4. " DATA_REQUEST ,Data request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " DATA_READY ,Data ready flag" "Not available,Available"
|
|
bitfld.long 0x00 0.--2. " RD_BYTE_COUNT ,Number of data bytes available in receive data register" "No data,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMBINTM,PMBus Interrupt Mask Register"
|
|
bitfld.long 0x00 9. " CLK_HIGH_TIMEOUT ,Clock high timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " LOST_ARB ,Lost arbitration interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " CONTROL ,Control detection interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " ALERT ,Alert detection interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOM ,End of message interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SLAVE_ADDR_READY ,Slave address ready interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DATA_REQUEST ,Data request interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DATA_READY ,Data ready interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BUS_LOW_TIMEOUT ,Clock low timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " BUS_FREE ,Bus free interrupt mask" "Not masked,Masked"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMBCTRL2,PMBus Control Register 2"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
bitfld.long 0x00 30. " SLAVE_ADDR_2_EN ,Enable auto detection of the 2nd slave address" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 23.--29. 0x800000 " SLAVE_ADDR_2 ,Configures the second device address of the slave"
|
|
endif
|
|
bitfld.long 0x00 21.--22. " RX_BYTE_ACK_CNT ,Configures number of data bytes to automatically acknowledge when receiving data in slave mode" "1 byte,2 bytes,3 bytes,4 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MAN_CMD ,Manual command acknowledgement mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TX_PEC ,Asserted when the slave needs to send a PEC byte at end of message" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 16.--18. " TX_COUNT ,Number of valid bytes in transmit data register" "No bytes,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " PEC_ENA ,PEC processing enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SLAVE_MASK ,The slave mask enables acknowledgement of multiple device addresses by the slave"
|
|
bitfld.long 0x00 7. " MAN_SLAVE_ACK ,Manual Slave Address Acknowledgement Mode" "Automatic,Manual"
|
|
hexmask.long.byte 0x00 0.--6. 0x00 " SLAVE_ADDR , Configures the current device address of the slave"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PMBHSA,PMBus Hold Slave Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x01 " SLAVE_ADDR , Stored device address acknowledged by the slave"
|
|
bitfld.long 0x00 0. " SLAVE_RW , Stored R/W bit from address acknowledged by the slave" "Write,Read"
|
|
if (((d.l(ad:0xFFF7F600+0x20))&0x400000)==0x400000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
bitfld.long 0x00 24. " I2C_MODE_EN ,I2C mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "No,Yes"
|
|
endif
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout disable" "No,Yes"
|
|
bitfld.long 0x00 19. " IBIAS_B_EN ,PMBus current source B control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IBIAS_A_EN ,PMBus current source A control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
bitfld.long 0x00 11. " CNTL_DIR ,Configures direction of Control pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 10. " CNTL_VALUE ,Configures output value of control pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 9. " CNTL_MODE ,Configures mode of control pin" "Functional,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALERT_DIR ,Configures direction of alert pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 7. " ALERT_VALUE ,Configures output value of alert pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 6. " ALERT_MODE ,Configures mode of alert pin" "Functional,GPIO"
|
|
bitfld.long 0x00 5. " CNTL_INT_EDGE ,Control Interrupt Edge Select" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FAST_MODE_PLUS ,Fast mode plus enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBIAS_B_EN ,PMBus current source B control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IBIAS_A_EN ,PMBus current source A control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CNTL_DIR ,Configures direction of Control pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 10. " CNTL_VALUE ,Configures output value of control pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 9. " CNTL_MODE ,Configures mode of control pin" "Functional,GPIO"
|
|
bitfld.long 0x00 8. " ALERT_DIR ,Configures direction of alert pin in GPIO mode" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALERT_VALUE ,Configures output value of alert pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 6. " ALERT_MODE ,Configures mode of alert pin" "Functional,GPIO"
|
|
bitfld.long 0x00 5. " CNTL_INT_EDGE ,Control Interrupt Edge Select" "Falling,Rising"
|
|
bitfld.long 0x00 4. " FAST_MODE_PLUS ,Fast mode plus enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "PMB1"
|
|
base ad:0xFFF7F700
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMBCTRL1,PMBUS Control Register 1"
|
|
bitfld.long 0x00 20. " PRC_CALL ,Master process call message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " GRP_CMD ,Master group command message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PEC_ENA ,Master PEC processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EXT_CMD ,Master extended command code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CMD_ENA ,Master command code enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE_COUNT ,Indicates number of data bytes transmitted in current message"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SLAVE_ADDR ,Specifies the address of the slave to which the current message is directed towards"
|
|
bitfld.long 0x00 0. " RW ,Indicates if current Master initiated message is read operation or write operation" "Write,Read"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PMBTXBUF,PMBus Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from transmit data buffer"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMBRXBUF,PMBus Receive Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from receive data buffer"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMBACK,PMBus Acknowledge Register"
|
|
bitfld.long 0x00 20. " ACK ,Allows firmware to acknowledge or not acknowledge received data" "Not acknowledge,Acknowledge"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PMBST,PMBus Status Register"
|
|
bitfld.long 0x00 21. " SCL_RAW ,PMBus clock pin real time status" "Low,High"
|
|
bitfld.long 0x00 20. " SDA_RAW ,PMBus data pin real time status" "Low,High"
|
|
bitfld.long 0x00 15. " MASTER ,Master indicator" "Slave/Idle,Master"
|
|
bitfld.long 0x00 14. " LOST_ARB ,Lost arbitration flag" "Attained control,Lost control"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BUS_FREE ,PMBus free indicator" "Processing,Free"
|
|
bitfld.long 0x00 12. " UNIT_BUSY ,PMBus busy indicator" "Idle,Busy"
|
|
bitfld.long 0x00 11. " RPT_START ,Repeated start flag" "Not repeated,Repeated"
|
|
bitfld.long 0x00 10. " SLAVE_ADDR_READY ,Slave address ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_HIGH_DETECTED ,Clock high detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " CLK_LOW_TIMEOUT ,Clock low timeout status" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " PEC_VALID ,PEC valid indicator" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " NACK ,Not acknowledge flag status" "Accepted,Not accepted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOM ,End of message indicator" "In progress,Message end"
|
|
bitfld.long 0x00 4. " DATA_REQUEST ,Data request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " DATA_READY ,Data ready flag" "Not available,Available"
|
|
bitfld.long 0x00 0.--2. " RD_BYTE_COUNT ,Number of data bytes available in receive data register" "No data,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMBINTM,PMBus Interrupt Mask Register"
|
|
bitfld.long 0x00 9. " CLK_HIGH_TIMEOUT ,Clock high timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " LOST_ARB ,Lost arbitration interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " EOM ,End of message interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SLAVE_ADDR_READY ,Slave address ready interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA_REQUEST ,Data request interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DATA_READY ,Data ready interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " BUS_LOW_TIMEOUT ,Clock low timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " BUS_FREE ,Bus free interrupt mask" "Not masked,Masked"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMBCTRL2,PMBus Control Register 2"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
bitfld.long 0x00 30. " SLAVE_ADDR_2_EN ,Enable auto detection of the 2nd slave address" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 23.--29. 0x800000 " SLAVE_ADDR_2 ,Configures the second device address of the slave"
|
|
endif
|
|
bitfld.long 0x00 21.--22. " RX_BYTE_ACK_CNT ,Configures number of data bytes to automatically acknowledge when receiving data in slave mode" "1 byte,2 bytes,3 bytes,4 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MAN_CMD ,Manual command acknowledgement mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TX_PEC ,Asserted when the slave needs to send a PEC byte at end of message" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 16.--18. " TX_COUNT ,Number of valid bytes in transmit data register" "No bytes,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " PEC_ENA ,PEC processing enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SLAVE_MASK ,The slave mask enables acknowledgement of multiple device addresses by the slave"
|
|
bitfld.long 0x00 7. " MAN_SLAVE_ACK ,Manual Slave Address Acknowledgement Mode" "Automatic,Manual"
|
|
hexmask.long.byte 0x00 0.--6. 0x00 " SLAVE_ADDR , Configures the current device address of the slave"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PMBHSA,PMBus Hold Slave Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x01 " SLAVE_ADDR , Stored device address acknowledged by the slave"
|
|
bitfld.long 0x00 0. " SLAVE_RW , Stored R/W bit from address acknowledged by the slave" "Write,Read"
|
|
if (((d.l(ad:0xFFF7F700+0x20))&0x400000)==0x400000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
bitfld.long 0x00 24. " I2C_MODE_EN ,I2C mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
bitfld.long 0x00 4. " FAST_MODE_PLUS ,Fast mode plus enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
else
|
|
tree "PMB0"
|
|
base ad:0xFFF7F600
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMBCTRL1,PMBUS Control Register 1"
|
|
bitfld.long 0x00 20. " PRC_CALL ,Master process call message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " GRP_CMD ,Master group command message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PEC_ENA ,Master PEC processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EXT_CMD ,Master extended command code enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CMD_ENA ,Master command code enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE_COUNT ,Indicates number of data bytes transmitted in current message"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SLAVE_ADDR ,Specifies the address of the slave to which the current message is directed towards"
|
|
bitfld.long 0x00 0. " RW ,Indicates if current Master initiated message is read operation or write operation" "Write,Read"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PMBTXBUF,PMBus Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from transmit data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from transmit data buffer"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMBRXBUF,PMBus Receive Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Last data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Third data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Second data byte transmitted from receive data buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,First data byte transmitted from receive data buffer"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMBACK,PMBus Acknowledge Register"
|
|
bitfld.long 0x00 20. " ACK ,Allows firmware to acknowledge or not acknowledge received data" "Not acknowledge,Acknowledge"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PMBST,PMBus Status Register"
|
|
bitfld.long 0x00 21. " SCL_RAW ,PMBus clock pin real time status" "Low,High"
|
|
bitfld.long 0x00 20. " SDA_RAW ,PMBus data pin real time status" "Low,High"
|
|
bitfld.long 0x00 19. " CONTROL_RAW ,Control pin real time status" "Low,High"
|
|
bitfld.long 0x00 18. " ALERT_RAW ,Alert pin real time status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONTROL_EDGE ,Control edge detection status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 16. " ALERT_EDGE ,Alert edge detection status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 15. " MASTER ,Master indicator" "Slave/Idle,Master"
|
|
bitfld.long 0x00 14. " LOST_ARB ,Lost arbitration flag" "Attained control,Lost control"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BUS_FREE ,PMBus free indicator" "Processing,Free"
|
|
bitfld.long 0x00 12. " UNIT_BUSY ,PMBus busy indicator" "Idle,Busy"
|
|
bitfld.long 0x00 11. " RPT_START ,Repeated start flag" "Not repeated,Repeated"
|
|
bitfld.long 0x00 10. " SLAVE_ADDR_READY ,Slave address ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_HIGH_DETECTED ,Clock high detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " CLK_LOW_TIMEOUT ,Clock low timeout status" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " PEC_VALID ,PEC valid indicator" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " NACK ,Not acknowledge flag status" "Accepted,Not accepted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOM ,End of message indicator" "In progress,Message end"
|
|
bitfld.long 0x00 4. " DATA_REQUEST ,Data request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " DATA_READY ,Data ready flag" "Not available,Available"
|
|
bitfld.long 0x00 0.--2. " RD_BYTE_COUNT ,Number of data bytes available in receive data register" "No data,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMBINTM,PMBus Interrupt Mask Register"
|
|
bitfld.long 0x00 9. " CLK_HIGH_TIMEOUT ,Clock high timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " LOST_ARB ,Lost arbitration interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " CONTROL ,Control detection interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " ALERT ,Alert detection interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOM ,End of message interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SLAVE_ADDR_READY ,Slave address ready interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DATA_REQUEST ,Data request interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DATA_READY ,Data ready interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BUS_LOW_TIMEOUT ,Clock low timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " BUS_FREE ,Bus free interrupt mask" "Not masked,Masked"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMBCTRL2,PMBus Control Register 2"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
bitfld.long 0x00 30. " SLAVE_ADDR_2_EN ,Enable auto detection of the 2nd slave address" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 23.--29. 0x800000 " SLAVE_ADDR_2 ,Configures the second device address of the slave"
|
|
endif
|
|
bitfld.long 0x00 21.--22. " RX_BYTE_ACK_CNT ,Configures number of data bytes to automatically acknowledge when receiving data in slave mode" "1 byte,2 bytes,3 bytes,4 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MAN_CMD ,Manual command acknowledgement mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TX_PEC ,Asserted when the slave needs to send a PEC byte at end of message" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 16.--18. " TX_COUNT ,Number of valid bytes in transmit data register" "No bytes,1 byte,2 bytes,3 bytes,4 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " PEC_ENA ,PEC processing enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SLAVE_MASK ,The slave mask enables acknowledgement of multiple device addresses by the slave"
|
|
bitfld.long 0x00 7. " MAN_SLAVE_ACK ,Manual Slave Address Acknowledgement Mode" "Automatic,Manual"
|
|
hexmask.long.byte 0x00 0.--6. 0x00 " SLAVE_ADDR , Configures the current device address of the slave"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PMBHSA,PMBus Hold Slave Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x01 " SLAVE_ADDR , Stored device address acknowledged by the slave"
|
|
bitfld.long 0x00 0. " SLAVE_RW , Stored R/W bit from address acknowledged by the slave" "Write,Read"
|
|
if (((d.l(ad:0xFFF7F600+0x20))&0x400000)==0x400000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
bitfld.long 0x00 24. " I2C_MODE_EN ,I2C mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "No,Yes"
|
|
endif
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout disable" "No,Yes"
|
|
bitfld.long 0x00 19. " IBIAS_B_EN ,PMBus current source B control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IBIAS_A_EN ,PMBus current source A control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
bitfld.long 0x00 11. " CNTL_DIR ,Configures direction of Control pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 10. " CNTL_VALUE ,Configures output value of control pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 9. " CNTL_MODE ,Configures mode of control pin" "Functional,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALERT_DIR ,Configures direction of alert pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 7. " ALERT_VALUE ,Configures output value of alert pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 6. " ALERT_MODE ,Configures mode of alert pin" "Functional,GPIO"
|
|
bitfld.long 0x00 5. " CNTL_INT_EDGE ,Control Interrupt Edge Select" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FAST_MODE_PLUS ,Fast mode plus enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PMBCTRL3,PMBus Control Register 3"
|
|
bitfld.long 0x00 23. " CLK_HI_DIS ,Clock high timeout disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock low timeout Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBIAS_B_EN ,PMBus current source B control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IBIAS_A_EN ,PMBus current source A control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus clock pin" "Functional,GPIO"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus data pin" "Functional,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CNTL_DIR ,Configures direction of Control pin in GPIO mode" "Output,Input"
|
|
bitfld.long 0x00 10. " CNTL_VALUE ,Configures output value of control pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 9. " CNTL_MODE ,Configures mode of control pin" "Functional,GPIO"
|
|
bitfld.long 0x00 8. " ALERT_DIR ,Configures direction of alert pin in GPIO mode" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ALERT_VALUE ,Configures output value of alert pin in GPIO Mode" "Low,High"
|
|
bitfld.long 0x00 6. " ALERT_MODE ,Configures mode of alert pin" "Functional,GPIO"
|
|
bitfld.long 0x00 5. " CNTL_INT_EDGE ,Control Interrupt Edge Select" "Falling,Rising"
|
|
bitfld.long 0x00 4. " FAST_MODE_PLUS ,Fast mode plus enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock low timeout interrupt edge select" "Rising,Falling"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,PMBus interface synchronous reset" "No reset,Reset"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output Module)"
|
|
base ad:0xFFF7FA00
|
|
width 14.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FAULTDIR,Fault IO Direction Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.byte 0x00 7. " GIO_D_DIR ,GIO_D pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 6. " GIO_C_DIR ,GIO_C pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 5. " GIO_B_DIR ,GIO_B pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 4. " GIO_A_DIR ,GIO_A pin configuration" "Input,Output"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.byte 0x00 6. " TMS_DIR ,TMS pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 5. " TDI_DIR ,TDI pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 4. " TDO_DIR ,TDO pin configuration" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3. " FLT3_DIR ,FAULT[3] pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 2. " FLT2_DIR ,FAULT[2] pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 1. " FLT1_DIR ,FAULT[1] pin configuration" "Input,Output"
|
|
bitfld.byte 0x00 0. " FLT0_DIR ,FAULT[0] pin configuration" "Input,Output"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "FAULTIN,Fault Input Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.byte 0x00 7. " GIO_D_IN ,Input value of GIO_D pin" "Low,High"
|
|
bitfld.byte 0x00 6. " GIO_C_IN ,Input value of GIO_C pin" "Low,High"
|
|
bitfld.byte 0x00 5. " GIO_B_IN ,Input value of GIO_B pin" "Low,High"
|
|
bitfld.byte 0x00 4. " GIO_A_IN ,Input value of GIO_A pin" "Low,High"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.byte 0x00 6. " TMS_IN ,Input value of TMS pin" "Low,High"
|
|
bitfld.byte 0x00 5. " TDI_IN ,Input value of TDI pin" "Low,High"
|
|
bitfld.byte 0x00 4. " TDO_IN ,Input value of TDO pin" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3. " FLT3_IN ,Input value of FAULT[3] pin" "Low,High"
|
|
bitfld.byte 0x00 2. " FLT2_IN ,Input value of FAULT[2] pin" "Low,High"
|
|
bitfld.byte 0x00 1. " FLT1_IN ,Input value of FAULT[1] pin" "Low,High"
|
|
bitfld.byte 0x00 0. " FLT0_IN ,Input value of FAULT[0] pin" "Low,High"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FAULTOUT,Fault Output Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.byte 0x00 7. " GIO_D_OUT ,GIO_D pin output value" "Low,High"
|
|
bitfld.byte 0x00 6. " GIO_C_OUT ,GIO_C pin output value" "Low,High"
|
|
bitfld.byte 0x00 5. " GIO_B_OUT ,GIO_B pin output value" "Low,High"
|
|
bitfld.byte 0x00 4. " GIO_A_OUT ,GIO_A pin output value" "Low,High"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.byte 0x00 6. " TMS_OUT ,TMS pin output value" "Low,High"
|
|
bitfld.byte 0x00 5. " TDI_OUT ,TDI pin output value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3. " FLT3_OUT ,FAULT[3] pin output value" "Low,High"
|
|
bitfld.byte 0x00 2. " FLT2_OUT ,FAULT[2] pin output value" "Low,High"
|
|
bitfld.byte 0x00 1. " FLT1_OUT ,FAULT[1] pin output value" "Low,High"
|
|
bitfld.byte 0x00 0. " FLT0_OUT ,FAULT[0] pin output value" "Low,High"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FAULTINTENA,Fault Interrupt Enable Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.byte 0x00 7. " GIO_D_INT_EN ,GIO_D interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " GIO_C_INT_EN ,GIO_C interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " GIO_B_INT_EN ,GIO_B interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " GIO_A_INT_EN ,GIO_A interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.byte 0x00 6. " TMS_INT_EN ,TMS interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TDI_INT_EN ,TDI interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TDO_INT_EN ,TDO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3. " FLT3_INT_EN ,FAULT[3] interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FLT2_INT_EN ,FAULT[2] interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " FLT1_INT_EN ,FAULT[1] interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FLT0_INT_EN ,FAULT[0] interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FAULTINTPOL,Fault Interrupt Polarity Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
bitfld.byte 0x00 7. " GIO_D_INT_POL ,GIO_D interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 6. " GIO_C_INT_POL ,GIO_C interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 5. " GIO_B_INT_POL ,GIO_B interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 4. " GIO_A_INT_POL ,GIO_A interrupt polarity select" "Falling,Rising"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
bitfld.byte 0x00 6. " TMS_INT_POL ,TMS interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 5. " TDI_INT_POL ,TDI interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 4. " TDO_INT_POL ,TDO interrupt polarity select" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3. " FLT3_INT_POL ,FAULT[3] interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 2. " FLT2_INT_POL ,FAULT[2] interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 1. " FLT1_INT_POL ,FAULT[1] interrupt polarity select" "Falling,Rising"
|
|
bitfld.byte 0x00 0. " FLT0_INT_POL ,FAULT[0] interrupt polarity select" "Falling,Rising"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "FAULTINTPEND,Fault Interrupt Pending Register"
|
|
sif (cpuis("UCD3138A64")||cpuis("UCD3138128"))
|
|
eventfld.byte 0x00 7. " GIO_D_INT_PEND ,GIO_D has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " GIO_C_INT_PEND ,GIO_C has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " GIO_B_INT_PEND ,GIO_B has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " GIO_A_INT_PEND ,GIO_A has caused an interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("UCD3138A")||cpuis("UCD3138R*"))
|
|
eventfld.byte 0x00 6. " TMS_INT_PEND ,TMS has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " TDI_INT_PEND ,TDI has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " TDO_INT_PEND ,TDO has caused an interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.byte 0x00 3. " FLT3_INT_PEND ,FAULT[3] has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " FLT2_INT_PEND ,FAULT[2] has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " FLT1_INT_PEND ,FAULT[1] has caused an interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " FLT0_INT_PEND ,FAULT[0] has caused an interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "EXTINTDIR,External Interrupt Direction Register"
|
|
bitfld.byte 0x00 0. " EXT_INT_DIR ,EXT-INT pin configuration" "Input,Output"
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "EXTINTIN,External Interrupt Input Register"
|
|
bitfld.byte 0x00 0. " EXT_INT_IN ,Input value of EXT-INT pin" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "EXTINTOUT,External Interrupt Output Register"
|
|
bitfld.byte 0x00 0. " EXT_INT_OUT ,EXT-INT pin output value" "Low,High"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "EXTINTENA,External Interrupt Enable Register"
|
|
bitfld.byte 0x00 0. " EXT_INT_EN ,EXT-INT interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "EXTTINTPOL,External Interrupt Polarity Register"
|
|
bitfld.byte 0x00 0. " EXT_INT_POL ,EXT-INT interrupt polarity select" "Falling,Rising"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "EXTINTPEND,External Interrupt Pending Register"
|
|
eventfld.byte 0x00 0. " EXT_INT_PEND ,EXT-INT has caused an interrupt" "No interrupt,Interrupt"
|
|
width 0x0b
|
|
tree.end
|
|
tree "TIMER Module"
|
|
base ad:0xFFF7FD00
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "T24CNTDAT, 24-bit Counter Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CNT_DAT , Contains the 24-bit counter value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "T24CNTCTRL, 24-bit Counter Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE , Defines the prescaler value used to select the 24-bit counter resolution"
|
|
bitfld.long 0x00 2. " EXT_CLK_SEL ,External clock select" "ICLK,External"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OV_INT_ENA ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " OV_FLAG ,Indicates a counter overflow" "No overflow,Overflow"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "T24CAPDAT0, 24-bit Capture Channel Data Register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CAP_DAT , Contains the 24-bit input capture value"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "T24CAPDAT1, 24-bit Capture Channel Data Register 1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CAP_DAT , Contains the 24-bit input capture value"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "T24CAPCTRL0, 24-bit Capture Channel Control Register 0"
|
|
bitfld.long 0x00 4.--5. " CAP_SEL , Capture pin select" "TCAP-A,SCI_RX[0],SCI_RX[1],SYNC"
|
|
bitfld.long 0x00 2.--3. " EDGE , Input capture edge select" "No capture,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAP_INT_ENA ,Input Capture Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP_INT_FLAG ,Flag which indicates a valid input capture event" "No valid,Valid"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "T24CAPCTRL1, 24-bit Capture Channel Control Register 1"
|
|
bitfld.long 0x00 4.--5. " CAP_SEL , Capture pin select" "TCAP-A,SCI_RX[0],SCI_RX[1],SYNC"
|
|
bitfld.long 0x00 2.--3. " EDGE , Input capture edge select" "No capture,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAP_INT_ENA ,Input capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP_INT_FLAG ,Flag which indicates a valid input capture event" "No valid,Valid"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "T24CAPIO, 24-bit Capture I/O Control and Data Register"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
rbitfld.long 0x00 5. " TCAP_1_IN , Input data for pin TCAP_1/TDI/TDO pin, when connected to chip I/O" "Low,High"
|
|
bitfld.long 0x00 4. " TCAP_1_OUT , Output data for pin TCAP_1 pin, when connected to chip I/O" "Low,High"
|
|
bitfld.long 0x00 3. " TCAP_1_DIR ,Controls data direction for pin TCAP, when connected to chip I/O" "Input,Output"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 2. " TCAP_0_IN ,Input data for pin TCAP_0/TDI/TDO pin, when connected to chip I/O" "Low,High"
|
|
bitfld.long 0x00 1. " TCAP_0_OUT ,Output data for pin TCAP_0 pin, when connected to chip I/O" "Low,High"
|
|
bitfld.long 0x00 0. " TCAP_0_DIR ,Controls data direction for pin TCAP_0, when connected to chip I/O" "Input,Output"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "T24CMPDAT0, 24-bit Output Compare Channel 0 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CMP_DAT , Contains the 24-bit output comparison value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "T24CMPDAT1, 24-bit Output Compare Channel 1 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CMP_DAT , Contains the 24-bit output comparison value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TT24CMPCTRL0, 24-bit Output Compare Channel 0 Control Register"
|
|
bitfld.long 0x00 1. " CMP_INT_ENA , Output compare channel interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP_INT_FLAG , Indicates a valid output compare event" "Not occurred,Occurred"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TT24CMPCTRL1, 24-bit Output Compare Channel 1 Control Register"
|
|
bitfld.long 0x00 1. " CMP_INT_ENA , Output compare channel interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP_INT_FLAG , Indicates a valid output compare event" "Not occurred,Occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "T16PWM0CNTDAT, PWM0 Counter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT_DAT , Contains the 16-bit counter value"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "T16PWM1CNTDAT, PWM1 Counter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT_DAT , Contains the 16-bit counter value"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "T16PWM2CNTDAT, PWM2 Counter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT_DAT , Contains the 16-bit counter value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "T16PWM3CNTDAT, PWM3 Counter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT_DAT , Contains the 16-bit counter value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "T16PWM0CNTCTRL, PWM0 Counter Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE , Defines the prescaler value to select the PWM counter resolution"
|
|
bitfld.long 0x00 5.--6. " SYNC_SEL , Configures master PWM counter" "PWM0,PWM1,PWM2,PWM3"
|
|
bitfld.long 0x00 4. " SYNC_EN , PWM counter starts when master PWM counter is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SW_RESET , PWM counter reset by software" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP_RESET_ENA , Enables PWM counter reset by compare action of T16CMP0DR" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OV_INT_ENA , PWM counter overflow interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " OV_INT_FLAG , Flag which indicates a PWM counter overflow" "No overflow,Overflow"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "T16PWM1CNTCTRL, PWM1 Counter Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE , Defines the prescaler value to select the PWM counter resolution"
|
|
bitfld.long 0x00 5.--6. " SYNC_SEL , Configures master PWM counter" "PWM0,PWM1,PWM2,PWM3"
|
|
bitfld.long 0x00 4. " SYNC_EN , PWM counter starts when master PWM counter is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SW_RESET , PWM counter reset by software" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP_RESET_ENA , Enables PWM counter reset by compare action of T16CMP1DR" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OV_INT_ENA , PWM Counter Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " OV_INT_FLAG , Flag which indicates a PWM counter overflow" "No overflow,Overflow"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "T16PWM2CNTCTRL, PWM2 Counter Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE , Defines the prescaler value to select the PWM counter resolution"
|
|
bitfld.long 0x00 5.--6. " SYNC_SEL , Configures master PWM counter" "PWM0,PWM1,PWM2,PWM3"
|
|
bitfld.long 0x00 4. " SYNC_EN , PWM counter starts when master PWM counter is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SW_RESET , PWM counter reset by software" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP_RESET_ENA , Enables PWM counter reset by compare action of T16CMP2DR" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OV_INT_ENA , PWM counter overflow interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " OV_INT_FLAG , Flag which indicates a PWM counter overflow" "No overflow,Overflow"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "T16PWM3CNTCTRL, PWM3 Counter Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE , Defines the prescaler value to select the PWM counter resolution"
|
|
bitfld.long 0x00 5.--6. " SYNC_SEL , Configures master PWM counter" "PWM0,PWM1,PWM2,PWM3"
|
|
bitfld.long 0x00 4. " SYNC_EN , PWM counter starts when master PWM counter is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SW_RESET , PWM counter reset by software" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP_RESET_ENA , Enables PWM counter reset by compare action of T16CMP3DR" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OV_INT_ENA , PWM counter overflow interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " OV_INT_FLAG , Flag which indicates a PWM counter overflow" "No overflow,Overflow"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "T16PWM0CMP0DAT, 16-bit PWM0 Compare Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
line.long 0x04 "T16PWM0CMP1DAT, 16-bit PWM0 Compare Channel 1 Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "T16PWM1CMP0DAT, 16-bit PWM1 Compare Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
line.long 0x04 "T16PWM1CMP1DAT, 16-bit PWM1 Compare Channel 1 Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "T16PWM2CMP0DAT, 16-bit PWM2 Compare Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
line.long 0x04 "T16PWM2CMP1DAT, 16-bit PWM2 Compare Channel 1 Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "T16PWM3CMP0DAT, 16-bit PWM3 Compare Channel 0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
line.long 0x04 "T16PWM3CMP1DAT, 16-bit PWM3 Compare Channel 1 Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMP_DAT , Contains the 16-bit compare value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "T16PWM0CMPCTRL, 16-bit PWM0 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
rbitfld.long 0x00 11. " PWM_IN ,Input value of PWM pin when configured in PWM mode" "Low,High"
|
|
bitfld.long 0x00 10. " PWM_OUT ,Data to be written into the output latch when PWM_OUT_DRV is high" "Cleared,Set"
|
|
bitfld.long 0x00 9. " PWM_OUT_ENA ,FAN-PWM pin configuration" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PWM_OUT_DRV ,Causes the value of the bit PWM_OUT to be written into the output latch" "Not affected,Affected"
|
|
bitfld.long 0x00 6.--7. " PWM_OUT_ACTION1 ,These 2 bits select the output action when a compare equal is detected on T16CMP1DAT" "No action,Set,Clear,Toggle"
|
|
bitfld.long 0x00 4.--5. " PWM_OUT_ACTION0 ,Selects the output action when a compare equal is detected on T16CMP0DAT" "No action,Set,Clear,Toggle"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "T16PWM1CMPCTRL, 16-bit PWM1 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
rbitfld.long 0x00 11. " PWM_IN ,Input value of PWM pin when configured in PWM mode" "Low,High"
|
|
bitfld.long 0x00 10. " PWM_OUT ,Data to be written into the output latch when PWM_OUT_DRV is high" "Cleared,Set"
|
|
bitfld.long 0x00 9. " PWM_OUT_ENA ,FAN-PWM pin configuration" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PWM_OUT_DRV ,Causes the value of the bit PWM_OUT to be written into the output latch" "Not affected,Affected"
|
|
bitfld.long 0x00 6.--7. " PWM_OUT_ACTION1 ,These 2 bits select the output action when a compare equal is detected on T16CMP1DAT" "No action,Set,Clear,Toggle"
|
|
bitfld.long 0x00 4.--5. " PWM_OUT_ACTION0 ,Selects the output action when a compare equal is detected on T16CMP1DAT" "No action,Set,Clear,Toggle"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "T16PWM2CMPCTRL, 16-bit PWM2 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
rbitfld.long 0x00 11. " PWM_IN ,Input value of PWM pin when configured in PWM mode" "Low,High"
|
|
bitfld.long 0x00 10. " PWM_OUT ,Data to be written into the output latch when PWM_OUT_DRV is high" "Cleared,Set"
|
|
bitfld.long 0x00 9. " PWM_OUT_ENA ,FAN-PWM pin configuration" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PWM_OUT_DRV ,Causes the value of the bit PWM_OUT to be written into the output latch" "Not affected,Affected"
|
|
bitfld.long 0x00 6.--7. " PWM_OUT_ACTION1 ,These 2 bits select the output action when a compare equal is detected on T16CMP1DAT" "No action,Set,Clear,Toggle"
|
|
bitfld.long 0x00 4.--5. " PWM_OUT_ACTION0 ,Selects the output action when a compare equal is detected on T16CMP2DAT" "No action,Set,Clear,Toggle"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "T16PWM3CMPCTRL, 16-bit PWM3 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
rbitfld.long 0x00 11. " PWM_IN ,Input value of PWM pin when configured in PWM mode" "Low,High"
|
|
bitfld.long 0x00 10. " PWM_OUT ,Data to be written into the output latch when PWM_OUT_DRV is high" "Cleared,Set"
|
|
bitfld.long 0x00 9. " PWM_OUT_ENA ,FAN-PWM pin configuration" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PWM_OUT_DRV ,Causes the value of the bit PWM_OUT to be written into the output latch" "Not affected,Affected"
|
|
bitfld.long 0x00 6.--7. " PWM_OUT_ACTION1 ,These 2 bits select the output action when a compare equal is detected on T16CMP1DAT" "No action,Set,Clear,Toggle"
|
|
bitfld.long 0x00 4.--5. " PWM_OUT_ACTION0 ,Selects the output action when a compare equal is detected on T16CMP3DAT" "No action,Set,Clear,Toggle"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "T16PWM2CMPCTRL, 16-bit PWM2 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "T16PWM3CMPCTRL, 16-bit PWM3 Compare Control Register"
|
|
bitfld.long 0x00 12. " SHADOW ,Controls the update of the 16-bit output compare Registers" "Immediately,Through buffers"
|
|
eventfld.long 0x00 3. " CMP1_INT_ENA ,Compare 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP1_INT_FLAG ,Flag which indicates a valid output compare 1 event" "No compare,Compare"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP0_INT_ENA ,Compare 0 interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CMP0_INT_FLAG ,Flag which indicates a valid output compare 0 event" "No compare,Compare"
|
|
endif
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "WDST, Watchdog Status"
|
|
in
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "WDCTRL, Watchdog Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " WD_PERIOD , Configures the time for the watchdog reset"
|
|
bitfld.long 0x00 6. " PROTECT ,Watchdog protect bit" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPU_RESET_EN ,Enables Watchdog reset event to reset the CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WDRST_INT_EN ,Watchdog reset event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WKEN_INT_EN ,Watchdog wake event interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WKEV_EN ,Watchdog wake event comparator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WDRST_EN ,Watchdog reset event comparator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNT_RESET ,This bit resets the watchdog counters" "Enabled,Reset"
|
|
width 0x0b
|
|
tree.end
|
|
tree "MMC (Memory Controller)"
|
|
base ad:0xFFFFFD00
|
|
width 10.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMCTRL,Static Memory Control Register"
|
|
bitfld.word 0x00 12.--13. " LEAD , Address setup time cycles (write operations)" "No setup time,1 cycle,2cycles,3 cycles"
|
|
bitfld.word 0x00 9.--11. " TRAIL , Number of trailing wait states" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 4.--7. " ACTIVE , Active Wait states (both read/write operations)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " ENDIAN , Endian mode Identification" "Big endian,Little endian"
|
|
bitfld.word 0x00 0.--1. " WIDTH , Data width for memories" "8 bits,16 bits,32 bits,"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "WCTRL,Write Control Register"
|
|
bitfld.word 0x00 1. " TRAIL_OVR , Write trailing wait state override" "No override,Override"
|
|
bitfld.word 0x00 0. " WBUF_ENA , Write buffer enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "PCTRL,Peripheral Control Register"
|
|
bitfld.word 0x00 1. " PBUF_ENA , Write buffer enable" "Disabled,Enabled"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PLOC,Peripheral Location Register"
|
|
bitfld.word 0x00 15. " LOC[15] ,Peripheral location bit 15" "Internal,External"
|
|
bitfld.word 0x00 14. " [14] ,Peripheral location bit 14" "Internal,External"
|
|
bitfld.word 0x00 13. " [13] ,Peripheral location bit 13" "Internal,External"
|
|
bitfld.word 0x00 12. " [12] ,Peripheral location bit 12" "Internal,External"
|
|
textline " "
|
|
bitfld.word 0x00 11. " [11] ,Peripheral location bit 11" "Internal,External"
|
|
bitfld.word 0x00 10. " [10] ,Peripheral location bit 10" "Internal,External"
|
|
bitfld.word 0x00 9. " [9] ,Peripheral location bit 9" "Internal,External"
|
|
bitfld.word 0x00 8. " [8] ,Peripheral location bit 8" "Internal,External"
|
|
textline " "
|
|
bitfld.word 0x00 7. " [7] ,Peripheral location bit 7" "Internal,External"
|
|
bitfld.word 0x00 6. " [6] ,Peripheral location bit 6" "Internal,External"
|
|
bitfld.word 0x00 5. " [5] ,Peripheral location bit 5" "Internal,External"
|
|
bitfld.word 0x00 4. " [4] ,Peripheral location bit 4" "Internal,External"
|
|
textline " "
|
|
bitfld.word 0x00 3. " [3] ,Peripheral location bit 3" "Internal,External"
|
|
bitfld.word 0x00 2. " [2] ,Peripheral location bit 2" "Internal,External"
|
|
bitfld.word 0x00 1. " [1] ,Peripheral location bit 1" "Internal,External"
|
|
bitfld.word 0x00 0. " [0] ,Peripheral location bit 0" "Internal,External"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "PPROT,Peripheral Protection Register"
|
|
bitfld.word 0x00 15. " PROT[15] ,Peripheral protection bit 15" "All modes,Privilege mode"
|
|
bitfld.word 0x00 14. " [14] ,Peripheral protection bit 14" "All modes,Privilege mode"
|
|
bitfld.word 0x00 13. " [13] ,Peripheral protection bit 13" "All modes,Privilege mode"
|
|
bitfld.word 0x00 12. " [12] ,Peripheral protection bit 12" "All modes,Privilege mode"
|
|
textline " "
|
|
bitfld.word 0x00 11. " [11] ,Peripheral protection bit 11" "All modes,Privilege mode"
|
|
bitfld.word 0x00 10. " [10] ,Peripheral protection bit 10" "All modes,Privilege mode"
|
|
bitfld.word 0x00 9. " [9] ,Peripheral protection bit 9" "All modes,Privilege mode"
|
|
bitfld.word 0x00 8. " [8] ,Peripheral protection bit 8" "All modes,Privilege mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " [7] ,Peripheral protection bit 7" "All modes,Privilege mode"
|
|
bitfld.word 0x00 6. " [6] ,Peripheral protection bit 6" "All modes,Privilege mode"
|
|
bitfld.word 0x00 5. " [5] ,Peripheral protection bit 5" "All modes,Privilege mode"
|
|
bitfld.word 0x00 4. " [4] ,Peripheral protection bit 4" "All modes,Privilege mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " [3] ,Peripheral protection bit 3" "All modes,Privilege mode"
|
|
bitfld.word 0x00 2. " [2] ,Peripheral protection bit 2" "All modes,Privilege mode"
|
|
bitfld.word 0x00 1. " [1] ,Peripheral protection bit 1" "All modes,Privilege mode"
|
|
bitfld.word 0x00 0. " [0] ,Peripheral protection bit 0" "All modes,Privilege mode"
|
|
width 0x0b
|
|
tree.end
|
|
tree "DEC (Address Manager)"
|
|
base ad:0xFFFFFE00
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MFBAHR0, Memory Fine Base Address High Register 0 Boot ROM (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MFBALR0, Memory Fine Base Address Low Register 0 Boot ROM (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 8. " MS ,Memory map select" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MFBAHR1, Memory Fine Base Address High Register 1 Program Flash 0(8Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MFBALR1, Memory Fine Base Address Low Register 1 Program Flash 0(8Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MFBAHR2, Memory Fine Base Address High Register 2 Data Flash (512x32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MFBALR2, Memory Fine Base Address Low Register 2 Data Flash (512x32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MFBAHR3, Memory Fine Base Address High Register 3 Data RAM (2Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MFBALR3, Memory Fine Base Address Low Register 3 Data RAM (2Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MFBAHR4, Memory Fine Base Address High Register 4 Loop Mux (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MFBALR4, Memory Fine Base Address Low Register 4 Loop Mux (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MFBAHR5, Memory Fine Base Address High Register 5 Fault Mux (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MFBALR5, Memory Fine Base Address Low Register 5 Fault Mux (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MFBAHR6, Memory Fine Base Address High Register 6 ADC12 Control (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MFBALR6, Memory Fine Base Address Low Register 6 ADC12 Control (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MFBAHR7, Memory Fine Base Address High Register 7 DPWM3 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MFBALR7, Memory Fine Base Address Low Register 7 DPWM3 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MFBAHR8, Memory Fine Base Address High Register 8 Filter 2 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MFBALR8, Memory Fine Base Address Low Register 8 Filter 2 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MFBAHR9, Memory Fine Base Address High Register 9 DPWM 2 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MFBALR9, Memory Fine Base Address Low Register 9 DPWM 2 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MFBAHR10, Memory Fine Base Address High Register 10 Front End Control 2 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MFBALR10, Memory Fine Base Address Low Register 10 Front End Control 2 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFBAHR11, Memory Fine Base Address High Register 11 Filter 1 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MFBALR11, Memory Fine Base Address Low Register 11 Filter 1 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MFBAHR12, Memory Fine Base Address High Register 12 DPWM 1 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MFBALR12, Memory Fine Base Address Low Register 12 DPWM 1 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "MFBAHR13, Memory Fine Base Address High Register 13 Front End Control 1 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MFBALR13, Memory Fine Base Address Low Register 13 Front End Control 1 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MFBAHR14, Memory Fine Base Address High Register 14 Filter 0 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "MFBALR14, Memory Fine Base Address Low Register 14 Filter 0 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "MFBAHR15, Memory Fine Base Address High Register 15 DPWM 0 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "MFBALR15, Memory Fine Base Address Low Register 15 DPWM 0 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MFBAHR16, Memory Fine Base Address High Register 16 Front End Control 0 (1Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "MFBALR16, Memory Fine Base Address Low Register 16 Front End Control 0 (1Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MFBAHR17, Memory Fine Base Address High Register 17 Program Flash 1(8Kx32)"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MFBALR17, Memory Fine Base Address Low Register 17 Program Flash 1(8Kx32)"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
sif cpuis("UCD3138128")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MFBAHR18, Memory Fine Base Address High Register 18"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "MFBALR18, Memory Fine Base Address Low Register 18"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MFBAHR19, Memory Fine Base Address High Register 19"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " ADDRESS[31:16] ,16 most significant bits of the base address"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "MFBALR19, Memory Fine Base Address Low Register 19"
|
|
hexmask.long.byte 0x00 10.--15. 0x04 " ADDRESS[15:10] ,6 least significant bits of the base address"
|
|
bitfld.long 0x00 9. " AW ,Auto-wait-on-write" "No cycle,Additional cycle"
|
|
bitfld.long 0x00 4.--7. " BLOCK_SIZE ,Configures the size of the memory" "Disabled,1K bytes,2K bytes,4K bytes,8K bytes,16K bytes,32K bytes,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RONLY ,Read-only protection" "Read/Write,Read"
|
|
bitfld.long 0x00 0. " PRIV ,Privilege mode protection" "User/privilege,Privilege"
|
|
endif
|
|
sif !cpuis("UCD3138A64")||!cpuis("UCD3138128")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PFLASHCTRL, Program Flash Control Register "
|
|
rbitfld.long 0x00 11. " BUSY , Program flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Program flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Program flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PFLASHCTRL_0, Program Flash Control Register 0"
|
|
rbitfld.long 0x00 11. " BUSY , Program flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Program flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Program flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("UCD3138A64")||cpuis("UCD3138128")
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PFLASHCTRL_1, Program Flash Control Register 1"
|
|
rbitfld.long 0x00 11. " BUSY , Program flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Program flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Program flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("UCD3138128")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PFLASHCTRL_2, Program Flash Control Register 2"
|
|
rbitfld.long 0x00 11. " BUSY , Program flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Program flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Program flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PFLASHCTRL_3, Program Flash Control Register 3"
|
|
rbitfld.long 0x00 11. " BUSY , Program flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Program flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Program flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DFLASHCTRL, Data Flash Control Register"
|
|
rbitfld.long 0x00 11. " BUSY , Data flash busy indicator" "Available,Unavailable"
|
|
bitfld.long 0x00 9. " PAGE_ERASE , Data flash page erase enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MASS_ERASE , Data flash mass erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " PAGE_SEL , Selects page to be erased during page erase cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FLASHILOCK, Flash Interlock Register"
|
|
width 0x0b
|
|
tree.end
|
|
tree "CIM (Central Interrupt Module)"
|
|
base ad:0xFFFFFF20
|
|
width 9.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "IRQIVEC, IRQ Index Offset Vector Register"
|
|
in
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "FIQIVEC, FIQ Index Offset Vector Register"
|
|
in
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FIRQPR, FIQ/IRQ Program Control Register"
|
|
bitfld.long 0x00 31. " FIRQPR[31] ,Interrupt request from a peripheral 31" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt request from a peripheral 30" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt request from a peripheral 29" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " [28] ,Interrupt request from a peripheral 28" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Interrupt request from a peripheral 27" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " [26] ,Interrupt request from a peripheral 26" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " [25] ,Interrupt request from a peripheral 25" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " [24] ,Interrupt request from a peripheral 24" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Interrupt request from a peripheral 23" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request from a peripheral 22" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request from a peripheral 21" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request from a peripheral 20" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request from a peripheral 19" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request from a peripheral 18" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request from a peripheral 17" "IRQ,FIQ"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request from a peripheral 16" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request from a peripheral 15" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request from a peripheral 14" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request from a peripheral 13" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request from a peripheral 12" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request from a peripheral 11" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request from a peripheral 10" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request from a peripheral 9" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request from a peripheral 8" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request from a peripheral 7" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request from a peripheral 6" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request from a peripheral 5" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request from a peripheral 4" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request from a peripheral 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request from a peripheral 2" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request from a peripheral 1" "IRQ,FIQ"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request from a peripheral 0" "IRQ,FIQ"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INTREQ, Pending Interrupt Read Location Register"
|
|
bitfld.long 0x00 31. " INTREQ[31] ,Interrupt request 31 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt request 30 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt request 29 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,Interrupt request 28 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Pending interrupt requests 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,Pending interrupt requests 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,Pending interrupt requests 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,Pending interrupt requests 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Interrupt request 23 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request 22 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request 21 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request 20 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request 19 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request 18 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request 17 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request 16 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request 15 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request 14 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request 13 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request 12 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request 11 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request 10 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request 9 pending status" "No interrupt,interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request 8 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request 7 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request 6 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request 5 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request 4 pending status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request 3 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request 2 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request 1 pending status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request 0 pending status" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "REQMASK, Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " REQMASK[31] ,Interrupt request mask select 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt request mask select 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt request mask select 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Interrupt request mask select 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Interrupt request mask select 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Interrupt request mask select 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Interrupt request mask select 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Interrupt request mask select 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Interrupt request mask select 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request mask select 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request mask select 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request mask select 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request mask select 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request mask select 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request mask select 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request mask select 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request mask select 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request mask select 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request mask select 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request mask select 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request mask select 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request mask select 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request mask select 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request mask select 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request mask select 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request mask select 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request mask select 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request mask select 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request mask select 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request mask select 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request mask select 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request mask select 0" "Disabled,Enabled"
|
|
width 0x0b
|
|
tree.end
|
|
tree "SYS (System Module)"
|
|
base ad:0xFFFFFFD0
|
|
width 9.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CLKCNTL, Clock Control Register"
|
|
bitfld.word 0x00 8.--9. " M_DIV_RATIO ,MCLK (processor clock) divide ratio" "/8,/16,/32,/64"
|
|
bitfld.word 0x00 5.--6. " CLKSR ,Source/function of CLKOUT" "CLKDOUT,ICLK,MCLK,SYSCLK"
|
|
bitfld.word 0x00 3. " CLKDOUT ,Output value of CLKOUT" "Low,High"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SYSECR, System Exception Control Register"
|
|
bitfld.word 0x00 14.--15. " RESET ,Software reset enable" "Reset,No reset,Reset,Reset"
|
|
bitfld.word 0x00 2. " PACCOVR ,Peripheral access violation override" "Reset enabled,Reset disabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ACCOVR ,Memory access reset override" "Reset enabled,Reset disabled"
|
|
bitfld.word 0x00 0. " ILLOVR ,Illegal Address reset override" "Reset enabled,Reset disabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "ABRTESR, Abort Exception Status Register"
|
|
bitfld.word 0x00 15. " PORRST ,Power-On reset flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CLKRST ,Clock fail flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " WDRST ,Watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 12. " ILLMODE ,Illegal mode flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " ILLADR ,Illegal address access flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " ILLACC ,Illegal memory access flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PILLACC ,Peripheral illegal access flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " ILLMAP ,Illegal address map flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " SWRST ,Software reset flag" "Not occurred,Occurred"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SYSESR, System Exception Status Register"
|
|
bitfld.word 0x00 15. " ADRABT ,Illegal address abort" "Not detected,Detected"
|
|
bitfld.word 0x00 14. " MEMABT ,Memory access abort" "Not detected,Detected"
|
|
bitfld.word 0x00 13. " PACCVIO ,Peripheral access violation error" "Not detected,Detected"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "GLBSTAT, Global Status Register"
|
|
bitfld.word 0x00 7. " SYSADDR ,System illegal address flag" "Not detected,Detected"
|
|
bitfld.word 0x00 6. " SYSACC ,System illegal access flag" "Not detected,Detected"
|
|
bitfld.word 0x00 5. " MPUADDR ,MPU illegal address flag" "Not detected,Detected"
|
|
bitfld.word 0x00 4. " MPUACC ,MPU illegal access flag" "Not detected,Detected"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "DEV, Device Identification Register"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SSIF, System Software Interrupt Flag Register"
|
|
bitfld.word 0x00 0. " SSIFLAG ,System software interrupt flag" "No IRQ/FIQ,IRQ/FIQ"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "SSIR, System Software Interrupt Request Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " SSKEY ,Software interrupt request key"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SSDATA ,System software interrupt data"
|
|
width 0x0b
|
|
tree.end
|
|
textline ""
|
|
width 0x0B
|