46936 lines
3.3 MiB
46936 lines
3.3 MiB
; --------------------------------------------------------------------------------
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; @Title: TMS570LS21xx On-Chip Peripherals
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; @Props: Released
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; @Author: CIN
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; @Changelog: 2011-07-11 CIN
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; @Manufacturer: TI - Texas Instruments
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; @Doc: SPNS166.pdf; SPNS160A.pdf; SPNS160B.pdf; modules; xml
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; @Core: Cortex-R4F
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertms570ls21xx.per 14459 2022-03-07 08:08:57Z kwisniewski $
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;known problems - VFP is not implemented because of missing register offsets
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config 16. 8.
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tree "Core Registers (Cortex-R4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUIR,MPU type register"
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hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
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bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
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bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
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bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
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bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
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bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
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bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
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textline " "
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bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
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bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
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bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable"
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bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable"
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bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
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textline " "
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bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
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bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
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bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
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textline " "
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bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
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bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable"
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bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
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textline " "
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bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable"
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bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
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bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
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textline " "
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bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
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bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled"
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bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
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textline " "
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bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable"
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bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable"
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bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
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bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable"
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textline " "
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group c15:0x0f--0x0f
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line.long 0x0 "SACTLR,Secondary Auxiliary Control Register"
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bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
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bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
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bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
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textline " "
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bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
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bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
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bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
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textline " "
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bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
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bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
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bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
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textline " "
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bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
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bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x201--0x201
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x0b--0x0b
|
|
line.long 0x00 "SPC,Slave Port Control"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group c15:0x0001--0x0001
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
rgroup.long c15:0x0ef++0x0
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
tree.end
|
|
width 8.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMNC,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMNXSEL,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "CCNT,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "ESR,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Count Register"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "USEREN,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "ITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "ECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "OSLAR,Operating System Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "OSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "OSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x46++0x00
|
|
line.long 0x00 "BVR6,Breakpoint Value Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group c14:0x56++0x00
|
|
line.long 0x00 "BCR6,Breakpoint Control Register 6"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x47++0x00
|
|
line.long 0x00 "BVR7,Breakpoint Value Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group c14:0x57++0x00
|
|
line.long 0x00 "BCR7,Breakpoint Control Register 7"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x64++0x00
|
|
line.long 0x00 "WVR4,Watchpoint Value Register 4"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4"
|
|
group c14:0x74--0x74
|
|
line.long 0x0 "WCR4,Watchpoint Control Register 4"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x65++0x00
|
|
line.long 0x00 "WVR5,Watchpoint Value Register 5"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5"
|
|
group c14:0x75--0x75
|
|
line.long 0x0 "WCR5,Watchpoint Control Register 5"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x66++0x00
|
|
line.long 0x00 "WVR6,Watchpoint Value Register 6"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6"
|
|
group c14:0x76--0x76
|
|
line.long 0x0 "WCR6,Watchpoint Control Register 6"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x67++0x00
|
|
line.long 0x00 "WVR7,Watchpoint Value Register 7"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7"
|
|
group c14:0x77--0x77
|
|
line.long 0x0 "WCR7,Watchpoint Control Register 7"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif cpuis("TMS570LS21*")
|
|
endian.be
|
|
endif
|
|
; tree "VFP"
|
|
; base ad:0xFFF7C000
|
|
; %include tms570ls21xx/vfp.ph
|
|
; tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
tree "MIBADC1"
|
|
base ad:0xFFF7C000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADRSTCR,ADC Reset Control Register"
|
|
bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADOPMODECR,ADC Operating Mode Control Register"
|
|
bitfld.long 0x00 31. " 10/12BIT ,Resolution of the ADC core select" "10-bit,12-bit"
|
|
bitfld.long 0x00 24. " COS ,ADCLK halt/continue when the emulation system enters suspend mode" "Halted,Continue"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " CHNTESTEN ,Enable the input channels impedance measurement mode" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16. " RAMTESTEN ,Enable the ADC results RAM test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,ADC core power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 4. " IDLEPWRDN ,ADC power down when idle" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADCEN ,ADC conversions enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLOCKCR,Clock Prescaler"
|
|
bitfld.long 0x00 0.--4. " PS[4:0] ,ADC clock prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1020000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x20001)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x201)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADEVMODECR,EV MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No event group results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event group (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the event group" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV8BIT ,Event group 8-bit result mode" "10-bit,8-bit"
|
|
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADG1MODECR,G1 MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No group1 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the group 1" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun group 1 RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Hardware"
|
|
bitfld.long 0x00 2. " G1_8BIT ,Group1 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion group 1" "Completed,Frozen"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADG2MODECR,G2 MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No group2 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the group 2" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun group 2 RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Hardware"
|
|
bitfld.long 0x00 2. " G2_8BIT ,Group2 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion group 2" "Completed,Frozen"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADEVSRC,Event Group Trigger Source Select"
|
|
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event group trigger on both edges" "EV_EDGE_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EV_EDG_SEL ,Event group trigger edge polarity select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET1[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADG1SRC,Group 1 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group1 trigger on both edges" "G1_EDG_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC group 1 trigger edge select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADG2SRC,Group 2 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group2 trigger on both edges" "G2_EDG_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC group 2 trigger edge select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADEVINTENA,Event Group Interrupt Enable"
|
|
bitfld.long 0x00 3. " EV_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event group memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event group memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ADG1INTENA,Group 1 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G1_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADG2INTENA,Group 2 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G2_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x34++0x0B
|
|
hide.long 0x00 "ADEVINTFLG,Event Group Interrupt Flag"
|
|
in
|
|
hide.long 0x04 "ADG1INTFLG,Group 1 Interrupt Flag"
|
|
in
|
|
hide.long 0x08 "ADG2INTFLG,Group 2 Interrupt Flag"
|
|
in
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADEVINTCR,Event Group Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event group interrupt threshold counter"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADG1INTCR,Group 1 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 interrupt threshold counter"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ADG2INTCR,Group 2 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 interrupt threshold counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADEVDMACR,Event Group DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of event group memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_EV_END ,Event group conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV_BLK_XFER ,Event group block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EV_DMA_EN ,Event group DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ADG1DMACR,Group 1 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of group 1 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G1_END ,Group1 conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ADG2DMACR,Group 2 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of group 2 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G2_END ,Group2 conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADBNDCR,Buffer Boundary Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A"
|
|
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ADBNDEND,Buffer End Boundary"
|
|
bitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM intialization process" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words"
|
|
width 10.
|
|
tree "ADC Sample Control Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ADEVSAMP,Event Group Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event group acquisition time"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "ADG1SAMP,Group1 Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 acquisition time"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "ADG2SAMP,Group2 Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 acquisition time"
|
|
tree.end
|
|
width 8.
|
|
tree "ADC Status Registers"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "ADEVSR,Event Group Status Register"
|
|
bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event group memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " EV_BUSY ,Event group Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " EV_STOP ,Event group conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended flag R/W" "Not completed,Completed"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "ADG1SR,Group 1 Status Register"
|
|
bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended flag" "Not completed,Completed"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADG2SR,Group 2 Status Register"
|
|
bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed"
|
|
tree.end
|
|
width 9.
|
|
tree "ADC Selection Control Registers"
|
|
sif cpu()=="RM57L843-ZWT"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADEVSEL,Event Group Select Register"
|
|
bitfld.long 0x00 31. " EVCHNSEL[31] ,A/D event channel 31 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 30. " EVCHNSEL[30] ,A/D event channel 30 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 29. " EVCHNSEL[29] ,A/D event channel 29 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 28. " EVCHNSEL[28] ,A/D event channel 28 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EVCHNSEL[27] ,A/D event channel 27 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 26. " EVCHNSEL[26] ,A/D event channel 26 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EVCHNSEL[25] ,A/D event channel 25 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D event channel 24 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADG1SEL,Group 1 Select Register"
|
|
bitfld.long 0x00 31. " G1CHNSEL[31] ,A/D channel 31 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 30. " G1CHNSEL[30] ,A/D channel 30 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 29. " G1CHNSEL[29] ,A/D channel 29 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 28. " G1CHNSEL[28] ,A/D channel 28 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G1CHNSEL[27] ,A/D channel 27 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 26. " G1CHNSEL[26] ,A/D channel 26 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " G1CHNSEL[25] ,A/D channel 25 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADG2SEL,Group 2 Select Register"
|
|
bitfld.long 0x00 31. " G2CHNSEL[31] ,A/D channel 31 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 30. " G2CHNSEL[30] ,A/D channel 30 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 29. " G2CHNSEL[29] ,A/D channel 29 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 28. " G2CHNSEL[28] ,A/D channel 28 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G2CHNSEL[27] ,A/D channel 27 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 26. " G2CHNSEL[26] ,A/D channel 26 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " G2CHNSEL[25] ,A/D channel 25 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADEVSEL,Event Group Select Register"
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADG1SEL,Group 1 Select Register"
|
|
bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADG2SEL,Group 2 Select Register"
|
|
bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
textline " "
|
|
sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C000+0x04))&0x80)==0x80)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits"
|
|
endif
|
|
endif
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ADSMSTATE,State Machine Current State"
|
|
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC state machine current state" "Idle,Conv_ev,Conv_sw1,Conv_sw2,Conv_cal,Start_ev,Start_sw1,Start_sw2,Start_cal,Wait_ev,Wait_sw1,Wait_sw2,Wait_cal,?..."
|
|
width 12.
|
|
sif (cpu()=="RM57L843-ZWT")
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ADLASTCONV,Last Conversion"
|
|
bitfld.long 0x00 31. " LAST_CONV[31] ,Digital input channel 31" "Low,High"
|
|
bitfld.long 0x00 30. " LAST_CONV[30] ,Digital input channel 30" "Low,High"
|
|
bitfld.long 0x00 29. " LAST_CONV[29] ,Digital input channel 29" "Low,High"
|
|
bitfld.long 0x00 28. " LAST_CONV[28] ,Digital input channel 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LAST_CONV[27] ,Digital input channel 27" "Low,High"
|
|
bitfld.long 0x00 26. " LAST_CONV[26] ,Digital input channel 26" "Low,High"
|
|
bitfld.long 0x00 25. " LAST_CONV[25] ,Digital input channel 25" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " LAST_CONV[24] ,Digital input channel 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High"
|
|
bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High"
|
|
bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High"
|
|
bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High"
|
|
bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High"
|
|
bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High"
|
|
bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High"
|
|
bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High"
|
|
bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High"
|
|
bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High"
|
|
bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High"
|
|
bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High"
|
|
bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High"
|
|
bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High"
|
|
else
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ADLASTCONV,Last Conversion"
|
|
bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High"
|
|
bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High"
|
|
bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High"
|
|
bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High"
|
|
bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High"
|
|
bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High"
|
|
bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High"
|
|
bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High"
|
|
bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High"
|
|
bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High"
|
|
bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High"
|
|
bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High"
|
|
bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High"
|
|
bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High"
|
|
endif
|
|
width 15.
|
|
tree "ADC Buffer Control Registers"
|
|
hgroup.long 0x90++0x1F
|
|
hide.long 0x00 "ADEVBUFFER0,Event Group Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADEVBUFFER1,Event Group Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADEVBUFFER2,Event Group Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADEVBUFFER3,Event Group Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADEVBUFFER4,Event Group Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADEVBUFFER5,Event Group Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADEVBUFFER6,Event Group Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADEVBUFFER7,Event Group Buffer 7"
|
|
in
|
|
hgroup.long 0xB0++0x1F
|
|
hide.long 0x00 "ADG1BUFFER0,Group1 Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADG1BUFFER1,Group1 Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADG1BUFFER2,Group1 Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADG1BUFFER3,Group1 Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADG1BUFFER4,Group1 Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADG1BUFFER5,Group1 Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADG1BUFFER6,Group1 Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADG1BUFFER7,Group1 Buffer 7"
|
|
in
|
|
hgroup.long 0xD0++0x1F
|
|
hide.long 0x00 "ADG2BUFFER0,Group2 Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADG2BUFFER1,Group2 Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADG2BUFFER2,Group2 Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADG2BUFFER3,Group2 Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADG2BUFFER4,Group2 Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADG2BUFFER5,Group2 Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADG2BUFFER6,Group2 Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADG2BUFFER7,Group2 Buffer 7"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "ADEVEMUBUFFER,Event Group EMU Buffer"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "ADG1BUFFER,Group 1 EMU Buffer"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "ADG2BUFFER,Group 2 EMU Buffer"
|
|
in
|
|
tree.end
|
|
width 11.
|
|
tree "ADC ADEVT Pin Control Registers"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ADEVTDIR,Event Group Pin Direction Selection"
|
|
bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Output disabled,Output enabled"
|
|
sif (cpu()=="RM48L950"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432")
|
|
if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x1000000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x01)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
endif
|
|
endif
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ADEVTIN,Event Group Pin Input Value"
|
|
bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ADEVTSET,Event Group Pin Set"
|
|
bitfld.long 0x00 0. " ADEVT_SET ,ADEVT pin set" "Low/no effect,High/set"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ADEVTCLR,Event Group Pin Clear"
|
|
bitfld.long 0x00 0. " ADEVT_CLR ,ADEVT pin clear" "Low/no effect,High/clear"
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01000000)==0x01000000)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01000000)==0x01000000))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
endif
|
|
else
|
|
if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
endif
|
|
endif
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ADEVTPSEL,Event Group Pull Select"
|
|
bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT pull select" "Pull-down,Pull-up"
|
|
tree.end
|
|
width 15.
|
|
tree "ADC Sampling Capacitor Discharge Mode Control Registers"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "ADEVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ADG1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ADG2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
tree.end
|
|
width 19.
|
|
tree "ADC Interrupt Control Registers"
|
|
sif (cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR1[11-0] ,12-bit compare value with MAG_CHID1"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP1 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT1 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the magnitude compare interrupt 1 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the magnitude compare interrupt 1 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR2[11-0] ,12-bit compare value with MAG_CHID2"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP2 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT2 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the magnitude compare interrupt 2 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the magnitude compare interrupt 2 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR3[11-0] ,12-bit compare value with MAG_CHID3"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP3 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT3 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the magnitude compare interrupt 3 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the magnitude compare interrupt 3 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
endif
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
endif
|
|
sif (cpu()!="RM57L843-ZWT")
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "MAGINTCTRL4,Magnitude Interrupt Control"
|
|
line.long 0x04 "MAGINT4MSK,Magnitude Interrupt Mask"
|
|
line.long 0x08 "MAGINTCTRL5,Magnitude Interrupt Control"
|
|
line.long 0x0C "MAGINT5MSK,Magnitude Interrupt Mask"
|
|
line.long 0x10 "MAGINTCTRL6,Magnitude Interrupt Control"
|
|
line.long 0x14 "MAGINT6MSK,Magnitude Interrupt Mask"
|
|
line.long 0x18 "MAGTHRINTENASET,Magnitude Interrupt Enable Set"
|
|
line.long 0x1C "MAGTHRINTENACLR,Magnitude Interrupt Enable Clear"
|
|
endif
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "ADMAGINTFLG,Magnitude Compare Interrupt Flag"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_INT3_SET/CLR ,Magnitude compare interrupt flag bit[3]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_INT2_SET/CLR ,Magnitude compare interrupt flag bit[2]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_INT1_SET/CLR ,Magnitude compare interrupt flag bit[1]" "No interrupt,Interrupt"
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "ADMAGINTOFF,Magnitude Compare Interrupt Offset"
|
|
in
|
|
tree.end
|
|
width 17.
|
|
tree "ADC RAM Control Registers"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "ADEVFIFORESETCR,Event Group FIFO Reset"
|
|
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC event group FIFO" "No reset,Reset"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "ADG1FIFORESETCR,Group 1 FIFO Reset"
|
|
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC group 1 FIFO" "No reset,Reset"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "ADG2FIFORESETCR,Group 2 FIFO Reset"
|
|
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC group 2 FIFO" "No reset,Reset"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "ADEVRAMADDR,Event Group ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event group ADC RAM pointer"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "ADG1RAMADDR,Group 1 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM pointer"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "ADG2RAMADDR,Group 2 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM pointer"
|
|
tree.end
|
|
width 11.
|
|
tree "ADC Parity Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "ADPARCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits map" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "ADPARADDR,Parity Address"
|
|
hexmask.long.word 0x00 2.--11. 0x04 " ERROR_ADDRESS ,ERROR ADDRESS"
|
|
tree.end
|
|
width 16.
|
|
textline " "
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "ADPWRUPDLYCTRL,Power-Up Delay Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY[9-0] ,Number of VCLK cycles to wait"
|
|
sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM57L843-ZWT")
|
|
width 20.
|
|
tree "ADC Selection/count Registers"
|
|
group.long 0x190++0x0B
|
|
line.long 0x00 "ADEVCHNSELMODECTRL,ADC Event Group Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
line.long 0x04 "ADG1CHNSELMODECTRL,ADC Group1 Channel Selection Mode Control Register"
|
|
bitfld.long 0x04 0.--3. " G1_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
line.long 0x08 "ADG2CHNSELMODECTRL,ADC Group2 Channel Selection Mode Control Register"
|
|
bitfld.long 0x08 0.--3. " G2_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
group.long 0x19C++0x17
|
|
line.long 0x00 "ADEVCURRCOUNT,ADC Event Group Current Count Register"
|
|
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT ,CURRENT_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ADEVMAXCOUNT,ADC Event Group Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " EV_MAX_COUNT ,MAX_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ADG1CURRCOUNT,ADC Group1 Current Count Register"
|
|
bitfld.long 0x08 0.--4. " G1_CURRENT_COUNT ,CURRENT_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ADG1MAXCOUNT,ADC Group1 Maximum Count Register"
|
|
bitfld.long 0x0C 0.--4. " G1_MAX_COUNT ,MAX_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ADG2CURRCOUNT,ADC Group2 Current Count Register"
|
|
bitfld.long 0x10 0.--4. " G2_CURRENT_COUNT ,CURRENT_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ADG2MAXCOUNT,ADC Group2 Maximum Count Register"
|
|
bitfld.long 0x14 0.--4. " G2_MAX_COUNT ,MAX_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MIBADC2"
|
|
base ad:0xFFF7C200
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADRSTCR,ADC Reset Control Register"
|
|
bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADOPMODECR,ADC Operating Mode Control Register"
|
|
bitfld.long 0x00 31. " 10/12BIT ,Resolution of the ADC core select" "10-bit,12-bit"
|
|
bitfld.long 0x00 24. " COS ,ADCLK halt/continue when the emulation system enters suspend mode" "Halted,Continue"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " CHNTESTEN ,Enable the input channels impedance measurement mode" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16. " RAMTESTEN ,Enable the ADC results RAM test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,ADC core power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 4. " IDLEPWRDN ,ADC power down when idle" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADCEN ,ADC conversions enable" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLOCKCR,Clock Prescaler"
|
|
bitfld.long 0x00 0.--4. " PS[4:0] ,ADC clock prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x1020000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x20001)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x201)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x1000200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADCALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADEVMODECR,EV MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No event group results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event group (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the event group" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV8BIT ,Event group 8-bit result mode" "10-bit,8-bit"
|
|
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADG1MODECR,G1 MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No group1 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the group 1" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun group 1 RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Hardware"
|
|
bitfld.long 0x00 2. " G1_8BIT ,Group1 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion group 1" "Completed,Frozen"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADG2MODECR,G2 MODE Control Register"
|
|
bitfld.long 0x00 16. " NORESETONCHNSEL ,No group2 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) data format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the group 2" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun group 2 RAM ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Hardware"
|
|
bitfld.long 0x00 2. " G2_8BIT ,Group2 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion group 2" "Completed,Frozen"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADEVSRC,Event Group Trigger Source Select"
|
|
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event group trigger on both edges" "EV_EDGE_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EV_EDG_SEL ,Event group trigger edge polarity select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET1[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADG1SRC,Group 1 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group1 trigger on both edges" "G1_EDG_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC group 1 trigger edge select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADG2SRC,Group 2 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group2 trigger on both edges" "G2_EDG_SEL bit,Rising or falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC group 2 trigger edge select" "High/low,Low/high"
|
|
sif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]"
|
|
else
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADEVINTENA,Event Group Interrupt Enable"
|
|
bitfld.long 0x00 3. " EV_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event group memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event group memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ADG1INTENA,Group 1 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G1_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADG2INTENA,Group 2 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G2_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x34++0x0B
|
|
hide.long 0x00 "ADEVINTFLG,Event Group Interrupt Flag"
|
|
in
|
|
hide.long 0x04 "ADG1INTFLG,Group 1 Interrupt Flag"
|
|
in
|
|
hide.long 0x08 "ADG2INTFLG,Group 2 Interrupt Flag"
|
|
in
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADEVINTCR,Event Group Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event group interrupt threshold counter"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADG1INTCR,Group 1 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 interrupt threshold counter"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ADG2INTCR,Group 2 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 interrupt threshold counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADEVDMACR,Event Group DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of event group memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_EV_END ,Event group conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV_BLK_XFER ,Event group block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EV_DMA_EN ,Event group DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ADG1DMACR,Group 1 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of group 1 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G1_END ,Group1 conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ADG2DMACR,Group 2 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of group 2 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G2_END ,Group2 conversion end DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADBNDCR,Buffer Boundary Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A"
|
|
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ADBNDEND,Buffer End Boundary"
|
|
bitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM intialization process" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words"
|
|
width 10.
|
|
tree "ADC Sample Control Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ADEVSAMP,Event Group Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event group acquisition time"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "ADG1SAMP,Group1 Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 acquisition time"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "ADG2SAMP,Group2 Sampling Time Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 acquisition time"
|
|
tree.end
|
|
width 8.
|
|
tree "ADC Status Registers"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "ADEVSR,Event Group Status Register"
|
|
bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event group memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " EV_BUSY ,Event group Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " EV_STOP ,Event group conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended flag R/W" "Not completed,Completed"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "ADG1SR,Group 1 Status Register"
|
|
bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended flag" "Not completed,Completed"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADG2SR,Group 2 Status Register"
|
|
bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy flag" "Not active,Busy"
|
|
bitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen"
|
|
textline " "
|
|
eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed"
|
|
tree.end
|
|
width 9.
|
|
tree "ADC Selection Control Registers"
|
|
sif cpu()=="RM57L843-ZWT"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADEVSEL,Event Group Select Register"
|
|
bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D event channel 24 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADG1SEL,Group 1 Select Register"
|
|
bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADG2SEL,Group 2 Select Register"
|
|
bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADEVSEL,Event Group Select Register"
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADG1SEL,Group 1 Select Register"
|
|
bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADG2SEL,Group 2 Select Register"
|
|
bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
textline " "
|
|
sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C200+0x04))&0x80)==0x80)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFF7C200+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADCALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits"
|
|
endif
|
|
endif
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ADSMSTATE,State Machine Current State"
|
|
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC state machine current state" "Idle,Conv_ev,Conv_sw1,Conv_sw2,Conv_cal,Start_ev,Start_sw1,Start_sw2,Start_cal,Wait_ev,Wait_sw1,Wait_sw2,Wait_cal,?..."
|
|
width 12.
|
|
sif (cpu()=="RM57L843-ZWT")
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ADLASTCONV,Last Conversion"
|
|
textline " "
|
|
bitfld.long 0x00 24. " LAST_CONV[24] ,Digital input channel 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High"
|
|
bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High"
|
|
bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High"
|
|
bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High"
|
|
bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High"
|
|
bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High"
|
|
bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High"
|
|
bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High"
|
|
bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High"
|
|
bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High"
|
|
bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High"
|
|
bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High"
|
|
bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High"
|
|
bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High"
|
|
else
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ADLASTCONV,Last Conversion"
|
|
bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High"
|
|
bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High"
|
|
bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High"
|
|
bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High"
|
|
bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High"
|
|
bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High"
|
|
bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High"
|
|
bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High"
|
|
endif
|
|
width 15.
|
|
tree "ADC Buffer Control Registers"
|
|
hgroup.long 0x90++0x1F
|
|
hide.long 0x00 "ADEVBUFFER0,Event Group Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADEVBUFFER1,Event Group Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADEVBUFFER2,Event Group Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADEVBUFFER3,Event Group Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADEVBUFFER4,Event Group Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADEVBUFFER5,Event Group Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADEVBUFFER6,Event Group Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADEVBUFFER7,Event Group Buffer 7"
|
|
in
|
|
hgroup.long 0xB0++0x1F
|
|
hide.long 0x00 "ADG1BUFFER0,Group1 Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADG1BUFFER1,Group1 Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADG1BUFFER2,Group1 Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADG1BUFFER3,Group1 Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADG1BUFFER4,Group1 Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADG1BUFFER5,Group1 Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADG1BUFFER6,Group1 Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADG1BUFFER7,Group1 Buffer 7"
|
|
in
|
|
hgroup.long 0xD0++0x1F
|
|
hide.long 0x00 "ADG2BUFFER0,Group2 Buffer 0"
|
|
in
|
|
hide.long 0x04 "ADG2BUFFER1,Group2 Buffer 1"
|
|
in
|
|
hide.long 0x08 "ADG2BUFFER2,Group2 Buffer 2"
|
|
in
|
|
hide.long 0x0C "ADG2BUFFER3,Group2 Buffer 3"
|
|
in
|
|
hide.long 0x10 "ADG2BUFFER4,Group2 Buffer 4"
|
|
in
|
|
hide.long 0x14 "ADG2BUFFER5,Group2 Buffer 5"
|
|
in
|
|
hide.long 0x18 "ADG2BUFFER6,Group2 Buffer 6"
|
|
in
|
|
hide.long 0x1C "ADG2BUFFER7,Group2 Buffer 7"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "ADEVEMUBUFFER,Event Group EMU Buffer"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "ADG1BUFFER,Group 1 EMU Buffer"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "ADG2BUFFER,Group 2 EMU Buffer"
|
|
in
|
|
tree.end
|
|
width 11.
|
|
tree "ADC ADEVT Pin Control Registers"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ADEVTDIR,Event Group Pin Direction Selection"
|
|
bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Output disabled,Output enabled"
|
|
sif (cpu()=="RM48L950"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432")
|
|
if (((d.l((ad:0xFFF7C200+0xFC)))&0x1000000)==0x1000000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0xFFF7C200+0xFC)))&0x01)==0x01)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output"
|
|
endif
|
|
endif
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ADEVTIN,Event Group Pin Input Value"
|
|
bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ADEVTSET,Event Group Pin Set"
|
|
bitfld.long 0x00 0. " ADEVT_SET ,ADEVT pin set" "Low/no effect,High/set"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ADEVTCLR,Event Group Pin Clear"
|
|
bitfld.long 0x00 0. " ADEVT_CLR ,ADEVT pin clear" "Low/no effect,High/clear"
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01000000)==0x01000000)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01000000)==0x01000000))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
endif
|
|
else
|
|
if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01)==0x01))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if (((d.l((ad:0xFFF7C200+0xFC)))&0x1000000)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0xFFF7C200+0xFC)))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable"
|
|
endif
|
|
endif
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ADEVTPSEL,Event Group Pull Select"
|
|
bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT pull select" "Pull-down,Pull-up"
|
|
tree.end
|
|
width 15.
|
|
tree "ADC Sampling Capacitor Discharge Mode Control Registers"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "ADEVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ADG1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ADG2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles"
|
|
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
tree.end
|
|
width 19.
|
|
tree "ADC Interrupt Control Registers"
|
|
sif (cpu()=="RM57L843-ZWT")
|
|
if (((d.l(ad:0xFFF7C200+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR1[11-0] ,12-bit compare value with MAG_CHID1"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP1 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT1 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the magnitude compare interrupt 1 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the magnitude compare interrupt 1 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR2[11-0] ,12-bit compare value with MAG_CHID2"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP2 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT2 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the magnitude compare interrupt 2 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the magnitude compare interrupt 2 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR3[11-0] ,12-bit compare value with MAG_CHID3"
|
|
bitfld.long 0x00 15. " CHN_THR_COMP3 ,Channel OR threshold comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE_LT3 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the magnitude compare interrupt 3 mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the magnitude compare interrupt 3 mask 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
endif
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked"
|
|
endif
|
|
sif (cpu()!="RM57L843-ZWT")
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "MAGINTCTRL4,Magnitude Interrupt Control"
|
|
line.long 0x04 "MAGINT4MSK,Magnitude Interrupt Mask"
|
|
line.long 0x08 "MAGINTCTRL5,Magnitude Interrupt Control"
|
|
line.long 0x0C "MAGINT5MSK,Magnitude Interrupt Mask"
|
|
line.long 0x10 "MAGINTCTRL6,Magnitude Interrupt Control"
|
|
line.long 0x14 "MAGINT6MSK,Magnitude Interrupt Mask"
|
|
line.long 0x18 "MAGTHRINTENASET,Magnitude Interrupt Enable Set"
|
|
line.long 0x1C "MAGTHRINTENACLR,Magnitude Interrupt Enable Clear"
|
|
endif
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "ADMAGINTFLG,Magnitude Compare Interrupt Flag"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_INT3_SET/CLR ,Magnitude compare interrupt flag bit[3]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_INT2_SET/CLR ,Magnitude compare interrupt flag bit[2]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_INT1_SET/CLR ,Magnitude compare interrupt flag bit[1]" "No interrupt,Interrupt"
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "ADMAGINTOFF,Magnitude Compare Interrupt Offset"
|
|
in
|
|
tree.end
|
|
width 17.
|
|
tree "ADC RAM Control Registers"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "ADEVFIFORESETCR,Event Group FIFO Reset"
|
|
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC event group FIFO" "No reset,Reset"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "ADG1FIFORESETCR,Group 1 FIFO Reset"
|
|
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC group 1 FIFO" "No reset,Reset"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "ADG2FIFORESETCR,Group 2 FIFO Reset"
|
|
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC group 2 FIFO" "No reset,Reset"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "ADEVRAMADDR,Event Group ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event group ADC RAM pointer"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "ADG1RAMADDR,Group 1 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM pointer"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "ADG2RAMADDR,Group 2 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM pointer"
|
|
tree.end
|
|
width 11.
|
|
tree "ADC Parity Control Registers"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "ADPARCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits map" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "ADPARADDR,Parity Address"
|
|
hexmask.long.word 0x00 2.--11. 0x04 " ERROR_ADDRESS ,ERROR ADDRESS"
|
|
tree.end
|
|
width 16.
|
|
textline " "
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "ADPWRUPDLYCTRL,Power-Up Delay Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY[9-0] ,Number of VCLK cycles to wait"
|
|
sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM57L843-ZWT")
|
|
width 20.
|
|
tree "ADC Selection/count Registers"
|
|
group.long 0x190++0x0B
|
|
line.long 0x00 "ADEVCHNSELMODECTRL,ADC Event Group Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
line.long 0x04 "ADG1CHNSELMODECTRL,ADC Group1 Channel Selection Mode Control Register"
|
|
bitfld.long 0x04 0.--3. " G1_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
line.long 0x08 "ADG2CHNSELMODECTRL,ADC Group2 Channel Selection Mode Control Register"
|
|
bitfld.long 0x08 0.--3. " G2_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect"
|
|
group.long 0x19C++0x17
|
|
line.long 0x00 "ADEVCURRCOUNT,ADC Event Group Current Count Register"
|
|
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT ,CURRENT_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "ADEVMAXCOUNT,ADC Event Group Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " EV_MAX_COUNT ,MAX_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ADG1CURRCOUNT,ADC Group1 Current Count Register"
|
|
bitfld.long 0x08 0.--4. " G1_CURRENT_COUNT ,CURRENT_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "ADG1MAXCOUNT,ADC Group1 Maximum Count Register"
|
|
bitfld.long 0x0C 0.--4. " G1_MAX_COUNT ,MAX_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "ADG2CURRCOUNT,ADC Group2 Current Count Register"
|
|
bitfld.long 0x10 0.--4. " G2_CURRENT_COUNT ,CURRENT_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "ADG2MAXCOUNT,ADC Group2 Maximum Count Register"
|
|
bitfld.long 0x14 0.--4. " G2_MAX_COUNT ,MAX_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DCAN (Controller Area Network)"
|
|
tree "DCAN1"
|
|
base ad:0xFFF7DC00
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
|
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bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
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bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
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bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
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bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
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bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
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bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
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bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
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bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
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bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
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bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
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bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
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bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
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bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
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bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
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bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
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bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
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bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
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bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
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bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
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bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
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bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
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bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
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bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
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bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
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group.long 0xD8++0x0F
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line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
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bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
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line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
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bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCAN2"
|
|
base ad:0xFFF7DE00
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
|
|
bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
|
|
bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
|
|
bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
|
|
bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
|
|
bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
|
|
bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
|
|
bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
|
|
bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
|
|
bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
|
|
bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
|
|
bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
|
|
bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
|
|
bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
|
|
bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
|
|
bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
|
|
bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCAN3"
|
|
base ad:0xFFF7E000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7E000))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7E000))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
|
|
bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
|
|
bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
|
|
bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
|
|
bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
|
|
bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
|
|
bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
|
|
bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
|
|
bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
|
|
bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
|
|
bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
|
|
bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
|
|
bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
|
|
bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
|
|
bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
|
|
bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
|
|
bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7E000+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7E000+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137"))
|
|
tree "EMAC (Ethernet Media Access Controller)"
|
|
base ad:0xFCF78000
|
|
width 19.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TXREVID,Transmit Identification and Version Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "TXCONTROL,Transmit Control Register"
|
|
bitfld.long 0x0 0. " TXEN ,Transmit enable" "Disabled,Enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TXTEARDOWN,Transmit Teardown Register"
|
|
bitfld.long 0x0 0.--2. " TXTDNCH ,TX teardown channed" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "RXREVID,RX Identification and Version Register"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "RXCONTROL,RX Control Register"
|
|
bitfld.long 0x0 0. " RXEN ,RX DMA enable" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RXTEARDOWN,RX Teardown Register"
|
|
bitfld.long 0x0 0.--2. " RXTDNCH ,RX teardown channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "TXINTSTATRAW,Transmit Interrupt Status Register"
|
|
bitfld.long 0x0 7. " TX7PEND ,TX7PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " TX6PEND ,TX6PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TX5PEND ,TX5PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " TX4PEND ,TX4PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TX3PEND ,TX3PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " TX2PEND ,TX2PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TX1PEND ,TX1PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " TX0PEND ,TX0PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "TXINTSTATMASKED,Transmit Interrupt Status Register Masked"
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " TX7PEND_SETCLR ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " TX6PEND_SETCLR ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " TX5PEND_SETCLR ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " TX4PEND_SETCLR ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " TX3PEND_SETCLR ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " TX2PEND_SETCLR ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " TX1PEND_SETCLR ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " TX0PEND_SETCLR ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
sif (cpuis("TMS570LS1227*"))
|
|
rgroup.long 0x90++0x3
|
|
else
|
|
group.long 0x90++0x3
|
|
endif
|
|
line.long 0x0 "MACINVECTOR,MAC Input Vector Register"
|
|
bitfld.long 0x0 27. " STATPEND ,Status Pending" "0,1"
|
|
bitfld.long 0x0 26. " HOSTPEND ,Host Pending" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 25. " LINKINT0 ,MDIO Link Int" "0,1"
|
|
bitfld.long 0x0 24. " USERINT0 ,MDIO User Int" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--23. 1. " TXPEND ,TX Pend[7:0]"
|
|
hexmask.long.byte 0x0 8.--15. 1. " RXTHRESHPEND ,RX Thresh Pend[7:0]"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " RXPEND ,RX Pend[7:0]"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "MACEOIVECTOR,MAC End of Interrupt Vector"
|
|
bitfld.long 0x00 0.--4. " INTVECT ,MAC End Of Interrupt Vector" "C0RXTHRESH,C0RX,C0TX,C0MISC,C1RXTHRESH,C1RX,C1TX,C1MISC,C2RXTHRESH,C2RX,C2TX,C2MISC,?..."
|
|
sif (cpuis("TMS570LS1227*"))
|
|
rgroup.long 0xA0++0x3
|
|
else
|
|
group.long 0xA0++0x3
|
|
endif
|
|
line.long 0x0 "RXINTSTATRAW,Receive Interrupt Status Register Raw"
|
|
bitfld.long 0x0 15. " RX7THRESHPEND ,RX7THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 14. " RX6THRESHPEND ,RX6THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 13. " RX5THRESHPEND ,RX5THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RX4THRESHPEND ,RX4THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " RX3THRESHPEND ,RX3THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 10. " RX2THRESHPEND ,RX2THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 9. " RX1THRESHPEND ,RX1THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RX0THRESHPEND ,RX0THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 7. " RX7PEND ,RX7PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RX6PEND ,RX6PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 5. " RX5PEND ,RX5PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " RX4PEND ,RX4PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RX3PEND ,RX3PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " RX2PEND ,RX2PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 1. " RX1PEND ,RX1PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RX0PEND ,RX0PEND raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "RXINTSTATMASKED,Receive Interrupt Status Register Masked"
|
|
setclrfld.long 0x0 15. 0x4 15. 0x8 15. " RX7THRESHPEND_SETCLR ,RX7THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0x4 14. 0x8 14. " RX6THRESHPEND_SETCLR ,RX6THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 13. 0x4 13. 0x8 13. " RX5THRESHPEND_SETCLR ,RX5THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 12. 0x4 12. 0x8 12. " RX4THRESHPEND_SETCLR ,RX4THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 11. 0x4 11. 0x8 11. " RX3THRESHPEND_SETCLR ,RX3THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0x4 10. 0x8 10. " RX2THRESHPEND_SETCLR ,RX2THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " RX1THRESHPEND_SETCLR ,RX1THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " RX0THRESHPEND_SETCLR ,RX0THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " RX7PEND_SETCLR ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " RX6PEND_SETCLR ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " RX5PEND_SETCLR ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " RX4PEND_SETCLR ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " RX3PEND_SETCLR ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " RX2PEND_SETCLR ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " RX1PEND_SETCLR ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " RX0PEND_SETCLR ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "MACINTSTATRAW,MAC Interrupt Status Register Raw (Unmasked)"
|
|
bitfld.long 0x0 1. " HOSTPEND ,Host pending interrupt (HOSTPEND); raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " STATPEND ,Statistics pending interrupt (STATPEND); raw interrupt read (before mask)" "No interrupt,Interrupt"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "MACINTSTATMASKED,MAC Interrupt Status Register Masked"
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " HOSTPEND_SETCLR ,Host pending interrupt (HOSTPEND); masked interrupt read" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " STATPEND_SETCLR ,Statistics pending interrupt (STATPEND); masked interrupt read" "No interrupt,Interrupt"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register"
|
|
bitfld.long 0x0 30. " RXPASSCRC ,Pass receive CRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " RXQOSEN ,Receive quality of service enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
|
|
textline " "
|
|
bitfld.long 0x0 24. " RXCMFEN ,Receive copy MAC control frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " RXCSFEN ,Receive copy short frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " RXCEFEN ,Receive copy error frames enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " RXCAFEN ,Receive copy all frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " RXPROMCH ,Receive promiscuous channel select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 13. " RXBROADEN ,Receive broadcast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8.--10. " RXBROADCH ,Receive broadcast channel select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5. " RXMULTEN ,RX multicast enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " RXMULTCH ,RX multicast channel select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "RXUNICASTSET,Receive Unicast Enable Set Register"
|
|
bitfld.long 0x0 7. " RXCH7EN ,RX channel 7 unicast enable set" "No effect,Set"
|
|
bitfld.long 0x0 6. " RXCH6EN ,RX channel 6 unicast enable set" "No effect,Set"
|
|
bitfld.long 0x0 5. " RXCH5EN ,RX channel 5 unicast enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 4. " RXCH4EN ,RX channel 4 unicast enable set" "No effect,Set"
|
|
bitfld.long 0x0 3. " RXCH3EN ,RX channel 3 unicast enable set" "No effect,Set"
|
|
bitfld.long 0x0 2. " RXCH2EN ,RX channel 2 unicast enable set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1EN ,RX channel 1 unicast enable set" "No effect,Set"
|
|
bitfld.long 0x0 0. " RXCH0EN ,RX channel 0 unicast enable set" "No effect,Set"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "RXUNICASTCLEAR,Receive Unicast Clear Register"
|
|
bitfld.long 0x0 7. " RXCH7EN ,RX channel 7 unicast enable clear" "No effect,Clear"
|
|
bitfld.long 0x0 6. " RXCH6EN ,RX channel 6 unicast enable clear" "No effect,Clear"
|
|
bitfld.long 0x0 5. " RXCH5EN ,RX channel 5 unicast enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 4. " RXCH4EN ,RX channel 4 unicast enable clear" "No effect,Clear"
|
|
bitfld.long 0x0 3. " RXCH3EN ,RX channel 3 unicast enable clear" "No effect,Clear"
|
|
bitfld.long 0x0 2. " RXCH2EN ,RX channel 2 unicast enable clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1EN ,RX channel 1 unicast enable clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RXCH0EN ,RX channel 0 unicast enable clear" "No effect,Clear"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "RXMAXLEN,Receive Maximum Length Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RXMAXLEN ,RX maximum frame length"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "RXBUFFEROFFSET,Receive Buffer Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RXBUFFEROFFSET ,RX buffer offset value"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "RXFILTERLOWTHRESH,Receive Filter Low Priority Frame Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RXFILTERTHRESH ,RX filter low threshold"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX1FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX2FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX3FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX4FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX5FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x138++0x3
|
|
line.long 0x0 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX6FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x13C++0x3
|
|
line.long 0x0 "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX7FLOWTHRESH ,RX flow threshold"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX1FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX2FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX3FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX4FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX5FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x158++0x3
|
|
line.long 0x0 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX6FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x15C++0x3
|
|
line.long 0x0 "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX7FREEBUF ,RX free buffer count; Write to increment"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "MACCONTROL,MAC Control Register"
|
|
bitfld.long 0x0 15. " RMIISPEED ,RMII 10/100 Speed Select (IFCTLA)" "10,100"
|
|
bitfld.long 0x0 14. " RXOFFLENBLOCK ,Receive Offset / Length word write block" "Not blocked/Length word,Blocked/During processing"
|
|
textline " "
|
|
bitfld.long 0x0 13. " RXOWNERSHIP ,Receive ownership write bit value" "0,1"
|
|
bitfld.long 0x0 11. " CMDIDLE ,Command Idle" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " TXSHORTGAPEN ,Transmit short gap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " TXPTYPE ,Transmit queue priority type" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " GMIIEN ,GMII enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " RXBUFFERFLOWEN ,Receive buffer flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " LOOPBACK ,Loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " FULLDUPLEX ,Full duplex mode; gigabit mode forces full duplex mode regardless of whether the fullduplex bit isset or not" "Disabled,Enabled"
|
|
sif (cpuis("TMS570LS1227*"))
|
|
rgroup.long 0x164++0x3
|
|
else
|
|
group.long 0x164++0x3
|
|
endif
|
|
line.long 0x0 "MACSTATUS,MAC Status Register"
|
|
bitfld.long 0x0 31. " IDLE ,CPGMAC idle" "Not idle,Idle"
|
|
bitfld.long 0x0 20.--23. " TXERRCODE ,TX host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer descriptor pointer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " TXERRCH ,TX host error channel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " RXERRCODE ,RX host error code" "No error,Reserved,Ownership bit not set in SOP buffer,Reserved,Zero buffer pointer,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8.--10. " RXERRCH ,RX host error channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. " RXQOSACT ,RX Quality of Service active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXFLOWACT ,RX flow control active" "Not active,Active"
|
|
bitfld.long 0x0 0. " TXFLOWACT ,TX flow control active" "Not active,Active"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "EMCONTROL,Emulation Control Register"
|
|
bitfld.long 0x0 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " FREE ,Emulation free bit" "Disabled,Enabled"
|
|
group.long 0x16C++0x3
|
|
line.long 0x0 "FIFOCONTROL,FIFO Control Register"
|
|
bitfld.long 0x0 0.--1. " TXCELLTHRESH ,TX FIFO cell threshold" "Reserved,Reserved,Two packet cells,Three packet cells"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "MACCONFIG,MAC Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " TXCELLDEPTH ,TX cell depth - the number of cells in the transmit FIFO"
|
|
hexmask.long.byte 0x0 16.--23. 1. " RXCELLDEPTH ,RX cell depth - the number of cells in the receive FIFO"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " ADDRESSTYPE ,Address type in the design"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACCFIG ,MAC configuration value"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "SOFTRESET,Soft Reset Register"
|
|
bitfld.long 0x0 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "MACSRCADDRLO,MAC Source Address Low"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits MACADDR[7:0]"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15:9 MACADDR[15:8]"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "MACSRCADDRHI,MAC Source Address High"
|
|
hexmask.long.byte 0x0 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23:16 (byte 2)"
|
|
hexmask.long.byte 0x0 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31:23 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39:32 (byte 4)"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47:40 (byte 5)"
|
|
group.long 0x1D8++0x3
|
|
line.long 0x0 "MACHASH1,MAC Hash Address Register 1"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x0 "MACHASH2,MAC Hash Address Register 2"
|
|
rgroup.long 0x1E0++0x3
|
|
line.long 0x0 "BOFFTEST,Back Off Test Register"
|
|
hexmask.long.word 0x0 16.--25. 1. " RNDNUM ,Backoff random number generator"
|
|
bitfld.long 0x0 12.--15. " COLLCOUNT ,Collision count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--9. 1. " TXBACKOFF ,Backoff count"
|
|
rgroup.long 0x1E4++0x3
|
|
line.long 0x0 "TPACETEST,Transmit Pacing Algorithm Test Register"
|
|
bitfld.long 0x0 0.--4. " PACEVAL ,Pacing register current value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "RXPAUSE,Receive Pause Timer Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " PAUSETIMER ,RX pause timer value"
|
|
rgroup.long 0x1EC++0x3
|
|
line.long 0x0 "TXPAUSE,Transmit Pause Timer Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " PAUSETIMER ,TX pause timer value"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "MACADDRLO,MAC Address Low - From Receive Address Matching Memory Map"
|
|
bitfld.long 0x0 20. " VALID ," "Not valid,Valid"
|
|
bitfld.long 0x0 19. " MATCHFILT ," "Filter,Match"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CHANNEL ,Channel select" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACADDR0 ,MAC addres lower 8 bits (byte 0)"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACADDR1 ,MAC addres bits 15:8 (byte 1)"
|
|
group.long 0x504++0x3
|
|
line.long 0x0 "MACADDRHI,MAC Address High - Receive Address Matching"
|
|
hexmask.long.byte 0x0 24.--31. 1. " MACADDR2 ,MAC source address bits 23:16 (byte 2)"
|
|
hexmask.long.byte 0x0 16.--23. 1. " MACADDR3 ,MAC source address bits 31:23 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " MACADDR4 ,MAC source address bits 39:32 (byte 4)"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MACADDR5 ,MAC source address bits 47:40 (byte 5)"
|
|
group.long 0x508++0x3
|
|
line.long 0x0 "MACINDEX,MAC Index Register"
|
|
bitfld.long 0x0 0.--4. " MACINDEX ,MAC address index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
|
|
group.long 0x604++0x3
|
|
line.long 0x0 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
|
|
group.long 0x608++0x3
|
|
line.long 0x0 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
|
|
group.long 0x60C++0x3
|
|
line.long 0x0 "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
|
|
group.long 0x610++0x3
|
|
line.long 0x0 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
|
|
group.long 0x614++0x3
|
|
line.long 0x0 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
|
|
group.long 0x618++0x3
|
|
line.long 0x0 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
|
|
group.long 0x61C++0x3
|
|
line.long 0x0 "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
|
|
group.long 0x624++0x3
|
|
line.long 0x0 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
|
|
group.long 0x628++0x3
|
|
line.long 0x0 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
|
|
group.long 0x62C++0x3
|
|
line.long 0x0 "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
|
|
group.long 0x630++0x3
|
|
line.long 0x0 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
|
|
group.long 0x634++0x3
|
|
line.long 0x0 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
|
|
group.long 0x63C++0x3
|
|
line.long 0x0 "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
|
|
group.long 0x640++0x3
|
|
line.long 0x0 "TX0CP,Transmit Channel 0 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x644++0x3
|
|
line.long 0x0 "TX1CP,Transmit Channel 1 Completion Pointer Register"
|
|
group.long 0x648++0x3
|
|
line.long 0x0 "TX2CP,Transmit Channel 2 Completion Pointer Register"
|
|
group.long 0x64C++0x3
|
|
line.long 0x0 "TX3CP,Transmit Channel 3 Completion Pointer Register"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "TX4CP,Transmit Channel 4 Completion Pointer Register"
|
|
group.long 0x654++0x3
|
|
line.long 0x0 "TX5CP,Transmit Channel 5 Completion Pointer Register"
|
|
group.long 0x658++0x3
|
|
line.long 0x0 "TX6CP,Transmit Channel 6 Completion Pointer Register"
|
|
group.long 0x65C++0x3
|
|
line.long 0x0 "TX7CP,Transmit Channel 7 Completion Pointer Register"
|
|
group.long 0x660++0x3
|
|
line.long 0x0 "RX0CP,Receive Channel 0 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x664++0x3
|
|
line.long 0x0 "RX1CP,Receive Channel 1 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x668++0x3
|
|
line.long 0x0 "RX2CP,Receive Channel 2 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x66C++0x3
|
|
line.long 0x0 "RX3CP,Receive Channel 3 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x670++0x3
|
|
line.long 0x0 "RX4CP,Receive Channel 4 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x674++0x3
|
|
line.long 0x0 "RX5CP,Receive Channel 5 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x678++0x3
|
|
line.long 0x0 "RX6CP,Receive Channel 6 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x67C++0x3
|
|
line.long 0x0 "RX7CP,Receive Channel 7 Completion Pointer (Interrupt Ack) Register"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "RXGOODFRAMES,Good RX Frames"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "RXBCASTFRAMES,Total number of good broadcast frames received"
|
|
group.long 0x208++0x3
|
|
line.long 0x0 "RXMCASTFRAMES,Total number of good multicast frames received"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "RXPAUSEFRAMES,Pause RX Frames Register"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "RXCRCERRORS,Total number of frames received with CRC errors"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RXALIGNCODEERRORS,Total number of frames received with alignment/code errors"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "RXOVERSIZED,Total number of oversized frames received"
|
|
group.long 0x21C++0x3
|
|
line.long 0x0 "RXJABBER,Total number of jabber frames received"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "RXUNDERSIZED,Total number of undersized frames received"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "RXFRAGMENTS,RX Frame Fragments Register"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "RXFILTERED,Filtered Receive Frames"
|
|
group.long 0x22C++0x3
|
|
line.long 0x0 "RXQOSFILTERED,Received Frames Filtered by QOS"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "RXOCTETS,Total number of received bytes in good frames"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "TXGOODFRAMES,Total number of good frames transmitted"
|
|
group.long 0x238++0x3
|
|
line.long 0x0 "TXBCASTFRAMES,Broadcast TX Frames Register"
|
|
group.long 0x23C++0x3
|
|
line.long 0x0 "TXMCASTFRAMES,Multicast TX Frames Register"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "TXPAUSEFRAMES,Pause TX Frames Register"
|
|
group.long 0x244++0x3
|
|
line.long 0x0 "TXDEFERRED,Deferred TX Frames Register"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "TXCOLLISION,TX Collision Frames Register"
|
|
group.long 0x24C++0x3
|
|
line.long 0x0 "TXSINGLECOLL,TX Single Collision Frames Register"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "TXMULTICOLL,TX Multiple Collision Frames Register"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "TXEXCESSIVECOLL,TX Excessive Collision Frames Register"
|
|
group.long 0x258++0x3
|
|
line.long 0x0 "TXLATECOLL,TX Late Collision Frames Register"
|
|
group.long 0x25C++0x3
|
|
line.long 0x0 "TXUNDERRUN,TX Underrun Error Register"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "TXCARRIERSENSE,TX Carrier Sense Errors Register"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "TXOCTETS,TX Octet Frames Register"
|
|
group.long 0x268++0x3
|
|
line.long 0x0 "FRAME64,Transmit and Receive 64 Octet Frames Register"
|
|
group.long 0x26C++0x3
|
|
line.long 0x0 "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register"
|
|
group.long 0x270++0x3
|
|
line.long 0x0 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register"
|
|
group.long 0x278++0x3
|
|
line.long 0x0 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register"
|
|
group.long 0x27C++0x3
|
|
line.long 0x0 "FRAME1024TUP,Transmit and Receive 1024 to 1518 Octet Frames Register"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "NETOCTETS,Network Octet Frames Register"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register"
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "RXMOFOVERRUNS,Receive FIFO or DMA Middle of Frame Overruns Register"
|
|
group.long 0x28C++0x3
|
|
line.long 0x0 "RXDMAOVERRUNS,Receive DMA Start of Frame and Middle of Frame Overruns Register"
|
|
width 11.
|
|
tree.end
|
|
tree "CPGMAC"
|
|
base ad:0xFCF78800
|
|
width 16.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "REVID,Transmit Identification and Version Register"
|
|
hexmask.long 0x0 0.--31. 1. " REV ,REV ID"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SOFTRESET,Software Reset Register"
|
|
bitfld.long 0x0 0. " RESET ,Soft Reset for CPGMACSS_R modules INT, REGS, CPPI" "No reset,Reset"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "INTCONTROL,Interrupt Control Register"
|
|
sif (!cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x0 21. " C2TXPACEEN ,C2_TX_PULSE Pacing" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 20. " C2RXPACEEN ,C2_RX_PULSE Pacing" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 19. " C1TXPACEEN ,C1_TX_PULSE Pacing" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 18. " C1RXPACEEN ,C1_RX_PULSE Pacing" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 17. " C0TXPACEEN ,C0_TX_PULSE Pacing" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 16. " C0RXPACEEN ,C0_RX_PULSE Pacing" "No interrupt,Interrupt"
|
|
textline " "
|
|
hexmask.long.word 0x0 0.--11. 1. " INTPRESCALE ,Interrupt Counter Prescaler (Number of 4us VBUSP_CLKs)"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "C0RXTHRESHEN,Core 0 Receive Threshold Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "C0RXEN,Core 0 Receive Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "C0TXEN,Core 0 Transmit Enable Register"
|
|
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "C0MISCEN,Core 0 Misc Interrupt Enable Register"
|
|
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
|
|
sif (!cpuis("TMS570LS1227*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "C1RXTHRESHEN,Core 1 Receive Threshold Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "C1RXEN,Core 1 Receive Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "C1TXEN,Core 1 Transmit Enable Register"
|
|
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "C1MISCEN,Core 1 Misc Enable Register"
|
|
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "C2RXTHRESHEN,Core 2 Receive Threshold Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "C2RXEN,Core 2 Receive Enable Register"
|
|
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "C2TXEN,Core 2 Transmit Enable Register"
|
|
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "C2MISCEN,Core 2 Misc Enable Register"
|
|
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "C0RXTHRESHSTAT,Core 0 Receive Threshold Status Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "C0RXSTAT,Core 0 Receive Status Register"
|
|
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "C0TXSTAT,Core 0 Transmit Status Register"
|
|
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "C0MISCSTAT,Core 0 Misc Interrupt Status Register"
|
|
bitfld.long 0x0 3. " STATPENDSTAT ," "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " HOSTPENDSTAT ," "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0STAT ," "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " USERINT0STAT ," "No interrupt,Interrupt"
|
|
sif (!cpuis("TMS570LS1227*"))
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "C1RXTHRESHSTAT,Core 1 Receive Threshold Status Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "C1RXSTAT,Core 1 Receive Status Register"
|
|
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "C1TXSTAT,Core 1 Transmit Status Register"
|
|
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "C1MISCSTAT,Core 1 Misc Interrupt Status Register"
|
|
bitfld.long 0x0 3. " STATPENDSTAT ," "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HOSTPENDSTAT ," "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0STAT ," "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " USERINT0STAT ," "Disabled,Enabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "C2RXTHRESHSTAT,Core 2 Receive Threshold Status Register"
|
|
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "C2RXSTAT,Core 2 Receive Status Register"
|
|
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "C2TXSTAT,Core 2 Transmit Status Register"
|
|
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "C2MISCSTAT,Core 2 Misc Interrupt Status Register"
|
|
bitfld.long 0x0 3. " STATPENDSTAT ," "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HOSTPENDSTAT ," "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " LINKINT0STAT ," "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " USERINT0STAT ," "Disabled,Enabled"
|
|
endif
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "C0RXIMAX,Core 0 Receive Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " RXIMAX ,Core 0 Receive Interrupts per Millisecond for C0RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "C0TXIMAX,Core 0 Transmit Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " TXIMAX ,Core 0 Receive Interrupts per Millisecond for C0TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (!cpuis("TMS570LS1227*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "C1RXIMAX,Core 1 Receive Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " RXIMAX ,Core 1 Receive Interrupts per Millisecond for C1RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "C1TXIMAX,Core 1 Transmit Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " TXIMAX ,Core 1 Receive Interrupts per Millisecond for C1TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "C2RXIMAX,Core 2 Receive Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " RXIMAX ,Core 1 Receive Interrupts per Millisecond for C1RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "C2TXIMAX,Core 2 Transmit Interrupts per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " TXIMAX ,Core 1 Receive Interrupts per Millisecond for C1TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "MDIO (Management Data Input/Output)"
|
|
base ad:0xFCF78900
|
|
width 18.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "REV,MDIO Version Register"
|
|
sif (cpuis("TMS570LS1227*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CONTROL,MDIO Control Register"
|
|
rbitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle"
|
|
bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error"
|
|
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divider bits"
|
|
else
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CONTROL,MDIO Control Register"
|
|
bitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle"
|
|
bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error"
|
|
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divider bits"
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ALIVE,PHY Acknowledge Status Register"
|
|
eventfld.long 0x00 31. " ALIVE[31] ,PHY access acknowledge bit 31" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 30. " ALIVE[30] ,PHY access acknowledge bit 30" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 29. " ALIVE[29] ,PHY access acknowledge bit 29" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 28. " ALIVE[28] ,PHY access acknowledge bit 28" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 27. " ALIVE[27] ,PHY access acknowledge bit 27" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 26. " ALIVE[26] ,PHY access acknowledge bit 26" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ALIVE[25] ,PHY access acknowledge bit 25" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 24. " ALIVE[24] ,PHY access acknowledge bit 24" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ALIVE[23] ,PHY access acknowledge bit 23" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 22. " ALIVE[22] ,PHY access acknowledge bit 22" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ALIVE[21] ,PHY access acknowledge bit 21" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 20. " ALIVE[20] ,PHY access acknowledge bit 20" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ALIVE[19] ,PHY access acknowledge bit 19" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 18. " ALIVE[18] ,PHY access acknowledge bit 18" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ALIVE[17] ,PHY access acknowledge bit 17" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 16. " ALIVE[16] ,PHY access acknowledge bit 16" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ALIVE[15] ,PHY access acknowledge bit 15" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 14. " ALIVE[14] ,PHY access acknowledge bit 14" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ALIVE[13] ,PHY access acknowledge bit 13" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 12. " ALIVE[12] ,PHY access acknowledge bit 12" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ALIVE[11] ,PHY access acknowledge bit 11" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 10. " ALIVE[10] ,PHY access acknowledge bit 10" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ALIVE[9] ,PHY access acknowledge bit 9" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 8. " ALIVE[8] ,PHY access acknowledge bit 8" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ALIVE[7] ,PHY access acknowledge bit 7" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 6. " ALIVE[6] ,PHY access acknowledge bit 6" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ALIVE[5] ,PHY access acknowledge bit 5" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 4. " ALIVE[4] ,PHY access acknowledge bit 4" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ALIVE[3] ,PHY access acknowledge bit 3" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 2. " ALIVE[2] ,PHY access acknowledge bit 2" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ALIVE[1] ,PHY access acknowledge bit 1" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x00 0. " ALIVE[0] ,PHY access acknowledge bit 0" "Not acknowledged,Acknowledged"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "LINK,PHY Link Status Register"
|
|
bitfld.long 0x00 31. " LINK[31] ,PHY read transaction acknowledge bit 31" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 30. " LINK[30] ,PHY read transaction acknowledge bit 30" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 29. " LINK[29] ,PHY read transaction acknowledge bit 29" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 28. " LINK[28] ,PHY read transaction acknowledge bit 28" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LINK[27] ,PHY read transaction acknowledge bit 27" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 26. " LINK[26] ,PHY read transaction acknowledge bit 26" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINK[25] ,PHY read transaction acknowledge bit 25" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 24. " LINK[24] ,PHY read transaction acknowledge bit 24" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LINK[23] ,PHY read transaction acknowledge bit 23" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 22. " LINK[22] ,PHY read transaction acknowledge bit 22" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 21. " LINK[21] ,PHY read transaction acknowledge bit 21" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " LINK[20] ,PHY read transaction acknowledge bit 20" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LINK[19] ,PHY read transaction acknowledge bit 19" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " LINK[18] ,PHY read transaction acknowledge bit 18" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LINK[17] ,PHY read transaction acknowledge bit 17" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 16. " LINK[16] ,PHY read transaction acknowledge bit 16" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LINK[15] ,PHY read transaction acknowledge bit 15" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 14. " LINK[14] ,PHY read transaction acknowledge bit 14" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LINK[13] ,PHY read transaction acknowledge bit 13" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 12. " LINK[12] ,PHY read transaction acknowledge bit 12" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LINK[11] ,PHY read transaction acknowledge bit 11" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 10. " LINK[10] ,PHY read transaction acknowledge bit 10" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LINK[9] ,PHY read transaction acknowledge bit 9" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 8. " LINK[8] ,PHY read transaction acknowledge bit 8" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LINK[7] ,PHY read transaction acknowledge bit 7" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 6. " LINK[6] ,PHY read transaction acknowledge bit 6" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LINK[5] ,PHY read transaction acknowledge bit 5" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 4. " LINK[4] ,PHY read transaction acknowledge bit 4" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LINK[3] ,PHY read transaction acknowledge bit 3" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 2. " LINK[2] ,PHY read transaction acknowledge bit 2" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LINK[1] ,PHY read transaction acknowledge bit 1" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 0. " LINK[0] ,PHY read transaction acknowledge bit 0" "Not acknowledged,Acknowledged"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "LINKINTRAW,MDIO Link Interrupt Raw Register"
|
|
eventfld.long 0x00 1. " USERPHY1 ,MDIO Link change event raw value" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " USERPHY0 ,MDIO Link change event raw value" "Not changed,Changed"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "LINKINTMASKED,MDIO Link Interrupt Masked Register"
|
|
eventfld.long 0x00 1. " USERPHY1 ,MDIO Link change interrupt masked value" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " USERPHY0 ,MDIO Link change interrupt masked value" "Not changed,Changed"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "USERINTRAW,MDIO User Interrupt Raw Register"
|
|
eventfld.long 0x00 1. " USERACCESS1 ,MDIO User command complete event bit" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " USERACCESS0 ,MDIO User command complete event bit" "Not completed,Completed"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "USERINTMASKED,MDIO User Interrupt Masked Register Set/Clr"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "USERACCESS0,MDIO User Access Register 0"
|
|
bitfld.long 0x0 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1"
|
|
bitfld.long 0x0 30. " WRITE ,Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " ACK ,PHY ACK of read transaction" "0,1"
|
|
bitfld.long 0x0 21.--25. " REGADR ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0 16.--20. " PHYADR ,PHY Address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,User Data. Data to be read or written to PHY register"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "USERPHYSEL0,MDIO User PHY Select REG0"
|
|
bitfld.long 0x0 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1"
|
|
bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " PHYADRMON ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "USERACCESS1,MDIO User Access Register 1"
|
|
bitfld.long 0x0 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1"
|
|
bitfld.long 0x0 30. " WRITE ,Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " ACK ,PHY ACK of read transaction" "0,1"
|
|
bitfld.long 0x0 21.--25. " REGADR ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0 16.--20. " PHYADR ,PHY Address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0 0.--15. 1. " DATA ,User Data. Data to be read or written to PHY register"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "USERPHYSEL1,MDIO User PHY Select REG1"
|
|
bitfld.long 0x0 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1"
|
|
bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " PHYADRMON ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
sif (cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2137"))
|
|
tree "FLEXRAY"
|
|
base ad:0xFFF7C800
|
|
width 13.
|
|
tree "Special Registers"
|
|
sif (!cpuis("TMS570LS2124-PGE")&&!cpuis("TMS570LS2124-ZWT")&&!cpuis("TMS570LS2134-PGE")&&!cpuis("TMS570LS2134-ZWT")&&!cpuis("TMS570LS3134-PGE")&&!cpuis("TMS570LS3134-ZWT")&&!cpuis("TMS570LS3135-PGE")&&!cpuis("TMS570LS3135-ZWT")&&!cpuis("TMS570LS3136")&&!cpuis("TMS570LS3137-PGE")&&!cpuis("TMS570LS3137-ZWT")&&!cpuis("TMS570LS30336")&&!cpuis("TMS570LS2126")&&!cpuis("TMS570LS2127")&&!cpuis("TMS570LS2136")&&!cpuis("TMS570LS2137")&&!cpuis("TMS570LS2125-PGE")&&!cpuis("TMS570LS2125-ZWT")&&!cpuis("TMS570LS2135-PGE")&&!cpuis("TMS570LS2135-ZWT")&&!cpuis("TMS570LC4357")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP"))
|
|
tree "ECC Registers"
|
|
newline
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "ECCDR,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " DIAGSEL ,Diagnostic mode select key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x04 "ECCDSR,ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 23. " DEFH ,ECC double bit error flag for FTU RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 22. " DEFG ,ECC double bit error flag for FlexRay message RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 21. " DEFF ,ECC double bit error flag for transient buffer B RAM" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 20. " DEFE ,ECC double bit error flag for transient buffer A RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 19. " DEFD ,ECC double bit error flag for output buffer 2 RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 18. " DEFC ,ECC double bit error flag for output buffer 1 RAM" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 17. " DEFB ,ECC double bit error flag for input buffer 2 RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 16. " DEFA ,ECC double bit error flag for input buffer 1 RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 7. " SEFH ,ECC single bit error flag for FTU ram" "not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 6. " SEFG ,ECC single bit error flag for flexray message RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 5. " SEFF ,ECC single bit error flag for transient buffer B RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 4. " SEFE ,ECC single bit error flag for transient buffer A RAM" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 3. " SEFD ,ECC Single bit error flag for output buffer 2 RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 2. " SEFC ,ECC single bit error flag for output buffer 1 RAM" "Not detected,Detected"
|
|
eventfld.long 0x04 1. " SEFB ,ECC single bit error flag for input buffer 2 RAM" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 0. " SEFA ,ECC Single bit error flag for input buffer 1 RAM" "Not detected,Detected"
|
|
line.long 0x08 "ECCTR,ECC Test Register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " RDECC ,Holds ECC bits when reading a RAM location"
|
|
hexmask.long.byte 0x08 0.--6. 1. " WRECC ,ECC bits to be written in ECC location when writing to a RAM location"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "ECCCR,ECC Control Register"
|
|
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC single bit error indication" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " SBEL ,ECC single bit error lock" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DIAGSEL ,Diagnostic mode select key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "ECCDSR,ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 23. " DEFH ,ECC double bit error flag for FTU RAM" "No error,Error"
|
|
eventfld.long 0x04 22. " DEFG ,ECC double bit error flag for flexray message RAM" "No error,Error"
|
|
eventfld.long 0x04 21. " DEFF ,ECC double bit error flag for transient buffer B RAM" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 20. " DEFE ,ECC double bit error flag for transient buffer A RAM" "No error,Error"
|
|
eventfld.long 0x04 19. " DEFD ,ECC double bit error flag for output buffer 2 RAM" "No error,Error"
|
|
eventfld.long 0x04 18. " DEFC ,ECC double bit error flag for output buffer 1 RAM" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " DEFB ,ECC double bit error flag for input buffer 2 RAM" "No error,Error"
|
|
eventfld.long 0x04 16. " DEFA ,ECC double bit error flag for input buffer 1 RAM" "No error,Error"
|
|
eventfld.long 0x04 7. " SEFH ,ECC single bit error flag for FTU RAM" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 6. " SEFG ,ECC single bit error flag for flexray message RAM" "No error,Error"
|
|
eventfld.long 0x04 5. " SEFF ,ECC single bit error flag for transient buffer B RAM" "No error,Error"
|
|
eventfld.long 0x04 4. " SEFE ,ECC single bit error flag for transient buffer A RAM" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 3. " SEFD ,ECC single bit error flag for output buffer 2 RAM" "No error,Error"
|
|
eventfld.long 0x04 2. " SEFC ,ECC single bit error flag for output buffer 1 RAM" "No error,Error"
|
|
eventfld.long 0x04 1. " SEFB ,ECC single bit error flag for input buffer 2 RAM" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 0. " SEFB ,ECC single bit error flag for input buffer 1 RAM" "No error,Error"
|
|
line.long 0x08 "ECCTR,ECC Test Register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " RDECC ,Holds ECC bits when reading a RAM location"
|
|
hexmask.long.byte 0x08 0.--6. 1. " WRECC ,ECC bits to be written in ECC location when writing to a RAM location"
|
|
line.long 0x0C "SBESR,Single Bit Error Status Register"
|
|
eventfld.long 0x0C 31. " SBE ,ECC single bit error" "No error,Error"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " FMB ,Faulty message buffer"
|
|
eventfld.long 0x0C 6. " MFMB ,Multiple message buffers with ECC single bit error fault detected" "No additional buffer,Additional buffer"
|
|
newline
|
|
eventfld.long 0x0C 5. " FMBD ,Message buffer with ECC single bit error fault detected" "No faulty buffer,Faulty buffer"
|
|
eventfld.long 0x0C 4. " STBF2 ,ECC single bit error in transient buffer RAM B" "No error,Error"
|
|
eventfld.long 0x0C 3. " STBF1 ,ECC single bit error in transient buffer RAM A" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 2. " SMR ,ECC single bit error in message RAM" "No error,Error"
|
|
eventfld.long 0x0C 1. " SOBF ,ECC single bit error in output buffer RAM 1 2" "No error,Error"
|
|
eventfld.long 0x0C 0. " SIBF ,ECC single bit error in input buffer RAM 1 2" "No error,Error"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TEST1,Test Register 1"
|
|
sif (cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x00 28.--31. " CERB ,Coding error report channel B" "No coding,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
|
|
rbitfld.long 0x00 24.--27. " CERA ,Coding error report channel A" "No coding,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
|
|
else
|
|
bitfld.long 0x00 28.--31. " CERB ,Coding error report channel B" "No coding,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
|
|
bitfld.long 0x00 24.--27. " CERA ,Coding error report channel A" "No coding,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
|
|
endif
|
|
bitfld.long 0x00 21. " TXENB ,Control of channel B transmit enable pin (txen2)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " TXENA ,Control of channel A transmit enable pin (txen1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TXB ,Control of channel B transmit pin (txd2)" "0,1"
|
|
bitfld.long 0x00 18. " TXA ,Control of channel A transmit pin (txd1)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " RXB ,Monitor channel B receive pin (rxd2)" "0,1"
|
|
bitfld.long 0x00 16. " RXA ,Monitor channel A receive pin (rxd1)" "0,1"
|
|
bitfld.long 0x00 9. " AOB ,Activity on B" "No activity,Activity"
|
|
newline
|
|
bitfld.long 0x00 8. " AOA ,Activity on A" "No activity,Activity"
|
|
bitfld.long 0x00 4.--5. " TMC ,Test mode control" "Normal,RAM,I/O,?..."
|
|
bitfld.long 0x00 1. " ELBE ,External loop back enable" "Internal,External"
|
|
newline
|
|
bitfld.long 0x00 0. " WRTEN ,Write test register enable" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(ad:0xFFF7C800+0x10))&0x01)==0x01)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x0 "TEST2,Test Register 2"
|
|
bitfld.long 0x00 15. " RDPB ,Read parity bit" "0,1"
|
|
bitfld.long 0x00 14. " WRPB ,Write parity bit" "0,1"
|
|
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0000 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBR1,IBR2,OBR1,OBR2,TBR,TBR2,MBR,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEST2,Test Register 2"
|
|
bitfld.long 0x00 15. " RDPB ,Read parity bit" "0,1"
|
|
bitfld.long 0x00 14. " WRPB ,Write parity bit" "0,1"
|
|
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0000 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBR1,IBR2,OBR1,OBR2,TBR,TBR2,MBR,?.."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7C800+0x10))&0x01)==0x04)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x0 "TR2,Test Register 2"
|
|
bitfld.long 0x00 15. " RDPB ,Read parity bit" "No parity,Parity"
|
|
bitfld.long 0x00 14. " WRPB ,Write parity bit" "No parity,Parity"
|
|
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0400 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBF1,IBF2,OBF1,OBF2,TBF1,TBF2,MBF,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TR2,Test Register 2"
|
|
bitfld.long 0x00 15. " RDPB ,Read parity bit" "No parity,Parity"
|
|
bitfld.long 0x00 14. " WRPB ,Write parity bit" "No parity,Parity"
|
|
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0400 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBF1,IBF2,OBF1,OBF2,TBF1,TBF2,MBF,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCK,Lock Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TMK ,Test mode key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK ,Configuration lock key"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "LCK,Lock register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TMK ,Test mode key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK ,Configuration lock key"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Registers"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "EIR,Error Interrupt Register"
|
|
eventfld.long 0x00 26. " TABB ,Transmission across boundary channel B" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " LTVB ,Latest transmit violation channel B" "No violation,Violation"
|
|
eventfld.long 0x00 24. " EDB ,Error detected on channel B" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 18. " TABA ,Transmission across boundary channel A" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " LTVA ,Latest transmit violation channel A" "No violation,Violation"
|
|
eventfld.long 0x00 16. " EDA ,Error detected on channel A" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " MHF ,Message handler constraints flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " IOBA ,Illegal output buffer access" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " IIBA ,Illegal input buffer access" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 8. " EFA ,Empty FIFO access" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RFO ,Receive FIFO overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 6. " PERR ,Parity error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " CCL ,CHI Command locked" "Not locked,Locked"
|
|
eventfld.long 0x00 4. " CCF ,Clock correction failure" "Successful,Failed"
|
|
eventfld.long 0x00 3. " SFO ,SYNC frame overflow" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 2. " SFBM ,SYNC frames below minimum" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " CNA ,Command not accepted" "Accepted,Not accepted"
|
|
eventfld.long 0x00 0. " PEMC ,POC error mode changed" "Not changed,Changed"
|
|
line.long 0x04 "SIR,Status Interrupt Register"
|
|
eventfld.long 0x04 25. " MTSB ,MTS received on channel B" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " WUPB ,Wakeup pattern channel B" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " MTSA ,MTS received on channel A" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 16. " WUPA ,Wakeup pattern channel A" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " SDS ,Start of dynamic segment" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " MBSI ,Message buffer status interrupt request" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " SUCS ,Startup completed successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " SWE ,Stop watch event" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " TOBC ,Transfer output buffer completed" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 10. " TIBC ,Transfer input buffer completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " TI1 ,Timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " TI0 ,Timer interrupt 0" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 7. " NMVC ,Network management vector changed" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " RFCL ,Receive FIFO critical level" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " RFNE ,Receive FIFO not empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 4. " RXI ,Receive service request" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " TXI ,Transmit service request" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " CYCS ,Cycle start service request" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x04 1. " CAS ,Collision avoidance symbol" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x04 1. " CAS ,Collision avoidance symbol" "No interrupt,Interrupt"
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x04 0. " WST ,Wakeup status" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x04 0. " WST ,Wakeup status" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x08 "EILS,Error Interrupt Line Select Register"
|
|
bitfld.long 0x08 26. " TABBL ,Transmission across boundary channel B interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 25. " LTVBL ,Latest transmit violation channel B interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 24. " EDBL ,Error detected on channel B interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x08 18. " TABAL ,Transmission across boundary channel A interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 17. " LTVAL ,Latest transmit violation channel A interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 16. " EDAL ,Error detected on channel A interrupt Line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x08 11. " MHFL ,Message handler constrains flag interrupt Line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 10. " IOBAL ,Illegal output buffer access interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 9. " IIBAL ,Illegal Input Buffer Access Interrupt Line" "CC_int0,CC_int1"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 8. " EFAL ,Empty FIFO Access Interrupt Line" "CC_int0,CC_int1"
|
|
else
|
|
bitfld.long 0x08 8. " EVAL ,Empty FIFO Access Interrupt Line" "CC_int0,CC_int1"
|
|
endif
|
|
bitfld.long 0x08 7. " RFOL ,Receive FIFO Overrun Interrupt Line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 6. " PERRL ,Parity error interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x08 5. " CCLL ,CHI command locked interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 4. " CCFL ,Clock correction failure interrupt Line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 3. " SFOL ,SYNC frame overflow interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x08 2. " SFBML ,SYNC frames below minimum interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 1. " CNAL ,Command not accepted interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x08 0. " PEMCL ,POC error mode changed interrupt line" "CC_int0,CC_int1"
|
|
line.long 0x0C "SILS,Status Interrupt Line Select Register"
|
|
bitfld.long 0x0C 25. " MTSBL ,Media access test symbol channel B interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 24. " WUPBL ,Wakeup pattern channel b interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 17. " MTSAL ,Media access test symbol channel A interrupt Line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 16. " WUPAL ,Wakeup pattern channel a interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 15. " SDSL ,Start of dynamic segment interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 14. " MBSIL ,Message buffer status interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 13. " SUCSL ,Startup completed successfully interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 12. " SWEL ,Stop watch event interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 11. " TOBCL ,Transfer output buffer completed interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 10. " TIBCL ,Transfer input buffer completed interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 9. " TI1L ,Timer interrupt 1 line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 8. " TI0L ,Timer interrupt 0 line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 7. " NMVCL ,Network management vector changed interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 6. " RFFL ,Receive FIFO full interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 5. " RFNEL ,Receive FIFO not empty interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 4. " RXIL ,Receive interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 3. " TXIL ,Transmit interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 2. " CYCSL ,Cycle start interrupt line" "CC_int0,CC_int1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CASL ,Collision avoidance symbol interrupt line" "CC_int0,CC_int1"
|
|
bitfld.long 0x0C 0. " WSTL ,Wakeup status interrupt line" "CC_int0,CC_int1"
|
|
line.long 0x10 "EIE_SET/CLR,Error Interrupt Enable Set/Reset Registers"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x14 26. " TABBE ,Transmission across boundary channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 25. 0x10 25. 0x14 25. " LTVBE ,Latest transmit violation channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x14 24. " EDBE ,Error detected on channel B interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 18. 0x10 18. 0x14 18. " TABAE ,Transmission across boundary channel A interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x14 17. " LTVAE ,Last transmit violation channel A interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x14 16. " EDAE ,Error detected on channel A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 11. 0x10 11. 0x14 11. " MHFE ,Message handler constraints flag interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x14 10. " IOBAE ,Illegal output buffer access interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x14 9. " IIBAE ,Illegal input buffer access interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 8. 0x10 8. 0x14 8. " EFAE ,Empty FIFO access interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " RFOE ,Receive FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " PERRE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " CCLE ,CHI Command locked interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " CCFE ,Clock correction failure interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " SFOE ,Sync frame overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " SFBME ,Sync frames below minimum interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " CNAE ,Command not accepted interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " PEMCE ,POC error mode changed PEMCE interrupt enable" "Disabled,Enabled"
|
|
group.long 0x038++0x03
|
|
line.long 0x00 "SIE_SET/CLR,Status Interrupt Enable Set/Reset Register"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " MTSBE ,MTS received on channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " WUPBE ,Wakeup pattern channel B interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " MTSAE ,MTS received on channel A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " WUPAE ,Wakeup pattern channel A interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SDSE ,Start of dynamic segment interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " MBSIE ,Message buffer status interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " SUCSE ,Startup completed successfully interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SWEE ,Stop watch event interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " TOBCE ,Transfer output buffer completed interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " TIBCE ,Transfer input buffer completed interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " TI1E ,Timer interrupt 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TI0E ,Timer interrupt 0 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " NMVCE ,Network management vector changed interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " RFCLE ,Receive FIFO full interrupt enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " RFFE ,Receive FIFO full interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " RFNEE ,Receive FIFO not empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " CYCSE ,Cycle start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " CASE ,Collision avoidance symbol interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " WSTE ,Wakeup status interrupt enable" "Disabled,Enabled"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0x00 0.--1. " EINT ,Enable interrupt line" "Disabled both,Int0 enabled,Int1 enabled,Enabled both"
|
|
line.long 0x04 "T0C,Timer 0 Configuration Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " T0MO ,Timer 0 macrotick offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " T0CC ,Timer 0 Cycle Code"
|
|
bitfld.long 0x04 1. " T0MS ,Timer 0 mode select" "Single-shot,Continuous"
|
|
newline
|
|
bitfld.long 0x04 0. " T0RC ,Timer 0 run control" "Halted,Running"
|
|
line.long 0x08 "T1C,Timer 1 Configuration Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " T1MC ,Timer 1 macrotick count"
|
|
bitfld.long 0x08 1. " T1MS ,Timer 1 mode select" "Single-shot,Continuous"
|
|
bitfld.long 0x08 0. " T1RC ,Timer 1 run control" "Halted,Running"
|
|
line.long 0x0C "STPW1,Stop Watch Register 1"
|
|
hexmask.long.word 0x0C 16.--29. 1. " SMTV ,Stop watch captured macrotick value"
|
|
hexmask.long.byte 0x0C 8.--13. 1. " SCCV ,Stop watch captured cycle counter value"
|
|
bitfld.long 0x0C 6. " EINT1 ,Enable interrupt 1 trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " EINT0 ,Enable interrupt 0 trigger" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " EETP ,Enable external trigger pin" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " SSWT ,Software stop watch trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " EDGE ,Stop watch trigger edge select" "Falling,Rising"
|
|
bitfld.long 0x0C 1. " SWMS ,Stop watch mode select" "Single-shot,Continuous"
|
|
bitfld.long 0x0C 0. " ESWT ,Enable stop watch trigger" "Disabled,Enabled"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x0 "STPW2,Stop Watch Register 2"
|
|
hexmask.long.word 0x00 16.--26. 1. " SSCVB ,Stop watch captured slot counter value channel B"
|
|
hexmask.long.word 0x00 0.--10. 1. " SSCVA ,Stop watch captured slot counter value channel A"
|
|
tree.end
|
|
tree "Communication Controller Control Registers"
|
|
group.long 0x80++0x1B
|
|
line.long 0x00 "SUCC1,SUC Configuration Register 1"
|
|
bitfld.long 0x00 27. " CCHB ,Connected to channel B" "Not connected,Connected"
|
|
bitfld.long 0x00 26. " CCHA ,Connected to channel A" "Not connected,Connected"
|
|
bitfld.long 0x00 25. " MTSB ,Select channel B for MTS transmission" "Not Selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 24. " MTSA ,Select channel A for MTS transmission" "Not Selected,Selected"
|
|
bitfld.long 0x00 23. " HCSE ,Halt due to clock sync error" "Not halted,Halted"
|
|
bitfld.long 0x00 22. " TSM ,Transmission slot mode" "All,Single"
|
|
newline
|
|
bitfld.long 0x00 21. " WUCS ,Wakeup channel select" "Channel A,Channel B"
|
|
bitfld.long 0x00 16.--20. " PTA ,Passive to actives" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11.--15. " CSA ,Cold start attempts" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 9. " TXSY ,Transmit sync frame in key slots" "Not used,Used"
|
|
bitfld.long 0x00 8. " TXST ,Transmit startup frame in key slots" "Not used,Used"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 7. " PBSY ,POC busy flag" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " CMD ,CHI command vector" "Not accepted,CONFIG,READY,WAKEUP,RUN,ALL_SLOTS,HALT,FREEZE,SEND_MTS,ALLOW_COLDSTART,RESET_STATUS_INDICATORS,MONITOR_MODE,CLEAR_RAMS,,,LOOPBACK MODE"
|
|
else
|
|
bitfld.long 0x00 7. " PBSY ,POC busy flag" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " CMD ,CHI command vector" "Disabled,CONFIG,READY,WAKEUP,RUN,ALL_SLOTS,HALT,FREEZE,SEND_MTS,ALLOW_COLDSTART,RESET_STATUS_INDICATORS,MONITOR_MODE,CLEAR_RAMS,,,LOOPBACK MODE"
|
|
endif
|
|
line.long 0x04 "SUCC2,SUC Configuration Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 24.--27. " LTN ,Listen timeout noises" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 24.--27. " LTN ,Listen timeout noises" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
endif
|
|
hexmask.long.tbyte 0x04 0.--20. 1. " LT ,Listen timeouts"
|
|
line.long 0x08 "SUCC3,SUC Configuration Register 3"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 4.--7. " WCF ,Maximum without clock correction fatal" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " WCP ,Maximum without clock correction passives" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x08 4.--7. " WCF ,Maximum without clock correction fatal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " WCP ,Maximum without clock correction passives" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0C "NEMC,NEM Configuration Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x0C 0.--3. " NML ,Network management vector length" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
else
|
|
bitfld.long 0x0C 0.--3. " NML ,Network management vector length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x10 "PRTC1,PRT Configuration Register 1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x10 26.--31. " RWP ,Repetitions of TX wakeup patterns" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x10 26.--31. " RWP ,Repetitions of TX wakeup patterns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hexmask.long.word 0x10 16.--24. 1. " RXW ,Wakeup symbol receive window lengths"
|
|
bitfld.long 0x10 14.--15. " BRP ,Baud rate prescaler" "10 Mbps,5 Mbps,2.5 Mbps,2.5 Mbps"
|
|
newline
|
|
bitfld.long 0x10 12.--13. " SPP ,Strobe point positions" "5,4,6,5"
|
|
hexmask.long.byte 0x10 4.--10. 1. " CASM ,Collision avoidance symbol max"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x10 0.--3. " TSST ,Transmission start sequence transmitters" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x10 0.--3. " TSST ,Transmission start sequence transmitters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x14 "PRTC2,PRT Configuration Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x14 24.--29. " TXL ,Wakeup symbol transmit low" ",,,,,,,,,,,,,,,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,?..."
|
|
else
|
|
bitfld.long 0x14 24.--29. " TXL ,Wakeup symbol transmit low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
hexmask.long.byte 0x14 16.--23. 1. " TXI ,Wakeup symbol transmit idle"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x14 8.--13. " RXL ,Wakeup symbol receive low" ",,,,,,,,,,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,?..."
|
|
newline
|
|
bitfld.long 0x14 0.--5. " RXI ,Wakeup symbol receive idle" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,?..."
|
|
else
|
|
bitfld.long 0x14 8.--13. " RXL ,Wakeup symbol receive low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " RXI ,Wakeup symbol receive idle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
line.long 0x18 "MHDC,MHD Configuration Register"
|
|
hexmask.long.word 0x18 16.--28. 1. " SLT ,Start of latest transmit"
|
|
hexmask.long.byte 0x18 0.--6. 1. " SFDL ,Static frame data length"
|
|
group.long 0xA0++0x2B
|
|
line.long 0x00 "GTUC1,GTU Configuration Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " UT ,Microtick per cycles"
|
|
line.long 0x04 "GTUC2,GTU Configuration Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 16.--19. " SNM ,Sync node max" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 16.--19. " SNM ,Sync node max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
hexmask.long.word 0x04 0.--13. 1. " MPC ,Macrotick per cycles"
|
|
line.long 0x08 "GTUC3,GTU Configuration Register 3"
|
|
hexmask.long.byte 0x08 24.--30. 1. " MIOB ,Macrotick initial offset channel B"
|
|
hexmask.long.byte 0x08 16.--22. 1. " MIOA ,Macrotick initial offset channel A"
|
|
hexmask.long.byte 0x08 8.--15. 1. " UIOB ,Microtick initial offset channel B"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " UIOA ,Microtick initial offset channel A"
|
|
line.long 0x0C "GTUC4,GTU Configuration Register 4"
|
|
hexmask.long.word 0x0C 16.--29. 1. " OCS ,Offset correction starts"
|
|
hexmask.long.word 0x0C 0.--13. 1. " NIT ,Network idle time starts"
|
|
line.long 0x10 "GTUC5,GTU Configuration Register 5"
|
|
hexmask.long.byte 0x10 24.--31. 1. " DEC ,Decoding corrections"
|
|
bitfld.long 0x10 16.--20. " CDD ,Cluster drift damping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DCB ,Delay compensation channel B"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCA ,Delay compensation channel A"
|
|
line.long 0x14 "GTUC6,GTU Configuration Register 6"
|
|
hexmask.long.word 0x14 16.--26. 1. " MOD ,Maximum oscillator drift"
|
|
hexmask.long.word 0x14 0.--10. 1. " ASR ,Accepted startup range"
|
|
line.long 0x18 "GTUC7,GTU Configuration Register 7"
|
|
hexmask.long.word 0x18 16.--25. 1. " NSS ,Number of static slots"
|
|
hexmask.long.word 0x18 0.--9. 1. " SSL ,Static slot length"
|
|
line.long 0x1C "GTUC8,GTU Configuration Register 8"
|
|
hexmask.long.word 0x1C 16.--28. 1. " NMS ,Number of minislots"
|
|
bitfld.long 0x1C 0.--5. " MSL ,Minislot length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x20 "GTUC9,GTU Configuration Register 9"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x20 16.--17. " DSI ,Dynamic slot idle phase" "0,1,2,?..."
|
|
bitfld.long 0x20 8.--12. " MAPO ,Minislot action point offset" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--5. " APO ,Action point offset" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x20 16.--17. " DSI ,Dynamic slot idle phase" "0,1,2,3"
|
|
bitfld.long 0x20 8.--12. " MAPO ,Minislot action point offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--5. " APO ,Action point offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
line.long 0x24 "GTUC10,GTU Configuration Register 10"
|
|
hexmask.long.word 0x24 16.--26. 1. " MRC ,Maximum rate correction"
|
|
hexmask.long.word 0x24 0.--13. 1. " MOC ,Maximum offset correction"
|
|
line.long 0x28 "GTUC11,GTU Configuration Register 11"
|
|
bitfld.long 0x28 24.--26. " ERC ,External rate correction" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 16.--18. " EOC ,External offset correction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x28 8.--9. " ERCC ,External offset correction" "No correction,No correction,Subtracted from calc. rate correction,Added to calc. rate correction"
|
|
newline
|
|
bitfld.long 0x28 0.--1. " EOCC ,External offset correction control" "No correction,No correction,Subtracted from calc. rate correction,Added to calc. rate correction"
|
|
tree.end
|
|
tree "Communication Controller Status Registers"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CCSV,Communication Controller Status Vector Register"
|
|
bitfld.long 0x00 24.--29. " PSL ,POC status log" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19.--23. " RCA ,Remaining coldstart attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " WSV ,Wakeup status" "UNDEFINED,RECEIVED_HEADER,RECEIVED_WUP,COLLISION_HEADER,COLLISION_WUP,COLLISION_UNKNOWN,TRANSMITTED,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " CSI ,Cold start inhibit" "No,Yes"
|
|
bitfld.long 0x00 13. " CSAI ,Coldstart abort indicator flag" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " CSNI ,Coldstart noise indicator flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " SLM ,Slot mode flag" "SINGLE,,ALL_PENDING,ALL"
|
|
bitfld.long 0x00 7. " HRQ ,Halt request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " FSI ,Freeze status indicator flag" "Not Frozen,Frozen"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " POCS ,Protocol operation control status flag" "DEFAULT_CONFIG,READY,NORMAL_ACTIVE,NORMAL_PASSIVE,HALT,MONITOR_MODE,,,,,,,,LOOPBACK MODE,,CONFIG,WAKEUP_STANDBY,WAKEUP_LISTEN,WAKEUP_SEND,WAKEUP_DETECT,,,,,,,,,,,,,STARTUP_PREPARE,COLDSTART_LISTEN,COLDSTART_COLLISION_RESOLUTION,COLDSTART_CONSISTENCY_CHECK,COLDSTART_GAP,COLDSTART_JOIN,INTEGRATION_COLDSTART_CHECK,INTEGRATION_LISTEN,INTEGRATION_CONSISTENCY_CHECK,INITIALIZE_SCHEDULE,ABORT_STARTUP,?..."
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CCSV,Communication Controller Status Vector Register"
|
|
bitfld.long 0x00 24.--29. " PSL ,POC status log" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19.--23. " RCA ,Remaining coldstart attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " WSV ,Wakeup status" "UNDEFINED,RECEIVED_HEADER,RECEIVED_WUP,COLLISION_HEADER,COLLISION_WUP,COLLISION_UNKNOWN,TRANSMITTED,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " CSI ,Cold start inhibit flag" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " CSAI ,Coldstart abort indicator flag" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " CSNI ,Coldstart noise indicator flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " SLM ,Slot mode flag" "SINGLE,,ALL_PENDING,ALL"
|
|
bitfld.long 0x00 7. " HRQ ,Halt request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " FSI ,Freeze status indicator flag" "Not Frozen,Frozen"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " POCS ,Protocol operation control status flag" "DEFAULT_CONFIG,READY,NORMAL_ACTIVE,NORMAL_PASSIVE,HALT,MONITOR_MODE,,,,,,,,,,,,,,,LOOPBACK MODE,,,CONFIG,WAKEUP_STANDBY,WAKEUP_LISTEN,WAKEUP_SEND,WAKEUP_DETECT,,,,,,,,,,,,,,,,,,,,,,,,,STARTUP_PREPARE,COLDSTART_LISTEN,COLDSTART_COLLISION_RESOLUTION,COLDSTART_CONSISTENCY_CHECK,COLDSTART_GAP,COLDSTART_JOIN,INTEGRATION_COLDSTART_CHECK,INTEGRATION_LISTEN,INTEGRATION_CONSISTENCY_CHECK,INITIALIZE_SCHEDULE,ABORT_STARTUP,?..."
|
|
endif
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CCEV,Communication Controller Error Vector Register"
|
|
bitfld.long 0x00 8.--12. " PTAC ,Passive to active count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. " ERRM ,Error mode flag" "ACTIVE,PASSIVE,COMM_HALT,?..."
|
|
bitfld.long 0x00 0.--3. " CCFC ,Clock correction failed counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x110++0x0F
|
|
line.long 0x00 "SCV,Slot Counter Value Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " SCCB ,Slot counter channel B"
|
|
hexmask.long.word 0x00 0.--10. 1. " SCCA ,Slot counter channel A"
|
|
line.long 0x04 "MTCCV,Macrotick And Cycle Counter Register"
|
|
bitfld.long 0x04 16.--21. " CCV ,Cycle counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--13. 1. " MTV ,Macrotick value"
|
|
line.long 0x08 "RCV,Rate Correction Value Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " RCV ,Rate correction value"
|
|
line.long 0x0C "OCV,Offset Correction Value Register"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " OCV ,Offset correction value"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFS,Sync Frame Status Register"
|
|
bitfld.long 0x00 19. " RCLR ,Rate correction limit reached flag" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " MRCS ,Missing rate correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 17. " OCLR ,Offset correction limit reached flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x00 16. " MOCS ,Missing offset correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 12.--15. " VSBO ,Valid sync frames channel B odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSBE ,Valid sync frames channel B even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " VSAO ,Valid sync frames channel A odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " VSAE ,Valid sync frames channel A even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7C800+0x80))&0xC000000)==0xC000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFS,Sync Frame Status Register"
|
|
bitfld.long 0x00 19. " RCLR ,Rate correction limit reached flag" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " MRCS ,Missing rate correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 17. " OCLR ,Offset correction limit reached flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x00 16. " MOCS ,Missing offset correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 12.--15. " VSBO ,Valid sync frames channel B odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSBE ,Valid sync frames channel B even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " VSAO ,Valid sync frames channel A odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " VSAE ,Valid sync frames channel A even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l.be(ad:0xFFF7C800+0x80))&0xC000000)==0x8000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFS,Sync Frame Status Register"
|
|
bitfld.long 0x00 19. " RCLR ,Rate correction limit reached flag" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " MRCS ,Missing rate correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 17. " OCLR ,Offset correction limit reached flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x00 16. " MOCS ,Missing offset correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 12.--15. " VSBO ,Valid sync frames channel B odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSBE ,Valid sync frames channel B even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l.be(ad:0xFFF7C800+0x80))&0xC000000)==0x4000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFSR,Sync Frame Status Register"
|
|
bitfld.long 0x00 19. " RCLR ,Rate correction limit reached flag" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " MRCS ,Missing rate correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 17. " OCLR ,Offset correction limit reached flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x00 16. " MOCS ,Missing offset correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 4.--7. " VSAO ,Valid sync frames channel A odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " VSAE ,Valid sync frames channel A even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFS,Sync Frame Status Register"
|
|
bitfld.long 0x00 19. " RCLR ,Rate correction limit reached flag" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " MRCS ,Missing rate correction signal flag" "Not missing,Missing"
|
|
bitfld.long 0x00 17. " OCLR ,Offset correction limit reached flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x00 16. " MOCS ,Missing offset correction signal flag" "Not missing,Missing"
|
|
endif
|
|
endif
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SWNIT,Symbol Window And NIT Status Register"
|
|
bitfld.long 0x00 11. " SBNB ,Slot boundary violation during NIT channel B flag" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " SENB ,Syntax error during NIT channel B flag" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SBNA ,Slot boundary violation during NIT channel A flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 8. " SENA ,Syntax error during NIT channel A flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " MTSB ,MTS received on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 6. " MTSA ,MTS received on channel A flag" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 5. " TCSB ,Transmission conflict in symbol window channel B flag" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " SBSB ,Slot boundary violation in symbol window channel B flag" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " SESB ,Syntax error in symbol window channel B flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 2. " TCSA ,Transmission conflict in symbol window channel A flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " SBSA ,Slot boundary violation in symbol window channel A flag" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SESA ,Syntax error in symbol window channel A flag" "Not detected,Detected"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ACS,Aggregated Channel Status Register"
|
|
eventfld.long 0x00 12. " SBVB ,Slot boundary violation on channel B flag" "Not observed,Observed"
|
|
eventfld.long 0x00 11. " CIB ,Communication indicator channel B flag" "Not valid,Valid"
|
|
eventfld.long 0x00 10. " CEDB ,Content error detected on channel B flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 9. " SEDB ,Syntax error detected on channel B flag" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " VFRB ,Valid frame received on channel B flag" "Not valid,Valid"
|
|
eventfld.long 0x00 4. " SBVA ,Slot boundary violation on channel A flag" "Not observed,Observed"
|
|
newline
|
|
eventfld.long 0x00 3. " CIA ,Communication indicator channel A flag" "Not valid,Valid"
|
|
eventfld.long 0x00 2. " CEDA ,Content error detected on channel A flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " SEDA ,Syntax error detected on channel A flag" "Not observed,Observed"
|
|
newline
|
|
eventfld.long 0x00 0. " VFRA ,Valid frame received on channel A flag" "Not valid,Valid"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "ESID1,Even Sync ID [1]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "ESID2,Even Sync ID [2]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "ESID3,Even Sync ID [3]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ESID4,Even Sync ID [4]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ESID5,Even Sync ID [5]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "ESID6,Even Sync ID [6]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "ESID7,Even Sync ID [7]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "ESID8,Even Sync ID [8]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "ESID9,Even Sync ID [9]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "ESID10,Even Sync ID [10]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ESID11,Even Sync ID [11]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "ESID12,Even Sync ID [12]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "ESID13,Even Sync ID [13]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "ESID14,Even Sync ID [14]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "ESID15,Even Sync ID [15]"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received / configured even sync ID on channel A flag" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "OSID1,Odd Sync ID [1]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "OSID2,Odd Sync ID [2]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "OSID3,Odd Sync ID [3]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "OSID4,Odd Sync ID [4]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "OSID5,Odd Sync ID [5]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "OSID6,Odd Sync ID [6]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "OSID7,Odd Sync ID [7]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "OSID8,Odd Sync ID [8]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "OSID9,Odd Sync ID [9]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "OSID10,Odd Sync ID [10]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "OSID11,Odd Sync ID [11]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "OSID12,Odd Sync ID [12]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "OSID13,Odd Sync ID [13]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "OSID14,Odd Sync ID [14]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "OSID15,Odd Sync ID [15]"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B flag" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "NMV1,Network Management Vector [1]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NMIDATA3 ,Network management vector data 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NMIDATA2 ,Network management vector data 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMIDATA1 ,Network management vector data 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " NMIDATA0 ,Network management vector data 0"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "NMV2,Network Management Vector [2]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NMIDATA7 ,Network management vector data 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NMIDATA6 ,Network management vector data 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMIDATA5 ,Network management vector data 5"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " NMIDATA4 ,Network management vector data 4"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "NMV3,Network Management Vector [3]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NMIDATA11 ,Network management vector data 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NMIDATA10 ,Network management vector data 10"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMIDATA9 ,Network management vector data 9"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " NMIDATA8 ,Network management vector data 8"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "ESID1R,Even Sync ID [1] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "ESID2R,Even Sync ID [2] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "ESID3R,Even Sync ID [3] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ESID4R,Even Sync ID [4] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ESID5R,Even Sync ID [5] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "ESID6R,Even Sync ID [6] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "ESID7R,Even Sync ID [7] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "ESID8R,Even Sync ID [8] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "ESID9R,Even Sync ID [9] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "ESID10R,Even Sync ID [10] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ESID11R,Even Sync ID [11] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "ESID12R,Even Sync ID [12] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "ESID13R,Even Sync ID [13] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "ESID14R,Even Sync ID [14] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "ESID15R,Even Sync ID [15] Register"
|
|
bitfld.long 0x00 15. " RXEB ,Received even sync ID on channel B" "Not received,Received"
|
|
bitfld.long 0x00 14. " RXEA ,Received even sync ID on channel A" "Not received,Received"
|
|
hexmask.long.word 0x00 0.--9. 1. " EID[9:0] ,Even sync ID"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "OSID1R,Odd Sync ID [1] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "OSID2R,Odd Sync ID [2] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "OSID3R,Odd Sync ID [3] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "OSID4R,Odd Sync ID [4] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "OSID5R,Odd Sync ID [5] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "OSID6R,Odd Sync ID [6] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "OSID7R,Odd Sync ID [7] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "OSID8R,Odd Sync ID [8] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "OSID9R,Odd Sync ID [9] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "OSID10R,Odd Sync ID [10] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "OSID11R,Odd Sync ID [11] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "OSID12R,Odd Sync ID [12] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "OSID13R,Odd Sync ID [13] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "OSID14R,Odd Sync ID [14] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "OSID15R,Odd Sync ID [15] Register"
|
|
bitfld.long 0x00 15. " RXOB ,Received / configured odd sync ID on channel B" "No sync,Sync"
|
|
bitfld.long 0x00 14. " RXOA ,Received / configured odd sync ID on channel A flag" "No sync,Sync"
|
|
hexmask.long.word 0x00 0.--9. 1. " OID[9:0] ,Odd sync ID"
|
|
rgroup.long 0x1B0++0x0B
|
|
line.long 0x00 "NMV1R,Network Management Vector 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NMIDATA3 ,Network management vector data 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NMIDATA2 ,Network management vector data 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NMIDATA1 ,Network management vector data 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " NMIDATA0 ,Network management vector data 0"
|
|
line.long 0x04 "NMV2R,Network Management Vector 2 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " NMIDATA7 ,Network management vector data 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NMIDATA6 ,Network management vector data 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " NMIDATA5 ,Network management vector data 5"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " NMIDATA4 ,Network management vector data 4"
|
|
line.long 0x08 "NMV3R,Network Management Vector 3 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " NMIDATA11 ,Network management vector data 11"
|
|
hexmask.long.byte 0x08 16.--23. 1. " NMIDATA10 ,Network management vector data 10"
|
|
hexmask.long.byte 0x08 8.--15. 1. " NMIDATA9 ,Network management vector data 9"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " NMIDATA8 ,Network management vector data 8"
|
|
endif
|
|
tree.end
|
|
tree "Message Buffer Control Registers"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
if ((((per.l.be(ad:0xFFF7C800+0x100))&0x3F)==0x00)||(((per.l.be(ad:0xFFF7C800+0x100))&0x3F)==0x0F))
|
|
group.long 0x0300++0x0F
|
|
line.long 0x00 "MRC,Message RAM Configuration Register"
|
|
bitfld.long 0x00 26. " SPLM ,Sync frame payload multiplex" "Buffer 0,Buffers 0 & 1"
|
|
bitfld.long 0x00 24.--25. " SEC ,Secure buffers reconfiguration of message status" "Enabled with numbers < FFBh,Locked with numbers <FDB and FFB,All message buffers locked,All message buffers locked/transmission with numbers FDB disabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last configured buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First buffer of FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First dynamic buffer"
|
|
line.long 0x04 "FRF,FIFO Rejection Filter Register"
|
|
bitfld.long 0x04 24. " RNF ,Reject null frames" "Not rejected,Rejected"
|
|
bitfld.long 0x04 23. " RSS ,Reject in static segment" "Not rejected,Rejected"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle counter filter"
|
|
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID filter"
|
|
newline
|
|
bitfld.long 0x04 0.--1. " CH ,Channel filter" "Both,Channel B,Channel A,No reception"
|
|
line.long 0x08 "FRFM,FIFO Rejection Filter Mask Register"
|
|
bitfld.long 0x08 12. " MFID12 ,Mask frame ID filter 12" "0,1"
|
|
bitfld.long 0x08 11. " MFID11 ,Mask frame ID filter 11" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. " MFID10 ,Mask frame ID filter 10" "0,1"
|
|
bitfld.long 0x08 9. " MFID9 ,Mask frame ID filter 9" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. " MFID8 ,Mask frame ID filter 8" "0,1"
|
|
bitfld.long 0x08 7. " MFID7 ,Mask frame ID filter 7" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " MFID6 ,Mask frame ID filter 6" "0,1"
|
|
bitfld.long 0x08 5. " MFID5 ,Mask frame ID filter 5" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. " MFID4 ,Mask frame ID filter 4" "0,1"
|
|
bitfld.long 0x08 3. " MFID3 ,Mask frame ID filter 3" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. " MFID2 ,Mask frame ID filter 2" "0,1"
|
|
line.long 0x0C "FCL,FIFO Critical Level Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical level"
|
|
else
|
|
rgroup.long 0x0300++0x0F
|
|
line.long 0x00 "MRC,Message RAM Configuration Register"
|
|
bitfld.long 0x00 26. " SPLM ,Sync frame payload multiplex" "Buffer 0,Buffers 0 & 1"
|
|
bitfld.long 0x00 24.--25. " SEC ,Secure buffers reconfiguration of message status" "Enabled with numbers < FFBh,Locked with numbers <FDB and FFB,All message buffers locked,All message buffers locked/transmission with numbers FDB disabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last configured buffer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First buffer of FIFO"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First dynamic buffer"
|
|
line.long 0x04 "FRF,FIFO Rejection Filter Register"
|
|
bitfld.long 0x04 24. " RNF ,Reject null frames" "Not rejected,Rejected"
|
|
bitfld.long 0x04 23. " RSS ,Reject in static segment" "Not rejected,Rejected"
|
|
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle counter filter"
|
|
newline
|
|
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID filter"
|
|
bitfld.long 0x04 0.--1. " CH ,Channel filter" "Both,Channel B,Channel A,No reception"
|
|
line.long 0x08 "FRFM,FIFO Rejection Filter Mask Register"
|
|
bitfld.long 0x08 12. " MFID12 ,Mask frame ID filter 12" "0,1"
|
|
bitfld.long 0x08 11. " MFID11 ,Mask frame ID filter 11" "0,1"
|
|
bitfld.long 0x08 10. " MFID10 ,Mask frame ID filter 10" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " MFID9 ,Mask frame ID filter 9" "0,1"
|
|
bitfld.long 0x08 8. " MFID8 ,Mask frame ID filter 8" "0,1"
|
|
bitfld.long 0x08 7. " MFID7 ,Mask frame ID filter 7" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " MFID6 ,Mask frame ID filter 6" "0,1"
|
|
bitfld.long 0x08 5. " MFID5 ,Mask frame ID filter 5" "0,1"
|
|
bitfld.long 0x08 4. " MFID4 ,Mask frame ID filter 4" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " MFID3 ,Mask frame ID filter 3" "0,1"
|
|
bitfld.long 0x08 2. " MFID2 ,Mask frame ID filter 2" "0,1"
|
|
line.long 0x0C "FCLR,FIFO Critical Level Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical level"
|
|
endif
|
|
else
|
|
group.long 0x0300++0x0F
|
|
line.long 0x00 "MRC,Message RAM Configuration Register"
|
|
bitfld.long 0x00 26. " SPLM ,Sync frame payload multiplex" "Buffer 0,Buffers 0 & 1"
|
|
bitfld.long 0x00 24.--25. " SEC ,Secure buffers" "< FFB,< FDB & >= FFB,Locked,>= FDB"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last configured buffer"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First buffer of FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First dynamic buffer"
|
|
line.long 0x04 "FRF,FIFO Rejection Filter Register"
|
|
bitfld.long 0x04 24. " RNF ,Reject null frames" "Not rejected,Rejected"
|
|
bitfld.long 0x04 23. " RSS ,Reject in static segment" "Not rejected,Rejected"
|
|
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle counter filter"
|
|
newline
|
|
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID filter"
|
|
bitfld.long 0x04 0.--1. " CH ,Channel filter" "Both,Channel B,Channel A,No reception"
|
|
line.long 0x08 "FRFM,FIFO Rejection Filter Mask Register"
|
|
bitfld.long 0x08 12. " MFID10 ,Mask frame ID filter 10" "0,1"
|
|
bitfld.long 0x08 11. " MFID9 ,Mask frame ID filter 9" "0,1"
|
|
bitfld.long 0x08 10. " MFID8 ,Mask frame ID filter 8" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " MFID7 ,Mask frame ID filter 7" "0,1"
|
|
bitfld.long 0x08 8. " MFID6 ,Mask frame ID filter 6" "0,1"
|
|
bitfld.long 0x08 7. " MFID5 ,Mask frame ID filter 5" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " MFID4 ,Mask frame ID filter 4" "0,1"
|
|
bitfld.long 0x08 5. " MFID3 ,Mask frame ID filter 3" "0,1"
|
|
bitfld.long 0x08 4. " MFID2 ,Mask frame ID filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " MFID1 ,Mask frame ID filter 1" "0,1"
|
|
bitfld.long 0x08 2. " MFID0 ,Mask frame ID filter 0" "0,1"
|
|
line.long 0x0C "FCL,FIFO Critical Level Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical level"
|
|
endif
|
|
tree.end
|
|
tree "Message Buffer Status Registers"
|
|
group.long 0x0310++0x03
|
|
line.long 0x00 "MHS,Message Handler Status Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " MBU ,Message buffer updated"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MBT ,Message buffer transmitted"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FMB ,Faulty message buffer"
|
|
newline
|
|
sif (cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x00 7. " CRAM ,Clear all internal RAM's Flag" "Not executed,Executed"
|
|
else
|
|
bitfld.long 0x00 7. " CRAM ,Clear all internal RAM's Flag" "No execution,Execution"
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 6. " MFMB ,Multiple faulty message buffers detected flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " FMBD ,Faulty message buffer detected flag" "Not detected,Detected"
|
|
else
|
|
eventfld.long 0x00 6. " MFMB ,Multiple faulty message buffers detected flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " FMBD ,Faulty message buffer detected flag" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 4. " PTBF2 ,Parity error transient buffer RAM B Flag" "No error,Error"
|
|
eventfld.long 0x00 3. " PTBF1 ,Parity error transient buffer RAM A flag" "No error,Error"
|
|
eventfld.long 0x00 2. " PMR ,Parity error message RAM flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " POBF ,Parity error output buffer RAM 1 & 2 flag" "No error,Error"
|
|
eventfld.long 0x00 0. " PIBF ,Parity error input buffer RAM 1 & 2 flag" "No error,Error"
|
|
rgroup.long 0x0314++0x07
|
|
line.long 0x00 "LDTS,Last Dynamic Transmit Slot Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " LDTB ,Last dynamic transmission channel B"
|
|
hexmask.long.word 0x00 0.--10. 1. " LDTA ,Last dynamic transmission channel A"
|
|
line.long 0x04 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RFFL ,Receive FIFO fill level"
|
|
bitfld.long 0x04 2. " RFO ,Receive FIFO overrun flag" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " RFCL ,Receive FIFO critical level flag" "Not reached,Reached"
|
|
newline
|
|
bitfld.long 0x04 0. " RFNE ,Receive FIFO not empty flag" "Empty,Not empty"
|
|
group.long 0x031C++0x03
|
|
line.long 0x00 "MHDF,Message Handler Constraint Flags Register"
|
|
eventfld.long 0x00 8. " WAHP ,Write attempt to header partition flag" "Not attempted,Attempted"
|
|
eventfld.long 0x00 7. " TNSA ,Transmission not started channel A" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " TNSB ,Transmission not started channel B" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 5. " TBFB ,Transient buffer access failure B flag" "Not Failed,Failed"
|
|
eventfld.long 0x00 4. " TBFA ,Transient buffer access failure A flag" "Not Failed,Failed"
|
|
eventfld.long 0x00 3. " FNFB ,Find sequence not finished for channel B flag" "Not Found,Found"
|
|
newline
|
|
eventfld.long 0x00 2. " FNFA ,Find sequence not finished for channel A flag" "Not Found,Found"
|
|
eventfld.long 0x00 1. " SNUB ,Status not updated channel B flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " SNUA ,Status not updated channel A flag" "Not occurred,Occurred"
|
|
rgroup.long 0x0320++0x0F
|
|
line.long 0x00 "TXRQ1,Transmission Request 1 Register"
|
|
bitfld.long 0x00 31. " TXR31 ,Transmission request flag 31" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " TXR30 ,Transmission request flag 30" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " TXR29 ,Transmission request flag 29" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 28. " TXR28 ,Transmission request flag 28" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " TXR27 ,Transmission request flag 27" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " TXR26 ,Transmission request flag 26" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 25. " TXR25 ,Transmission request flag 25" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " TXR24 ,Transmission request flag 24" "Not requested,Requested"
|
|
bitfld.long 0x00 23. " TXR23 ,Transmission request flag 23" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 22. " TXR22 ,Transmission request flag 22" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " TXR21 ,Transmission request flag 21" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " TXR20 ,Transmission request flag 20" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 19. " TXR19 ,Transmission request flag 19" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " TXR18 ,Transmission request flag 18" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " TXR17 ,Transmission request flag 17" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 16. " TXR16 ,Transmission request flag 16" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " TXR15 ,Transmission request flag 15" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " TXR14 ,Transmission request flag 14" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 13. " TXR13 ,Transmission request flag 13" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " TXR12 ,Transmission request flag 12" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " TXR11 ,Transmission request flag 11" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 10. " TXR10 ,Transmission request flag 10" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " TXR9 ,Transmission request flag 9" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " TXR8 ,Transmission request flag 8" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " TXR7 ,Transmission request flag 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " TXR6 ,Transmission request flag 6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " TXR5 ,Transmission request flag 5" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 4. " TXR4 ,Transmission request flag 4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " TXR3 ,Transmission request flag 3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " TXR2 ,Transmission request flag 2" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " TXR1 ,Transmission request flag 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " TXR0 ,Transmission request flag 0" "Not requested,Requested"
|
|
line.long 0x04 "TXRQ2,FlexRay Transmission Request Register 2"
|
|
bitfld.long 0x04 31. " TXR63 ,Transmission request flag 63" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " TXR62 ,Transmission request flag 62" "Not requested,Requested"
|
|
bitfld.long 0x04 29. " TXR61 ,Transmission request flag 61" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 28. " TXR60 ,Transmission request flag 60" "Not requested,Requested"
|
|
bitfld.long 0x04 27. " TXR59 ,Transmission request flag 59" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " TXR58 ,Transmission request flag 58" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " TXR57 ,Transmission request flag 57" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " TXR56 ,Transmission request flag 56" "Not requested,Requested"
|
|
bitfld.long 0x04 23. " TXR55 ,Transmission request flag 55" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 22. " TXR54 ,Transmission request flag 54" "Not requested,Requested"
|
|
bitfld.long 0x04 21. " TXR53 ,Transmission request flag 53" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " TXR52 ,Transmission request flag 52" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " TXR51 ,Transmission request flag 51" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " TXR50 ,Transmission request flag 50" "Not requested,Requested"
|
|
bitfld.long 0x04 17. " TXR49 ,Transmission request flag 49" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 16. " TXR48 ,Transmission request flag 48" "Not requested,Requested"
|
|
bitfld.long 0x04 15. " TXR47 ,Transmission request flag 47" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXR46 ,Transmission request flag 46" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " TXR45 ,Transmission request flag 45" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXR44 ,Transmission request flag 44" "Not requested,Requested"
|
|
bitfld.long 0x04 11. " TXR43 ,Transmission request flag 43" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 10. " TXR42 ,Transmission request flag 42" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXR41 ,Transmission request flag 41" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXR40 ,Transmission request flag 40" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " TXR39 ,Transmission request flag 39" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXR38 ,Transmission request flag 38" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXR37 ,Transmission request flag 37" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 4. " TXR36 ,Transmission request flag 36" "Not requested,Requested"
|
|
bitfld.long 0x04 3. " TXR35 ,Transmission request flag 35" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXR34 ,Transmission request flag 34" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " TXR33 ,Transmission request flag 33" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXR32 ,Transmission request flag 32" "Not requested,Requested"
|
|
line.long 0x08 "TXRQ3,FlexRay Transmission Request Register 3"
|
|
bitfld.long 0x08 31. " TXR95 ,Transmission request flag 95" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " TXR94 ,Transmission request flag 94" "Not requested,Requested"
|
|
bitfld.long 0x08 29. " TXR93 ,Transmission request flag 93" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 28. " TXR92 ,Transmission request flag 92" "Not requested,Requested"
|
|
bitfld.long 0x08 27. " TXR91 ,Transmission request flag 91" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " TXR90 ,Transmission request flag 90" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " TXR89 ,Transmission request flag 89" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " TXR88 ,Transmission request flag 88" "Not requested,Requested"
|
|
bitfld.long 0x08 23. " TXR87 ,Transmission request flag 87" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 22. " TXR86 ,Transmission request flag 86" "Not requested,Requested"
|
|
bitfld.long 0x08 21. " TXR85 ,Transmission request flag 85" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " TXR84 ,Transmission request flag 84" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " TXR83 ,Transmission request flag 83" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " TXR82 ,Transmission request flag 82" "Not requested,Requested"
|
|
bitfld.long 0x08 17. " TXR81 ,Transmission request flag 81" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 16. " TXR80 ,Transmission request flag 80" "Not requested,Requested"
|
|
bitfld.long 0x08 15. " TXR79 ,Transmission request flag 79" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " TXR78 ,Transmission request flag 78" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " TXR77 ,Transmission request flag 77" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " TXR76 ,Transmission request flag 76" "Not requested,Requested"
|
|
bitfld.long 0x08 11. " TXR75 ,Transmission request flag 75" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 10. " TXR74 ,Transmission request flag 74" "Not requested,Requested"
|
|
bitfld.long 0x08 9. " TXR73 ,Transmission request flag 73" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " TXR72 ,Transmission request flag 72" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " TXR71 ,Transmission request flag 71" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " TXR70 ,Transmission request flag 70" "Not requested,Requested"
|
|
bitfld.long 0x08 5. " TXR69 ,Transmission request flag 69" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 4. " TXR68 ,Transmission request flag 68" "Not requested,Requested"
|
|
bitfld.long 0x08 3. " TXR67 ,Transmission request flag 67" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " TXR66 ,Transmission request flag 66" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " TXR65 ,Transmission request flag 65" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " TXR64 ,Transmission request flag 64" "Not ready,Ready"
|
|
line.long 0x0C "TXRQ4,FlexRay Transmission Request Register 4"
|
|
bitfld.long 0x0C 31. " TXR127 ,Transmission request flag 127" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " TXR126 ,Transmission request flag 126" "Not requested,Requested"
|
|
bitfld.long 0x0C 29. " TXR125 ,Transmission request flag 125" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 28. " TXR124 ,Transmission request flag 124" "Not requested,Requested"
|
|
bitfld.long 0x0C 27. " TXR123 ,Transmission request flag 123" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " TXR122 ,Transmission request flag 122" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " TXR121 ,Transmission request flag 121" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " TXR120 ,Transmission request flag 120" "Not requested,Requested"
|
|
bitfld.long 0x0C 23. " TXR119 ,Transmission request flag 119" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 22. " TXR118 ,Transmission request flag 118" "Not requested,Requested"
|
|
bitfld.long 0x0C 21. " TXR117 ,Transmission request flag 117" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " TXR116 ,Transmission request flag 116" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " TXR115 ,Transmission request flag 115" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " TXR114 ,Transmission request flag 114" "Not requested,Requested"
|
|
bitfld.long 0x0C 17. " TXR113 ,Transmission request flag 113" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 16. " TXR112 ,Transmission request flag 112" "Not requested,Requested"
|
|
bitfld.long 0x0C 15. " TXR111 ,Transmission request flag 111" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " TXR110 ,Transmission request flag 110" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " TXR109 ,Transmission request flag 109" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " TXR108 ,Transmission request flag 108" "Not requested,Requested"
|
|
bitfld.long 0x0C 11. " TXR107 ,Transmission request flag 107" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 10. " TXR106 ,Transmission request flag 106" "Not requested,Requested"
|
|
bitfld.long 0x0C 9. " TXR105 ,Transmission request flag 105" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " TXR104 ,Transmission request flag 104" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " TXR103 ,Transmission request flag 103" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " TXR102 ,Transmission request flag 102" "Not requested,Requested"
|
|
bitfld.long 0x0C 5. " TXR101 ,Transmission request flag 101" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 4. " TXR100 ,Transmission request flag 100" "Not requested,Requested"
|
|
bitfld.long 0x0C 3. " TXR99 ,Transmission request flag 99" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " TXR98 ,Transmission request flag 98" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " TXR97 ,Transmission request flag 97" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " TXR96 ,Transmission request flag 96" "Not requested,Requested"
|
|
rgroup.long 0x0330++0x0F
|
|
line.long 0x00 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x00 31. " ND31 ,New data flag 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " ND30 ,New data flag 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " ND29 ,New data flag 29" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 28. " ND28 ,New data flag 28" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " ND27 ,New data flag 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " ND26 ,New data flag 26" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 25. " ND25 ,New data flag 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " ND24 ,New data flag 24" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " ND23 ,New data flag 23" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 22. " ND22 ,New data flag 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " ND21 ,New data flag 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " ND20 ,New data flag 20" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 19. " ND19 ,New data flag 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " ND18 ,New data flag 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " ND17 ,New data flag 17" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 16. " ND16 ,New data flag 16" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " ND15 ,New data flag 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " ND14 ,New data flag 14" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 13. " ND13 ,New data flag 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " ND12 ,New data flag 12" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " ND11 ,New data flag 11" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 10. " ND10 ,New data flag 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " ND9 ,New data flag 9" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " ND8 ,New data flag 8" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " ND7 ,New data flag 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " ND6 ,New data flag 6" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " ND5 ,New data flag 5" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 4. " ND4 ,New data flag 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ND3 ,New data flag 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " ND2 ,New data flag 2" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " ND1 ,New data flag 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " ND0 ,New data flag 0" "Not detected,Detected"
|
|
line.long 0x04 "NDAT2,FlexRay New Data Register 2"
|
|
bitfld.long 0x04 31. " ND63 ,New data flag 63" "Not detected,Detected"
|
|
bitfld.long 0x04 30. " ND62 ,New data flag 62" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " ND61 ,New data flag 61" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 28. " ND60 ,New data flag 60" "Not detected,Detected"
|
|
bitfld.long 0x04 27. " ND59 ,New data flag 59" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " ND58 ,New data flag 58" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 25. " ND57 ,New data flag 57" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " ND56 ,New data flag 56" "Not detected,Detected"
|
|
bitfld.long 0x04 23. " ND55 ,New data flag 55" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 22. " ND54 ,New data flag 54" "Not detected,Detected"
|
|
bitfld.long 0x04 21. " ND53 ,New data flag 53" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " ND52 ,New data flag 52" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 19. " ND51 ,New data flag 51" "Not detected,Detected"
|
|
bitfld.long 0x04 18. " ND50 ,New data flag 50" "Not detected,Detected"
|
|
bitfld.long 0x04 17. " ND49 ,New data flag 49" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 16. " ND48 ,New data flag 48" "Not detected,Detected"
|
|
bitfld.long 0x04 15. " ND47 ,New data flag 47" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " ND46 ,New data flag 46" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 13. " ND45 ,New data flag 45" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " ND44 ,New data flag 44" "Not detected,Detected"
|
|
bitfld.long 0x04 11. " ND43 ,New data flag 43" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 10. " ND42 ,New data flag 42" "Not detected,Detected"
|
|
bitfld.long 0x04 9. " ND41 ,New data flag 41" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " ND40 ,New data flag 40" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 7. " ND39 ,New data flag 39" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " ND38 ,New data flag 38" "Not detected,Detected"
|
|
bitfld.long 0x04 5. " ND37 ,New data flag 37" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 4. " ND36 ,New data flag 36" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " ND35 ,New data flag 35" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " ND34 ,New data flag 34" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 1. " ND33 ,New data flag 33" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " ND32 ,New data flag 32" "Not detected,Detected"
|
|
line.long 0x08 "NDAT3,FlexRay New Data Register 3"
|
|
bitfld.long 0x08 31. " ND95 ,New data flag 95" "Not detected,Detected"
|
|
bitfld.long 0x08 30. " ND94 ,New data flag 94" "Not detected,Detected"
|
|
bitfld.long 0x08 29. " ND93 ,New data flag 93" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 28. " ND92 ,New data flag 92" "Not detected,Detected"
|
|
bitfld.long 0x08 27. " ND91 ,New data flag 91" "Not detected,Detected"
|
|
bitfld.long 0x08 26. " ND90 ,New data flag 90" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 25. " ND89 ,New data flag 89" "Not detected,Detected"
|
|
bitfld.long 0x08 24. " ND88 ,New data flag 88" "Not detected,Detected"
|
|
bitfld.long 0x08 23. " ND87 ,New data flag 87" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 22. " ND86 ,New data flag 86" "Not detected,Detected"
|
|
bitfld.long 0x08 21. " ND85 ,New data flag 85" "Not detected,Detected"
|
|
bitfld.long 0x08 20. " ND84 ,New data flag 84" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 19. " ND83 ,New data flag 83" "Not detected,Detected"
|
|
bitfld.long 0x08 18. " ND82 ,New data flag 82" "Not detected,Detected"
|
|
bitfld.long 0x08 17. " ND81 ,New data flag 81" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 16. " ND80 ,New data flag 80" "Not detected,Detected"
|
|
bitfld.long 0x08 15. " ND79 ,New data flag 79" "Not detected,Detected"
|
|
bitfld.long 0x08 14. " ND78 ,New data flag 78" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 13. " ND77 ,New data flag 77" "Not detected,Detected"
|
|
bitfld.long 0x08 12. " ND76 ,New data flag 76" "Not detected,Detected"
|
|
bitfld.long 0x08 11. " ND75 ,New data flag 75" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 10. " ND74 ,New data flag 74" "Not detected,Detected"
|
|
bitfld.long 0x08 9. " ND73 ,New data flag 73" "Not detected,Detected"
|
|
bitfld.long 0x08 8. " ND72 ,New data flag 72" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 7. " ND71 ,New data flag 71" "Not detected,Detected"
|
|
bitfld.long 0x08 6. " ND70 ,New data flag 70" "Not detected,Detected"
|
|
bitfld.long 0x08 5. " ND69 ,New data flag 69" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 4. " ND68 ,New data flag 68" "Not detected,Detected"
|
|
bitfld.long 0x08 3. " ND67 ,New data flag 67" "Not detected,Detected"
|
|
bitfld.long 0x08 2. " ND66 ,New data flag 66" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 1. " ND65 ,New data flag 65" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " ND64 ,New data flag 64" "Not detected,Detected"
|
|
line.long 0x0C "NDAT4,FlexRay New Data Register 4"
|
|
bitfld.long 0x0C 31. " ND127 ,New data flag 127" "Not detected,Detected"
|
|
bitfld.long 0x0C 30. " ND126 ,New data flag 126" "Not detected,Detected"
|
|
bitfld.long 0x0C 29. " ND125 ,New data flag 125" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 28. " ND124 ,New data flag 124" "Not detected,Detected"
|
|
bitfld.long 0x0C 27. " ND123 ,New data flag 123" "Not detected,Detected"
|
|
bitfld.long 0x0C 26. " ND122 ,New data flag 122" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 25. " ND121 ,New data flag 121" "Not detected,Detected"
|
|
bitfld.long 0x0C 24. " ND120 ,New data flag 120" "Not detected,Detected"
|
|
bitfld.long 0x0C 23. " ND119 ,New data flag 119" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 22. " ND118 ,New data flag 118" "Not detected,Detected"
|
|
bitfld.long 0x0C 21. " ND117 ,New data flag 117" "Not detected,Detected"
|
|
bitfld.long 0x0C 20. " ND116 ,New data flag 116" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 19. " ND115 ,New data flag 115" "Not detected,Detected"
|
|
bitfld.long 0x0C 18. " ND114 ,New data flag 114" "Not detected,Detected"
|
|
bitfld.long 0x0C 17. " ND113 ,New data flag 113" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 16. " ND112 ,New data flag 112" "Not detected,Detected"
|
|
bitfld.long 0x0C 15. " ND111 ,New data flag 111" "Not detected,Detected"
|
|
bitfld.long 0x0C 14. " ND110 ,New data flag 110" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 13. " ND109 ,New data flag 109" "Not detected,Detected"
|
|
bitfld.long 0x0C 12. " ND108 ,New data flag 108" "Not detected,Detected"
|
|
bitfld.long 0x0C 11. " ND107 ,New data flag 107" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 10. " ND106 ,New data flag 106" "Not detected,Detected"
|
|
bitfld.long 0x0C 9. " ND105 ,New data flag 105" "Not detected,Detected"
|
|
bitfld.long 0x0C 8. " ND104 ,New data flag 104" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 7. " ND103 ,New data flag 103" "Not detected,Detected"
|
|
bitfld.long 0x0C 6. " ND102 ,New data flag 102" "Not detected,Detected"
|
|
bitfld.long 0x0C 5. " ND101 ,New data flag 101" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 4. " ND100 ,New data flag 100" "Not detected,Detected"
|
|
bitfld.long 0x0C 3. " ND99 ,New data flag 99" "Not detected,Detected"
|
|
bitfld.long 0x0C 2. " ND98 ,New data flag 98" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x0C 1. " ND97 ,New data flag 97" "Not detected,Detected"
|
|
bitfld.long 0x0C 0. " ND96 ,New data flag 96" "Not detected,Detected"
|
|
rgroup.long 0x0340++0x0F
|
|
line.long 0x00 "MBSC1,Message Buffer Status Changed 1 Register"
|
|
bitfld.long 0x00 31. " MBS31 ,Message buffer status changed flag 31" "Not changed,Changed"
|
|
bitfld.long 0x00 30. " MBS30 ,Message buffer status changed flag 30" "Not changed,Changed"
|
|
bitfld.long 0x00 29. " MBS29 ,Message buffer status changed flag 29" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 28. " MBS28 ,Message buffer status changed flag 28" "Not changed,Changed"
|
|
bitfld.long 0x00 27. " MBS27 ,Message buffer status changed flag 27" "Not changed,Changed"
|
|
bitfld.long 0x00 26. " MBS26 ,Message buffer status changed flag 26" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 25. " MBS25 ,Message buffer status changed flag 25" "Not changed,Changed"
|
|
bitfld.long 0x00 24. " MBS24 ,Message buffer status changed flag 24" "Not changed,Changed"
|
|
bitfld.long 0x00 23. " MBS23 ,Message buffer status changed flag 23" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 22. " MBS22 ,Message buffer status changed flag 22" "Not changed,Changed"
|
|
bitfld.long 0x00 21. " MBS21 ,Message buffer status changed flag 21" "Not changed,Changed"
|
|
bitfld.long 0x00 20. " MBS20 ,Message buffer status changed flag 20" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 19. " MBS19 ,Message buffer status changed flag 19" "Not changed,Changed"
|
|
bitfld.long 0x00 18. " MBS18 ,Message buffer status changed flag 18" "Not changed,Changed"
|
|
bitfld.long 0x00 17. " MBS17 ,Message buffer status changed flag 17" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 16. " MBS16 ,Message buffer status changed flag 16" "Not changed,Changed"
|
|
bitfld.long 0x00 15. " MBS15 ,Message buffer status changed flag 15" "Not changed,Changed"
|
|
bitfld.long 0x00 14. " MBS14 ,Message buffer status changed flag 14" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 13. " MBS13 ,Message buffer status changed flag 13" "Not changed,Changed"
|
|
bitfld.long 0x00 12. " MBS12 ,Message buffer status changed flag 12" "Not changed,Changed"
|
|
bitfld.long 0x00 11. " MBS11 ,Message buffer status changed flag 11" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 10. " MBS10 ,Message buffer status changed flag 10" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " MBS9 ,Message buffer status changed flag 9" "Not changed,Changed"
|
|
bitfld.long 0x00 8. " MBS8 ,Message buffer status changed flag 8" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 7. " MBS7 ,Message buffer status changed flag 7" "Not changed,Changed"
|
|
bitfld.long 0x00 6. " MBS6 ,Message buffer status changed flag 6" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " MBS5 ,Message buffer status changed flag 5" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 4. " MBS4 ,Message buffer status changed flag 4" "Not changed,Changed"
|
|
bitfld.long 0x00 3. " MBS3 ,Message buffer status changed flag 3" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " MBS2 ,Message buffer status changed flag 2" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 1. " MBS1 ,Message buffer status changed flag 1" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " MBS0 ,Message buffer status changed flag 0" "Not changed,Changed"
|
|
line.long 0x04 "MBSC2,FlexRay Message Buffer Status Changed Register 2"
|
|
bitfld.long 0x04 31. " MBS63 ,Message buffer status changed flag 63" "Not changed,Changed"
|
|
bitfld.long 0x04 30. " MBS62 ,Message buffer status changed flag 62" "Not changed,Changed"
|
|
bitfld.long 0x04 29. " MBS61 ,Message buffer status changed flag 61" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 28. " MBS60 ,Message buffer status changed flag 60" "Not changed,Changed"
|
|
bitfld.long 0x04 27. " MBS59 ,Message buffer status changed flag 59" "Not changed,Changed"
|
|
bitfld.long 0x04 26. " MBS58 ,Message buffer status changed flag 58" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 25. " MBS57 ,Message buffer status changed flag 57" "Not changed,Changed"
|
|
bitfld.long 0x04 24. " MBS56 ,Message buffer status changed flag 56" "Not changed,Changed"
|
|
bitfld.long 0x04 23. " MBS55 ,Message buffer status changed flag 55" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 22. " MBS54 ,Message buffer status changed flag 54" "Not changed,Changed"
|
|
bitfld.long 0x04 21. " MBS53 ,Message buffer status changed flag 53" "Not changed,Changed"
|
|
bitfld.long 0x04 20. " MBS52 ,Message buffer status changed flag 52" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 19. " MBS51 ,Message buffer status changed flag 51" "Not changed,Changed"
|
|
bitfld.long 0x04 18. " MBS50 ,Message buffer status changed flag 50" "Not changed,Changed"
|
|
bitfld.long 0x04 17. " MBS49 ,Message buffer status changed flag 49" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 16. " MBS48 ,Message buffer status changed flag 48" "Not changed,Changed"
|
|
bitfld.long 0x04 15. " MBS47 ,Message buffer status changed flag 47" "Not changed,Changed"
|
|
bitfld.long 0x04 14. " MBS46 ,Message buffer status changed flag 46" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 13. " MBS45 ,Message buffer status changed flag 45" "Not changed,Changed"
|
|
bitfld.long 0x04 12. " MBS44 ,Message buffer status changed flag 44" "Not changed,Changed"
|
|
bitfld.long 0x04 11. " MBS43 ,Message buffer status changed flag 43" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 10. " MBS42 ,Message buffer status changed flag 42" "Not changed,Changed"
|
|
bitfld.long 0x04 9. " MBS41 ,Message buffer status changed flag 41" "Not changed,Changed"
|
|
bitfld.long 0x04 8. " MBS40 ,Message buffer status changed flag 40" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 7. " MBS39 ,Message buffer status changed flag 39" "Not changed,Changed"
|
|
bitfld.long 0x04 6. " MBS38 ,Message buffer status changed flag 38" "Not changed,Changed"
|
|
bitfld.long 0x04 5. " MBS37 ,Message buffer status changed flag 37" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 4. " MBS36 ,Message buffer status changed flag 36" "Not changed,Changed"
|
|
bitfld.long 0x04 3. " MBS35 ,Message buffer status changed flag 35" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " MBS34 ,Message buffer status changed flag 34" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x04 1. " MBS33 ,Message buffer status changed flag 33" "Not changed,Changed"
|
|
bitfld.long 0x04 0. " MBS32 ,Message buffer status changed flag 32" "Not changed,Changed"
|
|
line.long 0x08 "MBSC3,FlexRay Message Buffer Status Changed Register 3"
|
|
bitfld.long 0x08 31. " MBS95 ,Message buffer status changed flag 95" "Not changed,Changed"
|
|
bitfld.long 0x08 30. " MBS94 ,Message buffer status changed flag 94" "Not changed,Changed"
|
|
bitfld.long 0x08 29. " MBS93 ,Message buffer status changed flag 93" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 28. " MBS92 ,Message buffer status changed flag 92" "Not changed,Changed"
|
|
bitfld.long 0x08 27. " MBS91 ,Message buffer status changed flag 91" "Not changed,Changed"
|
|
bitfld.long 0x08 26. " MBS90 ,Message buffer status changed flag 90" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 25. " MBS89 ,Message buffer status changed flag 89" "Not changed,Changed"
|
|
bitfld.long 0x08 24. " MBS88 ,Message buffer status changed flag 88" "Not changed,Changed"
|
|
bitfld.long 0x08 23. " MBS87 ,Message buffer status changed flag 87" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 22. " MBS86 ,Message buffer status changed flag 86" "Not changed,Changed"
|
|
bitfld.long 0x08 21. " MBS85 ,Message buffer status changed flag 85" "Not changed,Changed"
|
|
bitfld.long 0x08 20. " MBS84 ,Message buffer status changed flag 84" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 19. " MBS83 ,Message buffer status changed flag 83" "Not changed,Changed"
|
|
bitfld.long 0x08 18. " MBS82 ,Message buffer status changed flag 82" "Not changed,Changed"
|
|
bitfld.long 0x08 17. " MBS81 ,Message buffer status changed flag 81" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 16. " MBS80 ,Message buffer status changed flag 80" "Not changed,Changed"
|
|
bitfld.long 0x08 15. " MBS79 ,Message buffer status changed flag 79" "Not changed,Changed"
|
|
bitfld.long 0x08 14. " MBS78 ,Message buffer status changed flag 78" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 13. " MBS77 ,Message buffer status changed flag 77" "Not changed,Changed"
|
|
bitfld.long 0x08 12. " MBS76 ,Message buffer status changed flag 76" "Not changed,Changed"
|
|
bitfld.long 0x08 11. " MBS75 ,Message buffer status changed flag 75" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 10. " MBS74 ,Message buffer status changed flag 74" "Not changed,Changed"
|
|
bitfld.long 0x08 9. " MBS73 ,Message buffer status changed flag 73" "Not changed,Changed"
|
|
bitfld.long 0x08 8. " MBS72 ,Message buffer status changed flag 72" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 7. " MBS71 ,Message buffer status changed flag 71" "Not changed,Changed"
|
|
bitfld.long 0x08 6. " MBS70 ,Message buffer status changed flag 70" "Not changed,Changed"
|
|
bitfld.long 0x08 5. " MBS69 ,Message buffer status changed flag 69" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 4. " MBS68 ,Message buffer status changed flag 68" "Not changed,Changed"
|
|
bitfld.long 0x08 3. " MBS67 ,Message buffer status changed flag 67" "Not changed,Changed"
|
|
bitfld.long 0x08 2. " MBS66 ,Message buffer status changed flag 66" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x08 1. " MBS65 ,Message buffer status changed flag 65" "Not changed,Changed"
|
|
bitfld.long 0x08 0. " MBS64 ,Message buffer status changed flag 64" "Not changed,Changed"
|
|
line.long 0x0C "MBSC4,FlexRay Message Buffer Status Changed Register 4"
|
|
bitfld.long 0x0C 31. " MBS127 ,Message buffer status changed flag 127" "Not changed,Changed"
|
|
bitfld.long 0x0C 30. " MBS126 ,Message buffer status changed flag 126" "Not changed,Changed"
|
|
bitfld.long 0x0C 29. " MBS125 ,Message buffer status changed flag 125" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 28. " MBS124 ,Message buffer status changed flag 124" "Not changed,Changed"
|
|
bitfld.long 0x0C 27. " MBS123 ,Message buffer status changed flag 123" "Not changed,Changed"
|
|
bitfld.long 0x0C 26. " MBS122 ,Message buffer status changed flag 122" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 25. " MBS121 ,Message buffer status changed flag 121" "Not changed,Changed"
|
|
bitfld.long 0x0C 24. " MBS120 ,Message buffer status changed flag 120" "Not changed,Changed"
|
|
bitfld.long 0x0C 23. " MBS119 ,Message buffer status changed flag 119" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 22. " MBS118 ,Message buffer status changed flag 118" "Not changed,Changed"
|
|
bitfld.long 0x0C 21. " MBS117 ,Message buffer status changed flag 117" "Not changed,Changed"
|
|
bitfld.long 0x0C 20. " MBS116 ,Message buffer status changed flag 116" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 19. " MBS115 ,Message buffer status changed flag 115" "Not changed,Changed"
|
|
bitfld.long 0x0C 18. " MBS114 ,Message buffer status changed flag 114" "Not changed,Changed"
|
|
bitfld.long 0x0C 17. " MBS113 ,Message buffer status changed flag 113" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 16. " MBS112 ,Message buffer status changed flag 112" "Not changed,Changed"
|
|
bitfld.long 0x0C 15. " MBS111 ,Message buffer status changed flag 111" "Not changed,Changed"
|
|
bitfld.long 0x0C 14. " MBS110 ,Message buffer status changed flag 110" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 13. " MBS109 ,Message buffer status changed flag 109" "Not changed,Changed"
|
|
bitfld.long 0x0C 12. " MBS108 ,Message buffer status changed flag 108" "Not changed,Changed"
|
|
bitfld.long 0x0C 11. " MBS107 ,Message buffer status changed flag 107" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 10. " MBS106 ,Message buffer status changed flag 106" "Not changed,Changed"
|
|
bitfld.long 0x0C 9. " MBS105 ,Message buffer status changed flag 105" "Not changed,Changed"
|
|
bitfld.long 0x0C 8. " MBS104 ,Message buffer status changed flag 104" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 7. " MBS103 ,Message buffer status changed flag 103" "Not changed,Changed"
|
|
bitfld.long 0x0C 6. " MBS102 ,Message buffer status changed flag 102" "Not changed,Changed"
|
|
bitfld.long 0x0C 5. " MBS101 ,Message buffer status changed flag 101" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 4. " MBS100 ,Message buffer status changed flag 100" "Not changed,Changed"
|
|
bitfld.long 0x0C 3. " MBS99 ,Message buffer status changed flag 99" "Not changed,Changed"
|
|
bitfld.long 0x0C 2. " MBS98 ,Message buffer status changed flag 98" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x0C 1. " MBS97 ,Message buffer status changed flag 97" "Not changed,Changed"
|
|
bitfld.long 0x0C 0. " MBS96 ,Message buffer status changed flag 96" "Not changed,Changed"
|
|
tree.end
|
|
tree "Identification Registers"
|
|
sif (cpuis("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
hexmask.long.byte 0x00 20.--27. 1. " STEP ,Step of core release"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp- year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design time stamp- month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design time stamp- day"
|
|
elif (cpuis("TMS570LS3137-EP"))
|
|
rgroup.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " STEP ,Step of core release"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp- year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design time stamp- month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design time stamp- day"
|
|
else
|
|
if ((((per.l((ad:0xFFF7C800+0x03F0)))&0xF0F0)==0x0000))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" ",1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xF0F0)==0x1000))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" ",1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xF0F0)==(0x10||0x20)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" ",1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xF0F0)==(0x1010||0x1020)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xFFF0)==(0x130||0x0330||0x530||0x730||0x830)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "0,1,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xFFF0)==(0x1030||0x1230)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "0,1,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xFFF0)==(0x430||0x630||0x930)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "0,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xFFF0)==(0x1130)))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "0,?..."
|
|
elif ((((per.l((ad:0xFFF7C800+0x03F0)))&0xFFF0)==0x0230))
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "0,1,?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" ",1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "0,1,2,3,?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "?..."
|
|
else
|
|
group.long 0x03F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" ",,1,?..."
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,?..."
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design time stamp - year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " MON ,Design time stamp - month" "?..."
|
|
bitfld.long 0x00 8.--11. ",Design time stamp - month" "?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DAY ,Design time stamp - day" "?..."
|
|
bitfld.long 0x00 0.--3. ",Design time stamp - day" "?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x03F4++0x03
|
|
line.long 0x0 "ER,Endian Register"
|
|
tree.end
|
|
tree "Input Buffer"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "WRDS1,Write Data Section [1]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "WRDS2,Write Data Section [2]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "WRDS3,Write Data Section [3]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "WRDS4,Write Data Section [4]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "WRDS5,Write Data Section [5]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "WRDS6,Write Data Section [6]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "WRDS7,Write Data Section [7]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "WRDS8,Write Data Section [8]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "WRDS9,Write Data Section [9]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "WRDS10,Write Data Section [10]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "WRDS11,Write Data Section [11]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "WRDS12,Write Data Section [12]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "WRDS13,Write Data Section [13]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "WRDS14,Write Data Section [14]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "WRDS15,Write Data Section [15]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "WRDS16,Write Data Section [16]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "WRDS17,Write Data Section [17]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "WRDS18,Write Data Section [18]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "WRDS19,Write Data Section [19]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "WRDS20,Write Data Section [20]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "WRDS21,Write Data Section [21]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "WRDS22,Write Data Section [22]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "WRDS23,Write Data Section [23]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "WRDS24,Write Data Section [24]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "WRDS25,Write Data Section [25]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "WRDS26,Write Data Section [26]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "WRDS27,Write Data Section [27]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "WRDS28,Write Data Section [28]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "WRDS29,Write Data Section [29]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "WRDS30,Write Data Section [30]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "WRDS31,Write Data Section [31]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "WRDS32,Write Data Section [32]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "WRDS33,Write Data Section [33]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "WRDS34,Write Data Section [34]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "WRDS35,Write Data Section [35]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "WRDS36,Write Data Section [36]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "WRDS37,Write Data Section [37]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "WRDS38,Write Data Section [38]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "WRDS39,Write Data Section [39]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "WRDS40,Write Data Section [40]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "WRDS41,Write Data Section [41]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "WRDS42,Write Data Section [42]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "WRDS43,Write Data Section [43]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "WRDS44,Write Data Section [44]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "WRDS45,Write Data Section [45]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "WRDS46,Write Data Section [46]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "WRDS47,Write Data Section [47]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "WRDS48,Write Data Section [48]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "WRDS49,Write Data Section [49]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "WRDS50,Write Data Section [50]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "WRDS51,Write Data Section [51]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "WRDS52,Write Data Section [52]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "WRDS53,Write Data Section [53]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "WRDS54,Write Data Section [54]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "WRDS55,Write Data Section [55]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "WRDS56,Write Data Section [56]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "WRDS57,Write Data Section [57]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "WRDS58,Write Data Section [58]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "WRDS59,Write Data Section [59]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "WRDS60,Write Data Section [60]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "WRDS61,Write Data Section [61]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "WRDS62,Write Data Section [62]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "WRDS63,Write Data Section [63]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "WRDS64,Write Data Section [64]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "WRDS1,Write Data Section Register [1]"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "WRDS2,Write Data Section Register [2]"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "WRDS3,Write Data Section Register [3]"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "WRDS4,Write Data Section Register [4]"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "WRDS5,Write Data Section Register [5]"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "WRDS6,Write Data Section Register [6]"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "WRDS7,Write Data Section Register [7]"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "WRDS8,Write Data Section Register [8]"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "WRDS9,Write Data Section Register [9]"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "WRDS10,Write Data Section Register [10]"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "WRDS11,Write Data Section Register [11]"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "WRDS12,Write Data Section Register [12]"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "WRDS13,Write Data Section Register [13]"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "WRDS14,Write Data Section Register [14]"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "WRDS15,Write Data Section Register [15]"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "WRDS16,Write Data Section Register [16]"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "WRDS17,Write Data Section Register [17]"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "WRDS18,Write Data Section Register [18]"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "WRDS19,Write Data Section Register [19]"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "WRDS20,Write Data Section Register [20]"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "WRDS21,Write Data Section Register [21]"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "WRDS22,Write Data Section Register [22]"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "WRDS23,Write Data Section Register [23]"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "WRDS24,Write Data Section Register [24]"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "WRDS25,Write Data Section Register [25]"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "WRDS26,Write Data Section Register [26]"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "WRDS27,Write Data Section Register [27]"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "WRDS28,Write Data Section Register [28]"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "WRDS29,Write Data Section Register [29]"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "WRDS30,Write Data Section Register [30]"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "WRDS31,Write Data Section Register [31]"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "WRDS32,Write Data Section Register [32]"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "WRDS33,Write Data Section Register [33]"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "WRDS34,Write Data Section Register [34]"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "WRDS35,Write Data Section Register [35]"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "WRDS36,Write Data Section Register [36]"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "WRDS37,Write Data Section Register [37]"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "WRDS38,Write Data Section Register [38]"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "WRDS39,Write Data Section Register [39]"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "WRDS40,Write Data Section Register [40]"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "WRDS41,Write Data Section Register [41]"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "WRDS42,Write Data Section Register [42]"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "WRDS43,Write Data Section Register [43]"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "WRDS44,Write Data Section Register [44]"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "WRDS45,Write Data Section Register [45]"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "WRDS46,Write Data Section Register [46]"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "WRDS47,Write Data Section Register [47]"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "WRDS48,Write Data Section Register [48]"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "WRDS49,Write Data Section Register [49]"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "WRDS50,Write Data Section Register [50]"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "WRDS51,Write Data Section Register [51]"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "WRDS52,Write Data Section Register [52]"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "WRDS53,Write Data Section Register [53]"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "WRDS54,Write Data Section Register [54]"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "WRDS55,Write Data Section Register [55]"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "WRDS56,Write Data Section Register [56]"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "WRDS57,Write Data Section Register [57]"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "WRDS58,Write Data Section Register [58]"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "WRDS59,Write Data Section Register [59]"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "WRDS60,Write Data Section Register [60]"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "WRDS61,Write Data Section Register [61]"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "WRDS62,Write Data Section Register [62]"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "WRDS63,Write Data Section Register [63]"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "WRDS64,Write Data Section Register [64]"
|
|
endif
|
|
group.long 0x500++0x0B
|
|
line.long 0x00 "WRHS1,Write Header Section 1 Register"
|
|
bitfld.long 0x00 29. " MBI ,Message buffer interrupt" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " TXM ,Transmission mode" "Continuous,Single-shot"
|
|
bitfld.long 0x00 27. " PPIT ,Payload preamble indicator transmit" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CFG ,Message buffer configuration bit" "Receive,Transmit"
|
|
bitfld.long 0x00 25. " CHB ,Channel filter control B" "No effect,Channel B"
|
|
bitfld.long 0x00 24. " CHA ,Channel filter control A" "No effect,Channel A"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle code"
|
|
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
|
|
line.long 0x04 "WRHS2,Write Header Section 2 Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Payload length configured"
|
|
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC"
|
|
line.long 0x08 "WRHS3,Write Header Section 3 Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " DP ,Data pointer"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "IBCM,Input Buffer Command Mask Register"
|
|
bitfld.long 0x00 18. " STXRS ,Transmission request shadow" "Reset,Set"
|
|
bitfld.long 0x00 17. " LDSS ,Load data section shadow" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " LHSS ,Load header section shadow" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x00 2. " STXRH ,Set transmission request host" "Reset,Set"
|
|
bitfld.long 0x00 1. " LDSH ,Load data section host" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " LHSH ,Load header section host" "Not updated,Updated"
|
|
line.long 0x04 "IBCR,Input Buffer Command Request Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 31. " IBSYS ,Input buffer busy shadow" "Completed,In progress"
|
|
hexmask.long.byte 0x04 16.--22. 1. " IBRS ,Input buffer request shadow"
|
|
bitfld.long 0x04 15. " IBSYH ,Input buffer busy host" "Not requested,Requested"
|
|
else
|
|
hexmask.long.byte 0x04 16.--22. 1. " IBRS ,Input buffer request shadow"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x04 0.--6. 1. " IBRH ,Input buffer request host"
|
|
tree.end
|
|
tree "Output Buffer"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "RDDS1R,Read Data Section [1] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "RDDS2R,Read Data Section [2] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "RDDS3R,Read Data Section [3] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "RDDS4R,Read Data Section [4] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "RDDS5R,Read Data Section [5] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "RDDS6R,Read Data Section [6] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "RDDS7R,Read Data Section [7] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "RDDS8R,Read Data Section [8] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "RDDS9R,Read Data Section [9] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "RDDS10R,Read Data Section [10] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "RDDS11R,Read Data Section [11] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "RDDS12R,Read Data Section [12] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "RDDS13R,Read Data Section [13] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "RDDS14R,Read Data Section [14] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "RDDS15R,Read Data Section [15] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "RDDS16R,Read Data Section [16] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "RDDS17R,Read Data Section [17] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "RDDS18R,Read Data Section [18] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "RDDS19R,Read Data Section [19] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "RDDS20R,Read Data Section [20] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "RDDS21R,Read Data Section [21] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "RDDS22R,Read Data Section [22] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "RDDS23R,Read Data Section [23] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "RDDS24R,Read Data Section [24] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "RDDS25R,Read Data Section [25] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "RDDS26R,Read Data Section [26] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "RDDS27R,Read Data Section [27] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "RDDS28R,Read Data Section [28] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "RDDS29R,Read Data Section [29] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "RDDS30R,Read Data Section [30] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "RDDS31R,Read Data Section [31] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "RDDS32R,Read Data Section [32] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "RDDS33R,Read Data Section [33] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "RDDS34R,Read Data Section [34] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "RDDS35R,Read Data Section [35] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "RDDS36R,Read Data Section [36] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "RDDS37R,Read Data Section [37] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "RDDS38R,Read Data Section [38] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "RDDS39R,Read Data Section [39] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "RDDS40R,Read Data Section [40] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "RDDS41R,Read Data Section [41] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "RDDS42R,Read Data Section [42] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "RDDS43R,Read Data Section [43] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "RDDS44R,Read Data Section [44] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "RDDS45R,Read Data Section [45] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "RDDS46R,Read Data Section [46] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "RDDS47R,Read Data Section [47] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "RDDS48R,Read Data Section [48] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "RDDS49R,Read Data Section [49] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "RDDS50R,Read Data Section [50] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "RDDS51R,Read Data Section [51] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "RDDS52R,Read Data Section [52] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "RDDS53R,Read Data Section [53] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "RDDS54R,Read Data Section [54] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "RDDS55R,Read Data Section [55] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "RDDS56R,Read Data Section [56] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "RDDS57R,Read Data Section [57] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "RDDS58R,Read Data Section [58] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "RDDS59R,Read Data Section [59] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "RDDS60R,Read Data Section [60] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F4++0x03
|
|
line.long 0x00 "RDDS61R,Read Data Section [61] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F8++0x03
|
|
line.long 0x00 "RDDS62R,Read Data Section [62] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6FC++0x03
|
|
line.long 0x00 "RDDS63R,Read Data Section [63] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x700++0x03
|
|
line.long 0x00 "RDDS64R,Read Data Section [64] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
elif (cpuis("TMS570LS3137-EP"))
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "RDS1R,Read Data Section [1] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "RDS2R,Read Data Section [2] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "RDS3R,Read Data Section [3] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "RDS4R,Read Data Section [4] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "RDS5R,Read Data Section [5] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "RDS6R,Read Data Section [6] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "RDS7R,Read Data Section [7] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "RDS8R,Read Data Section [8] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "RDS9R,Read Data Section [9] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "RDS10R,Read Data Section [10] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "RDS11R,Read Data Section [11] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "RDS12R,Read Data Section [12] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "RDS13R,Read Data Section [13] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "RDS14R,Read Data Section [14] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "RDS15R,Read Data Section [15] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "RDS16R,Read Data Section [16] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "RDS17R,Read Data Section [17] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "RDS18R,Read Data Section [18] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "RDS19R,Read Data Section [19] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "RDS20R,Read Data Section [20] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "RDS21R,Read Data Section [21] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "RDS22R,Read Data Section [22] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "RDS23R,Read Data Section [23] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "RDS24R,Read Data Section [24] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "RDS25R,Read Data Section [25] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "RDS26R,Read Data Section [26] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "RDS27R,Read Data Section [27] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "RDS28R,Read Data Section [28] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "RDS29R,Read Data Section [29] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "RDS30R,Read Data Section [30] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "RDS31R,Read Data Section [31] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "RDS32R,Read Data Section [32] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "RDS33R,Read Data Section [33] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "RDS34R,Read Data Section [34] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "RDS35R,Read Data Section [35] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "RDS36R,Read Data Section [36] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "RDS37R,Read Data Section [37] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "RDS38R,Read Data Section [38] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "RDS39R,Read Data Section [39] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "RDS40R,Read Data Section [40] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "RDS41R,Read Data Section [41] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "RDS42R,Read Data Section [42] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "RDS43R,Read Data Section [43] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "RDS44R,Read Data Section [44] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "RDS45R,Read Data Section [45] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "RDS46R,Read Data Section [46] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "RDS47R,Read Data Section [47] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "RDS48R,Read Data Section [48] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "RDS49R,Read Data Section [49] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "RDS50R,Read Data Section [50] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "RDS51R,Read Data Section [51] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "RDS52R,Read Data Section [52] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "RDS53R,Read Data Section [53] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "RDS54R,Read Data Section [54] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "RDS55R,Read Data Section [55] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "RDS56R,Read Data Section [56] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "RDS57R,Read Data Section [57] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "RDS58R,Read Data Section [58] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "RDS59R,Read Data Section [59] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "RDS60R,Read Data Section [60] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F4++0x03
|
|
line.long 0x00 "RDS61R,Read Data Section [61] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6F8++0x03
|
|
line.long 0x00 "RDS62R,Read Data Section [62] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x6FC++0x03
|
|
line.long 0x00 "RDS63R,Read Data Section [63] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
rgroup.long 0x700++0x03
|
|
line.long 0x00 "RDS64R,Read Data Section [64] Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MD3 ,Message data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MD2 ,Message data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MD1 ,Message data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MD0 ,Message data byte 0"
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "RDSR1,Read Data Section Register [1]"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "RDSR2,Read Data Section Register [2]"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "RDSR3,Read Data Section Register [3]"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "RDSR4,Read Data Section Register [4]"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "RDSR5,Read Data Section Register [5]"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "RDSR6,Read Data Section Register [6]"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "RDSR7,Read Data Section Register [7]"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "RDSR8,Read Data Section Register [8]"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "RDSR9,Read Data Section Register [9]"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "RDSR10,Read Data Section Register [10]"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "RDSR11,Read Data Section Register [11]"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "RDSR12,Read Data Section Register [12]"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "RDSR13,Read Data Section Register [13]"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "RDSR14,Read Data Section Register [14]"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "RDSR15,Read Data Section Register [15]"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "RDSR16,Read Data Section Register [16]"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "RDSR17,Read Data Section Register [17]"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "RDSR18,Read Data Section Register [18]"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "RDSR19,Read Data Section Register [19]"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "RDSR20,Read Data Section Register [20]"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "RDSR21,Read Data Section Register [21]"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "RDSR22,Read Data Section Register [22]"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "RDSR23,Read Data Section Register [23]"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "RDSR24,Read Data Section Register [24]"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "RDSR25,Read Data Section Register [25]"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "RDSR26,Read Data Section Register [26]"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "RDSR27,Read Data Section Register [27]"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "RDSR28,Read Data Section Register [28]"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "RDSR29,Read Data Section Register [29]"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "RDSR30,Read Data Section Register [30]"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "RDSR31,Read Data Section Register [31]"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "RDSR32,Read Data Section Register [32]"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "RDSR33,Read Data Section Register [33]"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "RDSR34,Read Data Section Register [34]"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "RDSR35,Read Data Section Register [35]"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "RDSR36,Read Data Section Register [36]"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "RDSR37,Read Data Section Register [37]"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "RDSR38,Read Data Section Register [38]"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "RDSR39,Read Data Section Register [39]"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "RDSR40,Read Data Section Register [40]"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "RDSR41,Read Data Section Register [41]"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "RDSR42,Read Data Section Register [42]"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "RDSR43,Read Data Section Register [43]"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "RDSR44,Read Data Section Register [44]"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "RDSR45,Read Data Section Register [45]"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "RDSR46,Read Data Section Register [46]"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "RDSR47,Read Data Section Register [47]"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "RDSR48,Read Data Section Register [48]"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "RDSR49,Read Data Section Register [49]"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "RDSR50,Read Data Section Register [50]"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "RDSR51,Read Data Section Register [51]"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "RDSR52,Read Data Section Register [52]"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "RDSR53,Read Data Section Register [53]"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "RDSR54,Read Data Section Register [54]"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "RDSR55,Read Data Section Register [55]"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "RDSR56,Read Data Section Register [56]"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "RDSR57,Read Data Section Register [57]"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "RDSR58,Read Data Section Register [58]"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "RDSR59,Read Data Section Register [59]"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "RDSR60,Read Data Section Register [60]"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "RDSR61,Read Data Section Register [61]"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "RDSR62,Read Data Section Register [62]"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "RDSR63,Read Data Section Register [63]"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "RDSR64,Read Data Section Register [64]"
|
|
endif
|
|
group.long 0x700++0x07
|
|
line.long 0x0 "RDHS1,Read Header Section 1 Register"
|
|
bitfld.long 0x00 29. " MBI ,Message buffer interrupt" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " TXM ,Transmission mode" "Continuous,Single-shot"
|
|
bitfld.long 0x00 27. " PPIT ,Payload preamble indicator transmit" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CFG ,Message buffer configuration bit" "Receive,Transmit"
|
|
bitfld.long 0x00 25. " CHB ,Channel filter control B" "No effect,Channel B"
|
|
bitfld.long 0x00 24. " CHA ,Channel filter control A" "No effect,Channel A"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle Code"
|
|
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
|
|
line.long 0x04 "RDHS2,Read Header Section 2 Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " PLR ,Payload length received"
|
|
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Payload length configured"
|
|
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x708++0x03
|
|
line.long 0x00 "RDHS3,Read Header Section 3 Register"
|
|
bitfld.long 0x00 29. " RES ,Reflects the state of the received reserved bit" "0,1"
|
|
bitfld.long 0x00 28. " PPI ,Payload preamble indicator" "Not contained,Contained"
|
|
bitfld.long 0x00 27. " NFI ,NULL frame indicator" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 26. " SYN ,SYNC frame indicator" "Not received,Received"
|
|
bitfld.long 0x00 25. " SFI ,Startup frame indicator" "Not received,Received"
|
|
bitfld.long 0x00 24. " RCI ,Received on channel indicator" "Channel B,Channel A"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--21. 1. " RCC ,Receive cycle count"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " DP ,Data pointer"
|
|
else
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "RDHS3,Read Header Section 3 Register"
|
|
bitfld.long 0x00 28. " PPI ,Payload preamble indicator" "Not contained,Contained"
|
|
bitfld.long 0x00 27. " NFI ,NULL frame indicator" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 26. " SYN ,SYNC frame indicator" "Not received,Received"
|
|
bitfld.long 0x00 25. " SFI ,Startup frame indicator" "Not received,Received"
|
|
bitfld.long 0x00 24. " RCI ,Received on channel indicator" "Channel B,Channel A"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--21. 1. " RCC ,Receive cycle count"
|
|
hexmask.long.word 0x00 0.--10. 0x01 " DP ,Data pointer"
|
|
endif
|
|
group.long 0x70C++0x0B
|
|
line.long 0x00 "MBS,Message Buffer Status Register"
|
|
bitfld.long 0x00 28. " PPIS ,Payload preamble indictor status" "Not contained,Contained"
|
|
bitfld.long 0x00 27. " NFIS ,NULL frame indicator status" "Received,Not received"
|
|
bitfld.long 0x00 26. " SYNS ,SYNC Frame indicator status" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x00 25. " SFIS ,Startup frame indicator status" "Not received,Received"
|
|
bitfld.long 0x00 24. " RCIS ,Received on channel indicator status" "Channel B,Channel A"
|
|
hexmask.long.byte 0x00 16.--21. 1. " CCS ,Cycle count status"
|
|
newline
|
|
bitfld.long 0x00 15. " MTB ,Frame transmitted on channel B" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 14. " MTA ,Frame transmitted on channel A" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 12. " MLST ,Message Lost" "Not lost,Overwritten"
|
|
newline
|
|
bitfld.long 0x00 11. " ESB ,Empty slot channel B" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " ESA ,Empty slot channel A" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TCIB ,Transmission conflict indication channel B" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8. " TCIA ,Transmission conflict indication channel A" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " SVOB ,Slot boundary violation observed on channel B" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SVOA ,Slot boundary violation observed on channel A" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " CEOB ,Content error observed on channel B" "No error,Error"
|
|
bitfld.long 0x00 4. " CEOA ,Content error observed on channel A" "No error,Error"
|
|
bitfld.long 0x00 3. " SEOB ,Syntax error observed on channel B" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " SEOA ,Syntax error observed on channel A" "No error,Error"
|
|
bitfld.long 0x00 1. " VFRB ,Valid frame received on channel B" "Not received,Received"
|
|
bitfld.long 0x00 0. " VFRA ,Valid frame received on channel A" "Not received,Received"
|
|
line.long 0x04 "OBCM,Output Buffer Command Mask Register"
|
|
sif (cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x04 17. " RDSH ,Read data section host" "Not read,Selected"
|
|
rbitfld.long 0x04 16. " RHSH ,Read header section host" "Not read,Selected"
|
|
else
|
|
bitfld.long 0x04 17. " RDSH ,Read data section host" "Not read,Selected"
|
|
bitfld.long 0x04 16. " RHSH ,Read header section host" "Not read,Selected"
|
|
endif
|
|
bitfld.long 0x04 1. " RDSS ,Read data section shadow" "Not read,Selected"
|
|
newline
|
|
bitfld.long 0x04 0. " RHSS ,Read header section shadow" "Not read,Selected"
|
|
line.long 0x08 "OBCR,Output Buffer Command Request Register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " OBRH ,Output buffer request host"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 15. " OBSYS ,Output buffer busy shadow" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x08 15. " OBSYS ,Output buffer busy shadow" "Not requested,Requested"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 9. " REQ ,Request message RAM transfer" "Not requested,Requested"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 8. " VIEW ,View shadow buffer" "No effect,Swap"
|
|
else
|
|
bitfld.long 0x08 8. " VIEW ,View shadow buffer" "No action,Swapped"
|
|
endif
|
|
hexmask.long.byte 0x08 0.--6. 1. " OBRS ,Output buffer request shadow"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "FLEXRAYTU"
|
|
base ad:0xFFF7A000
|
|
width 18.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "GSN0,Global Static Number 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " DATA_A ,Data A"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_B ,Data B"
|
|
line.long 0x04 "GSN1,Global Static Number 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " DATA_C ,Data C"
|
|
hexmask.long.word 0x04 0.--15. 1. " DATA_D ,Data D"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "GCS/R,Global Control Set/Reset"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ENDVBM_SET/CLR ,Endianess correction on VBusp master" "Off,On"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ENDVBS_SET/CLR ,ENDianess correction on VBusp slave" "Off,On"
|
|
bitfld.long 0x00 28.--29. " ENDR ,ENDianess Correction for No (header or payload) data sink access" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
bitfld.long 0x00 26.--27. " ENDH ,ENDianess correction for header" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " ENDP ,ENDianess correction for payload" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PRIO_SET/CLR ,Transfer priority" "TTSM>TTCC,TTCC>TTSM"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " PEFT_SET/CLR ,Parity/ECC for test" "Not used,Used"
|
|
bitfld.long 0x00 16.--19. " PEL ,Parity/ECC lock" "On,On,On,On,On,Off,On,On,On,On,On,On,On,On,On,On"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " CETESM_SET/CLR ,Clear ETESM register" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " CTTCC_SET/CLR ,Clear TTCC register" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " CTTSM_SET/CLR ,Clear TTSM register" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ETSM_SET/CLR ,Enable transfer status mirrored (TSCB/LTBCC/LTBSM/TSMO1-4/TCCO1-4/TOOFF)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SILE_SET/CLR ,Status interrupt line enable (TU_int0)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " EILE_SET/CLR ,Error interrupt line enable (TU_int1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TUH_SET/CLR ,Transfer unit halted" "Not halted,Halted"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " TUE_SET/CLR ,Transfer unit enabled" "Disabled,Enabled"
|
|
line.long 0x04 "GCR,Global Control Clear"
|
|
bitfld.long 0x04 28.--29. " ENDR ,ENDianess correction for no (header or payload) data sink access" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
bitfld.long 0x04 26.--27. " ENDH ,ENDianess correction for header" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
bitfld.long 0x04 24.--25. " ENDP ,ENDianess correction for payload" "0xABCD,0xBADC,0xCDAB,0xDCBA"
|
|
bitfld.long 0x04 16.--19. " PEL ,Parity/ECC lock" "On,On,On,On,On,Off,On,On,On,On,On,On,On,On,On,On"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSCB,Transfer Status Current Buffer"
|
|
sif (cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x00 16.--20. " TSMS ,Transfer state machine status" ",IDLE,TTSM_START,TTSM_OBCM,TTSM_REQ,TTSM_VIEW,TTSM_CHECK,TTSM_RDHS,TTSM_RDDS,TTCC_START,TTCC_IBUSY,TTCC_CHECK,TTCC_WRHS,TTCC_PLC_READ,TTCC_PLC_CALC,TTCC_WRDS,TTCC_IBCM,TTCC_IBCR,TTCC_MIRROR,TTSM_END,,,,,,,,,,,,Undefined state"
|
|
rbitfld.long 0x00 12. " STUH ,Status of transfer unit state machine for halt detection" "Not halted,Halted"
|
|
else
|
|
bitfld.long 0x00 16.--20. " TSMS ,Transfer state machine status" ",IDLE,TTSM_START,TTSM_OBCM,TTSM_REQ,TTSM_VIEW,TTSM_CHECK,TTSM_RDHS,TTSM_RDDS,TTCC_START,TTCC_IBUSY,TTCC_CHECK,TTCC_WRHS,TTCC_PLC_READ,TTCC_PLC_CALC,TTCC_WRDS,TTCC_IBCM,TTCC_IBCR,TTCC_MIRROR,TTSM_END,,,,,,,,,,,,Undefined state"
|
|
bitfld.long 0x00 12. " STUH ,Status of transfer unit state machine for halt detection" "Not halted,Halted"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 8. " IDLE ,Detects transfer state machine state IDLE" "Not reached,Reached"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " BN ,Buffer number"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "LTBCC,Last Transferred Buffer to Communication Controller"
|
|
hexmask.long.byte 0x00 0.--6. 1. " BN ,Buffer number"
|
|
line.long 0x04 "LTBSM,Last Transferred Buffer to System Memory"
|
|
hexmask.long.byte 0x04 0.--6. 1. " BN ,Buffer number"
|
|
group.long 0x24++0x13
|
|
line.long 0x00 "TBA,Transfer Base Address"
|
|
line.long 0x04 "NTBA,Next Transfer Base Address"
|
|
line.long 0x08 "BAMS,Base Address of Mirrored Status"
|
|
line.long 0x0C "SAMP,Start Address of Memory Protection"
|
|
line.long 0x10 "EAMP,End Address of Memory Protection"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "TSMO1,Transfer to System Memory Occurred 1"
|
|
eventfld.long 0x00 31. " TSMO1[31] ,Transfer to system memory occurred register 1 buffer 31" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " [30] ,Transfer to system memory occurred register 1 buffer 30" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " [29] ,Transfer to system memory occurred register 1 buffer 29" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " [28] ,Transfer to system memory occurred register 1 buffer 28" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Transfer to system memory occurred register 1 buffer 27" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " [26] ,Transfer to system memory occurred register 1 buffer 26" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " [25] ,Transfer to system memory occurred register 1 buffer 25" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " [24] ,Transfer to system memory occurred register 1 buffer 24" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Transfer to system memory occurred register 1 buffer 23" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " [22] ,Transfer to system memory occurred register 1 buffer 22" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " [21] ,Transfer to system memory occurred register 1 buffer 21" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " [20] ,Transfer to system memory occurred register 1 buffer 20" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Transfer to system memory occurred register 1 buffer 19" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " [18] ,Transfer to system memory occurred register 1 buffer 18" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " [17] ,Transfer to system memory occurred register 1 buffer 17" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " [16] ,Transfer to system memory occurred register 1 buffer 16" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Transfer to system memory occurred register 1 buffer 15" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " [14] ,Transfer to system memory occurred register 1 buffer 14" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " [13] ,Transfer to system memory occurred register 1 buffer 13" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " [12] ,Transfer to system memory occurred register 1 buffer 12" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Transfer to system memory occurred register 1 buffer 11" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " [10] ,Transfer to system memory occurred register 1 buffer 10" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " [9] ,Transfer to system memory occurred register 1 buffer 9" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " [8] ,Transfer to system memory occurred register 1 buffer 8" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Transfer to system memory occurred register 1 buffer 7" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " [6] ,Transfer to system memory occurred register 1 buffer 6" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " [5] ,Transfer to system memory occurred register 1 buffer 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " [4] ,Transfer to system memory occurred register 1 buffer 4" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Transfer to system memory occurred register 1 buffer 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Transfer to system memory occurred register 1 buffer 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Transfer to system memory occurred register 1 buffer 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " [0] ,Transfer to system memory occurred register 1 buffer 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TSMO2,Transfer to System Memory Occurred 2"
|
|
eventfld.long 0x04 31. " TSMO2[63] ,Transfer to system memory occurred register 2 buffer 63" "Not occurred,Occurred"
|
|
eventfld.long 0x04 30. " [62] ,Transfer to system memory occurred register 2 buffer 62" "Not occurred,Occurred"
|
|
eventfld.long 0x04 29. " [61] ,Transfer to system memory occurred register 2 buffer 61" "Not occurred,Occurred"
|
|
eventfld.long 0x04 28. " [60] ,Transfer to system memory occurred register 2 buffer 60" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 27. " [59] ,Transfer to system memory occurred register 2 buffer 59" "Not occurred,Occurred"
|
|
eventfld.long 0x04 26. " [58] ,Transfer to system memory occurred register 2 buffer 58" "Not occurred,Occurred"
|
|
eventfld.long 0x04 25. " [57] ,Transfer to system memory occurred register 2 buffer 57" "Not occurred,Occurred"
|
|
eventfld.long 0x04 24. " [56] ,Transfer to system memory occurred register 2 buffer 56" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 23. " [55] ,Transfer to system memory occurred register 2 buffer 55" "Not occurred,Occurred"
|
|
eventfld.long 0x04 22. " [54] ,Transfer to system memory occurred register 2 buffer 54" "Not occurred,Occurred"
|
|
eventfld.long 0x04 21. " [53] ,Transfer to system memory occurred register 2 buffer 53" "Not occurred,Occurred"
|
|
eventfld.long 0x04 20. " [52] ,Transfer to system memory occurred register 2 buffer 52" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 19. " [51] ,Transfer to system memory occurred register 2 buffer 51" "Not occurred,Occurred"
|
|
eventfld.long 0x04 18. " [50] ,Transfer to system memory occurred register 2 buffer 50" "Not occurred,Occurred"
|
|
eventfld.long 0x04 17. " [49] ,Transfer to system memory occurred register 2 buffer 49" "Not occurred,Occurred"
|
|
eventfld.long 0x04 16. " [48] ,Transfer to system memory occurred register 2 buffer 48" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 15. " [47] ,Transfer to system memory occurred register 2 buffer 47" "Not occurred,Occurred"
|
|
eventfld.long 0x04 14. " [46] ,Transfer to system memory occurred register 2 buffer 46" "Not occurred,Occurred"
|
|
eventfld.long 0x04 13. " [45] ,Transfer to system memory occurred register 2 buffer 45" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " [44] ,Transfer to system memory occurred register 2 buffer 44" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 11. " [43] ,Transfer to system memory occurred register 2 buffer 43" "Not occurred,Occurred"
|
|
eventfld.long 0x04 10. " [42] ,Transfer to system memory occurred register 2 buffer 42" "Not occurred,Occurred"
|
|
eventfld.long 0x04 9. " [41] ,Transfer to system memory occurred register 2 buffer 41" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " [40] ,Transfer to system memory occurred register 2 buffer 40" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 7. " [39] ,Transfer to system memory occurred register 2 buffer 39" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " [38] ,Transfer to system memory occurred register 2 buffer 38" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " [37] ,Transfer to system memory occurred register 2 buffer 37" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " [36] ,Transfer to system memory occurred register 2 buffer 36" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 3. " [35] ,Transfer to system memory occurred register 2 buffer 35" "Not occurred,Occurred"
|
|
eventfld.long 0x04 2. " [34] ,Transfer to system memory occurred register 2 buffer 34" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " [33] ,Transfer to system memory occurred register 2 buffer 33" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " [32] ,Transfer to system memory occurred register 2 buffer 32" "Not occurred,Occurred"
|
|
line.long 0x08 "TSMO3,Transfer to System Memory Occurred 3"
|
|
eventfld.long 0x08 31. " TSMO3[95] ,Transfer to system memory occurred register 3 buffer 95" "Not occurred,Occurred"
|
|
eventfld.long 0x08 30. " [94] ,Transfer to system memory occurred register 3 buffer 94" "Not occurred,Occurred"
|
|
eventfld.long 0x08 29. " [93] ,Transfer to system memory occurred register 3 buffer 93" "Not occurred,Occurred"
|
|
eventfld.long 0x08 28. " [92] ,Transfer to system memory occurred register 3 buffer 92" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 27. " [91] ,Transfer to system memory occurred register 3 buffer 91" "Not occurred,Occurred"
|
|
eventfld.long 0x08 26. " [90] ,Transfer to system memory occurred register 3 buffer 90" "Not occurred,Occurred"
|
|
eventfld.long 0x08 25. " [89] ,Transfer to system memory occurred register 3 buffer 89" "Not occurred,Occurred"
|
|
eventfld.long 0x08 24. " [88] ,Transfer to system memory occurred register 3 buffer 88" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 23. " [87] ,Transfer to system memory occurred register 3 buffer 87" "Not occurred,Occurred"
|
|
eventfld.long 0x08 22. " [86] ,Transfer to system memory occurred register 3 buffer 86" "Not occurred,Occurred"
|
|
eventfld.long 0x08 21. " [85] ,Transfer to system memory occurred register 3 buffer 85" "Not occurred,Occurred"
|
|
eventfld.long 0x08 20. " [84] ,Transfer to system memory occurred register 3 buffer 84" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 19. " [83] ,Transfer to system memory occurred register 3 buffer 83" "Not occurred,Occurred"
|
|
eventfld.long 0x08 18. " [82] ,Transfer to system memory occurred register 3 buffer 82" "Not occurred,Occurred"
|
|
eventfld.long 0x08 17. " [81] ,Transfer to system memory occurred register 3 buffer 81" "Not occurred,Occurred"
|
|
eventfld.long 0x08 16. " [80] ,Transfer to system memory occurred register 3 buffer 80" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 15. " [79] ,Transfer to system memory occurred register 3 buffer 79" "Not occurred,Occurred"
|
|
eventfld.long 0x08 14. " [78] ,Transfer to system memory occurred register 3 buffer 78" "Not occurred,Occurred"
|
|
eventfld.long 0x08 13. " [77] ,Transfer to system memory occurred register 3 buffer 77" "Not occurred,Occurred"
|
|
eventfld.long 0x08 12. " [76] ,Transfer to system memory occurred register 3 buffer 76" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 11. " [75] ,Transfer to system memory occurred register 3 buffer 75" "Not occurred,Occurred"
|
|
eventfld.long 0x08 10. " [74] ,Transfer to system memory occurred register 3 buffer 74" "Not occurred,Occurred"
|
|
eventfld.long 0x08 9. " [73] ,Transfer to system memory occurred register 3 buffer 73" "Not occurred,Occurred"
|
|
eventfld.long 0x08 8. " [72] ,Transfer to system memory occurred register 3 buffer 72" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 7. " [71] ,Transfer to system memory occurred register 3 buffer 71" "Not occurred,Occurred"
|
|
eventfld.long 0x08 6. " [70] ,Transfer to system memory occurred register 3 buffer 70" "Not occurred,Occurred"
|
|
eventfld.long 0x08 5. " [69] ,Transfer to system memory occurred register 3 buffer 69" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " [68] ,Transfer to system memory occurred register 3 buffer 68" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 3. " [67] ,Transfer to system memory occurred register 3 buffer 67" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " [66] ,Transfer to system memory occurred register 3 buffer 66" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " [65] ,Transfer to system memory occurred register 3 buffer 65" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " [64] ,Transfer to system memory occurred register 3 buffer 64" "Not occurred,Occurred"
|
|
line.long 0x0C "TSMO4,Transfer to System Memory Occurred 4"
|
|
eventfld.long 0x0C 31. " TSMO4[127] ,Transfer to system memory occurred register 4 buffer 127" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 30. " [126] ,Transfer to system memory occurred register 4 buffer 126" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 29. " [125] ,Transfer to system memory occurred register 4 buffer 125" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 28. " [124] ,Transfer to system memory occurred register 4 buffer 124" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 27. " [123] ,Transfer to system memory occurred register 4 buffer 123" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 26. " [122] ,Transfer to system memory occurred register 4 buffer 122" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 25. " [121] ,Transfer to system memory occurred register 4 buffer 121" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 24. " [120] ,Transfer to system memory occurred register 4 buffer 120" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 23. " [119] ,Transfer to system memory occurred register 4 buffer 119" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 22. " [118] ,Transfer to system memory occurred register 4 buffer 118" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 21. " [117] ,Transfer to system memory occurred register 4 buffer 117" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 20. " [116] ,Transfer to system memory occurred register 4 buffer 116" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 19. " [115] ,Transfer to system memory occurred register 4 buffer 115" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 18. " [114] ,Transfer to system memory occurred register 4 buffer 114" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 17. " [113] ,Transfer to system memory occurred register 4 buffer 113" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 16. " [112] ,Transfer to system memory occurred register 4 buffer 112" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 15. " [111] ,Transfer to system memory occurred register 4 buffer 111" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 14. " [110] ,Transfer to system memory occurred register 4 buffer 110" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 13. " [109] ,Transfer to system memory occurred register 4 buffer 109" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 12. " [108] ,Transfer to system memory occurred register 4 buffer 108" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 11. " [107] ,Transfer to system memory occurred register 4 buffer 107" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 10. " [106] ,Transfer to system memory occurred register 4 buffer 106" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 9. " [105] ,Transfer to system memory occurred register 4 buffer 105" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 8. " [104] ,Transfer to system memory occurred register 4 buffer 104" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 7. " [103] ,Transfer to system memory occurred register 4 buffer 103" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 6. " [102] ,Transfer to system memory occurred register 4 buffer 102" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 5. " [101] ,Transfer to system memory occurred register 4 buffer 101" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 4. " [100] ,Transfer to system memory occurred register 4 buffer 100" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x0C 3. " [99] ,Transfer to system memory occurred register 4 buffer 99" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 2. " [98] ,Transfer to system memory occurred register 4 buffer 98" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 1. " [97] ,Transfer to system memory occurred register 4 buffer 97" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 0. " [96] ,Transfer to system memory occurred register 4 buffer 96" "Not occurred,Occurred"
|
|
line.long 0x10 "TCCO1,Transfer to Communication Controller Occurred 1"
|
|
eventfld.long 0x10 31. " TCCO1[31] ,Transfer to communication controller occurred register 1 buffer 31" "Not occurred,Occurred"
|
|
eventfld.long 0x10 30. " [30] ,Transfer to communication controller occurred register 1 buffer 30" "Not occurred,Occurred"
|
|
eventfld.long 0x10 29. " [29] ,Transfer to communication controller occurred register 1 buffer 29" "Not occurred,Occurred"
|
|
eventfld.long 0x10 28. " [28] ,Transfer to communication controller occurred register 1 buffer 28" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 27. " [27] ,Transfer to communication controller occurred register 1 buffer 27" "Not occurred,Occurred"
|
|
eventfld.long 0x10 26. " [26] ,Transfer to communication controller occurred register 1 buffer 26" "Not occurred,Occurred"
|
|
eventfld.long 0x10 25. " [25] ,Transfer to communication controller occurred register 1 buffer 25" "Not occurred,Occurred"
|
|
eventfld.long 0x10 24. " [24] ,Transfer to communication controller occurred register 1 buffer 24" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 23. " [23] ,Transfer to communication controller occurred register 1 buffer 23" "Not occurred,Occurred"
|
|
eventfld.long 0x10 22. " [22] ,Transfer to communication controller occurred register 1 buffer 22" "Not occurred,Occurred"
|
|
eventfld.long 0x10 21. " [21] ,Transfer to communication controller occurred register 1 buffer 21" "Not occurred,Occurred"
|
|
eventfld.long 0x10 20. " [20] ,Transfer to communication controller occurred register 1 buffer 20" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 19. " [19] ,Transfer to communication controller occurred register 1 buffer 19" "Not occurred,Occurred"
|
|
eventfld.long 0x10 18. " [18] ,Transfer to communication controller occurred register 1 buffer 18" "Not occurred,Occurred"
|
|
eventfld.long 0x10 17. " [17] ,Transfer to communication controller occurred register 1 buffer 17" "Not occurred,Occurred"
|
|
eventfld.long 0x10 16. " [16] ,Transfer to communication controller occurred register 1 buffer 16" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 15. " [15] ,Transfer to communication controller occurred register 1 buffer 15" "Not occurred,Occurred"
|
|
eventfld.long 0x10 14. " [14] ,Transfer to communication controller occurred register 1 buffer 14" "Not occurred,Occurred"
|
|
eventfld.long 0x10 13. " [13] ,Transfer to communication controller occurred register 1 buffer 13" "Not occurred,Occurred"
|
|
eventfld.long 0x10 12. " [12] ,Transfer to communication controller occurred register 1 buffer 12" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 11. " [11] ,Transfer to communication controller occurred register 1 buffer 11" "Not occurred,Occurred"
|
|
eventfld.long 0x10 10. " [10] ,Transfer to communication controller occurred register 1 buffer 10" "Not occurred,Occurred"
|
|
eventfld.long 0x10 9. " [9] ,Transfer to communication controller occurred register 1 buffer 9" "Not occurred,Occurred"
|
|
eventfld.long 0x10 8. " [8] ,Transfer to communication controller occurred register 1 buffer 8" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 7. " [7] ,Transfer to communication controller occurred register 1 buffer 7" "Not occurred,Occurred"
|
|
eventfld.long 0x10 6. " [6] ,Transfer to communication controller occurred register 1 buffer 6" "Not occurred,Occurred"
|
|
eventfld.long 0x10 5. " [5] ,Transfer to communication controller occurred register 1 buffer 5" "Not occurred,Occurred"
|
|
eventfld.long 0x10 4. " [4] ,Transfer to communication controller occurred register 1 buffer 4" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x10 3. " [3] ,Transfer to communication controller occurred register 1 buffer 3" "Not occurred,Occurred"
|
|
eventfld.long 0x10 2. " [2] ,Transfer to communication controller occurred register 1 buffer 2" "Not occurred,Occurred"
|
|
eventfld.long 0x10 1. " [1] ,Transfer to communication controller occurred register 1 buffer 1" "Not occurred,Occurred"
|
|
eventfld.long 0x10 0. " [0] ,Transfer to communication controller occurred register 1 buffer 0" "Not occurred,Occurred"
|
|
line.long 0x14 "TCCO2,Transfer to Communication Controller Occurred 2"
|
|
eventfld.long 0x14 31. " TCCO2[63] ,Transfer to communication controller occurred register 2 buffer 63" "Not occurred,Occurred"
|
|
eventfld.long 0x14 30. " [62] ,Transfer to communication controller occurred register 2 buffer 62" "Not occurred,Occurred"
|
|
eventfld.long 0x14 29. " [61] ,Transfer to communication controller occurred register 2 buffer 61" "Not occurred,Occurred"
|
|
eventfld.long 0x14 28. " [60] ,Transfer to communication controller occurred register 2 buffer 60" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 27. " [59] ,Transfer to communication controller occurred register 2 buffer 59" "Not occurred,Occurred"
|
|
eventfld.long 0x14 26. " [58] ,Transfer to communication controller occurred register 2 buffer 58" "Not occurred,Occurred"
|
|
eventfld.long 0x14 25. " [57] ,Transfer to communication controller occurred register 2 buffer 57" "Not occurred,Occurred"
|
|
eventfld.long 0x14 24. " [56] ,Transfer to communication controller occurred register 2 buffer 56" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 23. " [55] ,Transfer to communication controller occurred register 2 buffer 55" "Not occurred,Occurred"
|
|
eventfld.long 0x14 22. " [54] ,Transfer to communication controller occurred register 2 buffer 54" "Not occurred,Occurred"
|
|
eventfld.long 0x14 21. " [53] ,Transfer to communication controller occurred register 2 buffer 53" "Not occurred,Occurred"
|
|
eventfld.long 0x14 20. " [52] ,Transfer to communication controller occurred register 2 buffer 52" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 19. " [51] ,Transfer to communication controller occurred register 2 buffer 51" "Not occurred,Occurred"
|
|
eventfld.long 0x14 18. " [50] ,Transfer to communication controller occurred register 2 buffer 50" "Not occurred,Occurred"
|
|
eventfld.long 0x14 17. " [49] ,Transfer to communication controller occurred register 2 buffer 49" "Not occurred,Occurred"
|
|
eventfld.long 0x14 16. " [48] ,Transfer to communication controller occurred register 2 buffer 48" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 15. " [47] ,Transfer to communication controller occurred register 2 buffer 47" "Not occurred,Occurred"
|
|
eventfld.long 0x14 14. " [46] ,Transfer to communication controller occurred register 2 buffer 46" "Not occurred,Occurred"
|
|
eventfld.long 0x14 13. " [45] ,Transfer to communication controller occurred register 2 buffer 45" "Not occurred,Occurred"
|
|
eventfld.long 0x14 12. " [44] ,Transfer to communication controller occurred register 2 buffer 44" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 11. " [43] ,Transfer to communication controller occurred register 2 buffer 43" "Not occurred,Occurred"
|
|
eventfld.long 0x14 10. " [42] ,Transfer to communication controller occurred register 2 buffer 42" "Not occurred,Occurred"
|
|
eventfld.long 0x14 9. " [41] ,Transfer to communication controller occurred register 2 buffer 41" "Not occurred,Occurred"
|
|
eventfld.long 0x14 8. " [40] ,Transfer to communication controller occurred register 2 buffer 40" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 7. " [39] ,Transfer to communication controller occurred register 2 buffer 39" "Not occurred,Occurred"
|
|
eventfld.long 0x14 6. " [38] ,Transfer to communication controller occurred register 2 buffer 38" "Not occurred,Occurred"
|
|
eventfld.long 0x14 5. " [37] ,Transfer to communication controller occurred register 2 buffer 37" "Not occurred,Occurred"
|
|
eventfld.long 0x14 4. " [36] ,Transfer to communication controller occurred register 2 buffer 36" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x14 3. " [35] ,Transfer to communication controller occurred register 2 buffer 35" "Not occurred,Occurred"
|
|
eventfld.long 0x14 2. " [34] ,Transfer to communication controller occurred register 2 buffer 34" "Not occurred,Occurred"
|
|
eventfld.long 0x14 1. " [33] ,Transfer to communication controller occurred register 2 buffer 33" "Not occurred,Occurred"
|
|
eventfld.long 0x14 0. " [32] ,Transfer to communication controller occurred register 2 buffer 32" "Not occurred,Occurred"
|
|
line.long 0x18 "TCCO3,Transfer to Communication Controller Occurred 3"
|
|
eventfld.long 0x18 31. " TCCO3[95] ,Transfer to communication controller occurred register 3 buffer 95" "Not occurred,Occurred"
|
|
eventfld.long 0x18 30. " [94] ,Transfer to communication controller occurred register 3 buffer 94" "Not occurred,Occurred"
|
|
eventfld.long 0x18 29. " [93] ,Transfer to communication controller occurred register 3 buffer 93" "Not occurred,Occurred"
|
|
eventfld.long 0x18 28. " [92] ,Transfer to communication controller occurred register 3 buffer 92" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 27. " [91] ,Transfer to communication controller occurred register 3 buffer 91" "Not occurred,Occurred"
|
|
eventfld.long 0x18 26. " [90] ,Transfer to communication controller occurred register 3 buffer 90" "Not occurred,Occurred"
|
|
eventfld.long 0x18 25. " [89] ,Transfer to communication controller occurred register 3 buffer 89" "Not occurred,Occurred"
|
|
eventfld.long 0x18 24. " [88] ,Transfer to communication controller occurred register 3 buffer 88" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 23. " [87] ,Transfer to communication controller occurred register 3 buffer 87" "Not occurred,Occurred"
|
|
eventfld.long 0x18 22. " [86] ,Transfer to communication controller occurred register 3 buffer 86" "Not occurred,Occurred"
|
|
eventfld.long 0x18 21. " [85] ,Transfer to communication controller occurred register 3 buffer 85" "Not occurred,Occurred"
|
|
eventfld.long 0x18 20. " [84] ,Transfer to communication controller occurred register 3 buffer 84" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 19. " [83] ,Transfer to communication controller occurred register 3 buffer 83" "Not occurred,Occurred"
|
|
eventfld.long 0x18 18. " [82] ,Transfer to communication controller occurred register 3 buffer 82" "Not occurred,Occurred"
|
|
eventfld.long 0x18 17. " [81] ,Transfer to communication controller occurred register 3 buffer 81" "Not occurred,Occurred"
|
|
eventfld.long 0x18 16. " [80] ,Transfer to communication controller occurred register 3 buffer 80" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 15. " [79] ,Transfer to communication controller occurred register 3 buffer 79" "Not occurred,Occurred"
|
|
eventfld.long 0x18 14. " [78] ,Transfer to communication controller occurred register 3 buffer 78" "Not occurred,Occurred"
|
|
eventfld.long 0x18 13. " [77] ,Transfer to communication controller occurred register 3 buffer 77" "Not occurred,Occurred"
|
|
eventfld.long 0x18 12. " [76] ,Transfer to communication controller occurred register 3 buffer 76" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 11. " [75] ,Transfer to communication controller occurred register 3 buffer 75" "Not occurred,Occurred"
|
|
eventfld.long 0x18 10. " [74] ,Transfer to communication controller occurred register 3 buffer 74" "Not occurred,Occurred"
|
|
eventfld.long 0x18 9. " [73] ,Transfer to communication controller occurred register 3 buffer 73" "Not occurred,Occurred"
|
|
eventfld.long 0x18 8. " [72] ,Transfer to communication controller occurred register 3 buffer 72" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 7. " [71] ,Transfer to communication controller occurred register 3 buffer 71" "Not occurred,Occurred"
|
|
eventfld.long 0x18 6. " [70] ,Transfer to communication controller occurred register 3 buffer 70" "Not occurred,Occurred"
|
|
eventfld.long 0x18 5. " [69] ,Transfer to communication controller occurred register 3 buffer 69" "Not occurred,Occurred"
|
|
eventfld.long 0x18 4. " [68] ,Transfer to communication controller occurred register 3 buffer 68" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x18 3. " [67] ,Transfer to communication controller occurred register 3 buffer 67" "Not occurred,Occurred"
|
|
eventfld.long 0x18 2. " [66] ,Transfer to communication controller occurred register 3 buffer 66" "Not occurred,Occurred"
|
|
eventfld.long 0x18 1. " [65] ,Transfer to communication controller occurred register 3 buffer 65" "Not occurred,Occurred"
|
|
eventfld.long 0x18 0. " [64] ,Transfer to communication controller occurred register 3 buffer 64" "Not occurred,Occurred"
|
|
line.long 0x1C "TCCO4,Transfer to Communication Controller Occurred 4"
|
|
eventfld.long 0x1C 31. " TCCO4[127] ,Transfer to communication controller occurred register 4 buffer 127" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 30. " [126] ,Transfer to communication controller occurred register 4 buffer 126" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 29. " [125] ,Transfer to communication controller occurred register 4 buffer 125" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 28. " [124] ,Transfer to communication controller occurred register 4 buffer 124" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 27. " [123] ,Transfer to communication controller occurred register 4 buffer 123" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 26. " [122] ,Transfer to communication controller occurred register 4 buffer 122" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 25. " [121] ,Transfer to communication controller occurred register 4 buffer 121" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 24. " [120] ,Transfer to communication controller occurred register 4 buffer 120" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 23. " [119] ,Transfer to communication controller occurred register 4 buffer 119" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 22. " [118] ,Transfer to communication controller occurred register 4 buffer 118" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 21. " [117] ,Transfer to communication controller occurred register 4 buffer 117" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 20. " [116] ,Transfer to communication controller occurred register 4 buffer 116" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 19. " [115] ,Transfer to communication controller occurred register 4 buffer 115" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 18. " [114] ,Transfer to communication controller occurred register 4 buffer 114" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 17. " [113] ,Transfer to communication controller occurred register 4 buffer 113" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 16. " [112] ,Transfer to communication controller occurred register 4 buffer 112" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 15. " [111] ,Transfer to communication controller occurred register 4 buffer 111" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 14. " [110] ,Transfer to communication controller occurred register 4 buffer 110" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 13. " [109] ,Transfer to communication controller occurred register 4 buffer 109" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 12. " [108] ,Transfer to communication controller occurred register 4 buffer 108" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 11. " [107] ,Transfer to communication controller occurred register 4 buffer 107" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 10. " [106] ,Transfer to communication controller occurred register 4 buffer 106" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 9. " [105] ,Transfer to communication controller occurred register 4 buffer 105" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 8. " [104] ,Transfer to communication controller occurred register 4 buffer 104" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 7. " [103] ,Transfer to communication controller occurred register 4 buffer 103" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 6. " [102] ,Transfer to communication controller occurred register 4 buffer 102" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 5. " [101] ,Transfer to communication controller occurred register 4 buffer 101" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 4. " [100] ,Transfer to communication controller occurred register 4 buffer 100" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x1C 3. " [99] ,Transfer to communication controller occurred register 4 buffer 99" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 2. " [98] ,Transfer to communication controller occurred register 4 buffer 98" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 1. " [97] ,Transfer to communication controller occurred register 4 buffer 97" "Not occurred,Occurred"
|
|
eventfld.long 0x1C 0. " [96] ,Transfer to communication controller occurred register 4 buffer 96" "Not occurred,Occurred"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TOOFF,Transfer Occurred Offset"
|
|
bitfld.long 0x00 8. " TDIR ,Transfer direction" "System Memory,Communication Controller"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OFF ,Offset vector"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TOOFF,Transfer Occurred Offset"
|
|
in
|
|
endif
|
|
sif cpuis("TMS570LC4357")
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "TSBESTAT,TCR Single Bit Error Status"
|
|
in
|
|
endif
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "PEADR,Parity Error Address"
|
|
in
|
|
sif (cpuis("RM48L950*")||cpuis("TMS570LS2124-PGE")||cpuis("TMS570LS2124-ZWT")||cpuis("TMS570LS2134-PGE")||cpuis("TMS570LS2134-ZWT")||cpuis("TMS570LS3134-PGE")||cpuis("TMS570LS3134-ZWT")||cpuis("TMS570LS3135-PGE")||cpuis("TMS570LS3135-ZWT")||cpuis("TMS570LS3136")||cpuis("TMS570LS3137-PGE")||cpuis("TMS570LS3137-ZWT")||cpuis("TMS570LS30336")||cpuis("TMS570LS2126")||cpuis("TMS570LS2127")||cpuis("TMS570LS2136")||cpuis("TMS570LS2137")||cpuis("TMS570LS2125-PGE")||cpuis("TMS570LS2125-ZWT")||cpuis("TMS570LS2135-PGE")||cpuis("TMS570LS2135-ZWT")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "TEIR,Transfer Error Interrupt"
|
|
eventfld.long 0x00 17. " MPV ,Memory protection violation" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " PE ,Parity/ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSTAT ,Read error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " WSTAT ,Write error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,,Unsupported addr,,Exclusive write"
|
|
newline
|
|
eventfld.long 0x00 1. " TNR ,Transfer not ready" "Ready,Not ready"
|
|
eventfld.long 0x00 0. " FAC ,Forbidden access" "No forbidden,Forbidden"
|
|
line.long 0x04 "TEIRE,Transfer Error Interrupt Enable Set"
|
|
bitfld.long 0x04 8.--10. " RSTATE ,Read error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " WSTATE ,Write error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive write"
|
|
newline
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " TNRE_SET/CLR ,Transfer not ready enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " FACE_SET/CLR ,Forbidden access enable" "Disabled,Enabled"
|
|
line.long 0x08 "TEIRER,Transfer Error Interrupt Enable Reset"
|
|
bitfld.long 0x08 8.--10. " RSTATE ,Read error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " WSTATE ,Write error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive write"
|
|
elif cpuis("TMS570LC4357")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "TEIR,Transfer Error Interrupt"
|
|
eventfld.long 0x00 17. " MPV ,Memory protection violation" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " PE ,Parity/ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSTAT ,Read error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " WSTAT ,Write error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,,Unsupported addr,,Exclusive write"
|
|
newline
|
|
eventfld.long 0x00 1. " TNR ,Transfer not ready" "Ready,Not ready"
|
|
eventfld.long 0x00 0. " FAC ,Forbidden access" "Not occurred,Occurred"
|
|
line.long 0x04 "TEIRES,Transfer Error InterRupt Enable Set"
|
|
bitfld.long 0x04 8.--10. " RSTATE ,Read error interrupt generation" "Disabled,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " WSTATE ,Write error interrupt generation" "Disabled,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " TNRE_SET/CLR ,Transfer not ready enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " FACE_SET/CLR ,Forbidden access enable" "Disabled,Enabled"
|
|
line.long 0x08 "TEIRER,Transfer Error InterRupt Enable Reset"
|
|
bitfld.long 0x08 8.--10. " RSTATE ,Read error interrupt generation" "Disabled,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " WSTATE ,Write error interrupt generation" "Disabled,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Not guaranteed,Enabled"
|
|
else
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "TEIR,Transfer Error Interrupt"
|
|
eventfld.long 0x00 17. " MPV ,Memory protection violation" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " PE ,Parity/ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSTAT ,Read error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " WSTAT ,Write error status of transfer unit state machine" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive write"
|
|
newline
|
|
eventfld.long 0x00 1. " TNR ,Transfer not ready" "Ready,Not ready"
|
|
eventfld.long 0x00 0. " FAC ,Forbidden Access" "No forbidden,Forbidden"
|
|
line.long 0x04 "TEIRES,Transfer Error InterRupt Enable Set"
|
|
bitfld.long 0x04 8.--10. " RSTATE ,Read error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " WSTATE ,Write error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive write"
|
|
newline
|
|
bitfld.long 0x04 1. " TNRE_set ,Transfer not ready enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " FACE_set ,Forbidden Access Enable" "Disabled,Enabled"
|
|
line.long 0x08 "TEIRER,Transfer Error InterRupt Enable Reset"
|
|
bitfld.long 0x08 8.--10. " RSTATE ,Read error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive read"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " WSTATE ,Write error transfer interrupt generation" "Success,Addressing,Protection,Timeout,Data,Unsupported addr,,Exclusive write"
|
|
newline
|
|
bitfld.long 0x08 1. " TNRE_clr ,Transfer not ready enable" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " FACE_clr ,Forbidden access enable" "No effect,Cleared"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TTSMS/R1_SET/CLR,Trigger Transfer to System Memory Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R1[31] ,Trigger transfer to system memory set/reset 1 buffer 31" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger transfer to system memory set/reset 1 buffer 30" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger transfer to system memory set/reset 1 buffer 29" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger transfer to system memory set/reset 1 buffer 28" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger transfer to system memory set/reset 1 buffer 27" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger transfer to system memory set/reset 1 buffer 26" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger transfer to system memory set/reset 1 buffer 25" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger transfer to system memory set/reset 1 buffer 24" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger transfer to system memory set/reset 1 buffer 23" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger transfer to system memory set/reset 1 buffer 22" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger transfer to system memory set/reset 1 buffer 21" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger transfer to system memory set/reset 1 buffer 20" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger transfer to system memory set/reset 1 buffer 19" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger transfer to system memory set/reset 1 buffer 18" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger transfer to system memory set/reset 1 buffer 17" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger transfer to system memory set/reset 1 buffer 16" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger transfer to system memory set/reset 1 buffer 15" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger transfer to system memory set/reset 1 buffer 14" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger transfer to system memory set/reset 1 buffer 13" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger transfer to system memory set/reset 1 buffer 12" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger transfer to system memory set/reset 1 buffer 11" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger transfer to system memory set/reset 1 buffer 10" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger transfer to system memory set/reset 1 buffer 9" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger transfer to system memory set/reset 1 buffer 8" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger transfer to system memory set/reset 1 buffer 7" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger transfer to system memory set/reset 1 buffer 6" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger transfer to system memory set/reset 1 buffer 5" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger transfer to system memory set/reset 1 buffer 4" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger transfer to system memory set/reset 1 buffer 3" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger transfer to system memory set/reset 1 buffer 2" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger transfer to system memory set/reset 1 buffer 1" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger transfer to system memory set/reset 1 buffer 0" "Not requested,Requested"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TTSMS/R2_SET/CLR,Trigger Transfer to System Memory Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R2[63] ,Trigger transfer to system memory set/reset 2 buffer 63" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Trigger transfer to system memory set/reset 2 buffer 62" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Trigger transfer to system memory set/reset 2 buffer 61" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Trigger transfer to system memory set/reset 2 buffer 60" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Trigger transfer to system memory set/reset 2 buffer 59" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Trigger transfer to system memory set/reset 2 buffer 58" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Trigger transfer to system memory set/reset 2 buffer 57" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Trigger transfer to system memory set/reset 2 buffer 56" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Trigger transfer to system memory set/reset 2 buffer 55" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Trigger transfer to system memory set/reset 2 buffer 54" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Trigger transfer to system memory set/reset 2 buffer 53" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Trigger transfer to system memory set/reset 2 buffer 52" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Trigger transfer to system memory set/reset 2 buffer 51" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Trigger transfer to system memory set/reset 2 buffer 50" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Trigger transfer to system memory set/reset 2 buffer 49" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Trigger transfer to system memory set/reset 2 buffer 48" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Trigger transfer to system memory set/reset 2 buffer 47" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Trigger transfer to system memory set/reset 2 buffer 46" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Trigger transfer to system memory set/reset 2 buffer 45" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Trigger transfer to system memory set/reset 2 buffer 44" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Trigger transfer to system memory set/reset 2 buffer 43" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Trigger transfer to system memory set/reset 2 buffer 42" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Trigger transfer to system memory set/reset 2 buffer 41" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Trigger transfer to system memory set/reset 2 buffer 40" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Trigger transfer to system memory set/reset 2 buffer 39" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Trigger transfer to system memory set/reset 2 buffer 38" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Trigger transfer to system memory set/reset 2 buffer 37" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Trigger transfer to system memory set/reset 2 buffer 36" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Trigger transfer to system memory set/reset 2 buffer 35" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Trigger transfer to system memory set/reset 2 buffer 34" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Trigger transfer to system memory set/reset 2 buffer 33" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Trigger transfer to system memory set/reset 2 buffer 32" "Not requested,Requested"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TTSMS/R3_SET/CLR,Trigger Transfer to System Memory Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R3[95] ,Trigger transfer to system memory set/reset 3 buffer 95" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Trigger transfer to system memory set/reset 3 buffer 94" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Trigger transfer to system memory set/reset 3 buffer 93" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Trigger transfer to system memory set/reset 3 buffer 92" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Trigger transfer to system memory set/reset 3 buffer 91" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Trigger transfer to system memory set/reset 3 buffer 90" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Trigger transfer to system memory set/reset 3 buffer 89" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Trigger transfer to system memory set/reset 3 buffer 88" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Trigger transfer to system memory set/reset 3 buffer 87" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Trigger transfer to system memory set/reset 3 buffer 86" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Trigger transfer to system memory set/reset 3 buffer 85" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Trigger transfer to system memory set/reset 3 buffer 84" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Trigger transfer to system memory set/reset 3 buffer 83" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Trigger transfer to system memory set/reset 3 buffer 82" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Trigger transfer to system memory set/reset 3 buffer 81" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Trigger transfer to system memory set/reset 3 buffer 80" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Trigger transfer to system memory set/reset 3 buffer 79" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Trigger transfer to system memory set/reset 3 buffer 78" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Trigger transfer to system memory set/reset 3 buffer 77" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Trigger transfer to system memory set/reset 3 buffer 76" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Trigger transfer to system memory set/reset 3 buffer 75" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Trigger transfer to system memory set/reset 3 buffer 74" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Trigger transfer to system memory set/reset 3 buffer 73" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Trigger transfer to system memory set/reset 3 buffer 72" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Trigger transfer to system memory set/reset 3 buffer 71" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Trigger transfer to system memory set/reset 3 buffer 70" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Trigger transfer to system memory set/reset 3 buffer 69" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Trigger transfer to system memory set/reset 3 buffer 68" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Trigger transfer to system memory set/reset 3 buffer 67" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Trigger transfer to system memory set/reset 3 buffer 66" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Trigger transfer to system memory set/reset 3 buffer 65" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Trigger transfer to system memory set/reset 3 buffer 64" "Not requested,Requested"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TTSMS/R4_SET/CLR,Trigger Transfer to System Memory Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R4[127]_SET/CLR ,Trigger transfer to system memory set/reset 4 buffer 127" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Trigger transfer to system memory set/reset 4 buffer 126" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Trigger transfer to system memory set/reset 4 buffer 125" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Trigger transfer to system memory set/reset 4 buffer 124" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Trigger transfer to system memory set/reset 4 buffer 123" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Trigger transfer to system memory set/reset 4 buffer 122" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Trigger transfer to system memory set/reset 4 buffer 121" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Trigger transfer to system memory set/reset 4 buffer 120" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Trigger transfer to system memory set/reset 4 buffer 119" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Trigger transfer to system memory set/reset 4 buffer 118" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Trigger transfer to system memory set/reset 4 buffer 117" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Trigger transfer to system memory set/reset 4 buffer 116" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Trigger transfer to system memory set/reset 4 buffer 115" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Trigger transfer to system memory set/reset 4 buffer 114" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Trigger transfer to system memory set/reset 4 buffer 113" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Trigger transfer to system memory set/reset 4 buffer 112" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Trigger transfer to system memory set/reset 4 buffer 111" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Trigger transfer to system memory set/reset 4 buffer 110" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Trigger transfer to system memory set/reset 4 buffer 109" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Trigger transfer to system memory set/reset 4 buffer 108" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Trigger transfer to system memory set/reset 4 buffer 107" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Trigger transfer to system memory set/reset 4 buffer 106" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Trigger transfer to system memory set/reset 4 buffer 105" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Trigger transfer to system memory set/reset 4 buffer 104" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Trigger transfer to system memory set/reset 4 buffer 103" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Trigger transfer to system memory set/reset 4 buffer 102" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Trigger transfer to system memory set/reset 4 buffer 101" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [100] ,Trigger transfer to system memory set/reset 4 buffer 100" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [99] ,Trigger transfer to system memory set/reset 4 buffer 99" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [98] ,Trigger transfer to system memory set/reset 4 buffer 98" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [97] ,Trigger transfer to system memory set/reset 4 buffer 97" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [96] ,Trigger transfer to system memory set/reset 4 buffer 96" "Not requested,Requested"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TTCCS/R1_SET/CLR,Trigger Transfer to Communication Controller Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R1[31] ,Trigger transfer to communication controller set/reset 1 buffer 31" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger transfer to communication controller set/reset 1 buffer 30" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger transfer to communication controller set/reset 1 buffer 29" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger transfer to communication controller set/reset 1 buffer 28" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger transfer to communication controller set/reset 1 buffer 27" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger transfer to communication controller set/reset 1 buffer 26" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger transfer to communication controller set/reset 1 buffer 25" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger transfer to communication controller set/reset 1 buffer 24" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger transfer to communication controller set/reset 1 buffer 23" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger transfer to communication controller set/reset 1 buffer 22" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger transfer to communication controller set/reset 1 buffer 21" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger transfer to communication controller set/reset 1 buffer 20" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger transfer to communication controller set/reset 1 buffer 19" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger transfer to communication controller set/reset 1 buffer 18" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger transfer to communication controller set/reset 1 buffer 17" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger transfer to communication controller set/reset 1 buffer 16" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger transfer to communication controller set/reset 1 buffer 15" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger transfer to communication controller set/reset 1 buffer 14" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger transfer to communication controller set/reset 1 buffer 13" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger transfer to communication controller set/reset 1 buffer 12" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger transfer to communication controller set/reset 1 buffer 11" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger transfer to communication controller set/reset 1 buffer 10" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger transfer to communication controller set/reset 1 buffer 9" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger transfer to communication controller set/reset 1 buffer 8" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger transfer to communication controller set/reset 1 buffer 7" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger transfer to communication controller set/reset 1 buffer 6" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger transfer to communication controller set/reset 1 buffer 5" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger transfer to communication controller set/reset 1 buffer 4" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger transfer to communication controller set/reset 1 buffer 3" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger transfer to communication controller set/reset 1 buffer 2" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger transfer to communication controller set/reset 1 buffer 1" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger transfer to communication controller set/reset 1 buffer 0" "Not requested,Requested"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TTCCS/R2_SET/CLR,Trigger Transfer to Communication Controller Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R2[63] ,Trigger transfer to communication controller set/reset 2 buffer 63" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Trigger transfer to communication controller set/reset 2 buffer 62" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Trigger transfer to communication controller set/reset 2 buffer 61" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Trigger transfer to communication controller set/reset 2 buffer 60" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Trigger transfer to communication controller set/reset 2 buffer 59" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Trigger transfer to communication controller set/reset 2 buffer 58" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Trigger transfer to communication controller set/reset 2 buffer 57" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Trigger transfer to communication controller set/reset 2 buffer 56" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Trigger transfer to communication controller set/reset 2 buffer 55" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Trigger transfer to communication controller set/reset 2 buffer 54" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Trigger transfer to communication controller set/reset 2 buffer 53" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Trigger transfer to communication controller set/reset 2 buffer 52" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Trigger transfer to communication controller set/reset 2 buffer 51" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Trigger transfer to communication controller set/reset 2 buffer 50" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Trigger transfer to communication controller set/reset 2 buffer 49" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Trigger transfer to communication controller set/reset 2 buffer 48" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Trigger transfer to communication controller set/reset 2 buffer 47" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Trigger transfer to communication controller set/reset 2 buffer 46" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Trigger transfer to communication controller set/reset 2 buffer 45" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Trigger transfer to communication controller set/reset 2 buffer 44" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Trigger transfer to communication controller set/reset 2 buffer 43" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Trigger transfer to communication controller set/reset 2 buffer 42" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Trigger transfer to communication controller set/reset 2 buffer 41" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Trigger transfer to communication controller set/reset 2 buffer 40" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Trigger transfer to communication controller set/reset 2 buffer 39" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Trigger transfer to communication controller set/reset 2 buffer 38" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Trigger transfer to communication controller set/reset 2 buffer 37" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Trigger transfer to communication controller set/reset 2 buffer 36" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Trigger transfer to communication controller set/reset 2 buffer 35" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Trigger transfer to communication controller set/reset 2 buffer 34" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Trigger transfer to communication controller set/reset 2 buffer 33" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Trigger transfer to communication controller set/reset 2 buffer 32" "Not requested,Requested"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TTCCS/R3_SET/CLR,Trigger Transfer to Communication Controller Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R3[95] ,Trigger transfer to communication controller set/reset 3 buffer 95" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Trigger transfer to communication controller set/reset 3 buffer 94" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Trigger transfer to communication controller set/reset 3 buffer 93" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Trigger transfer to communication controller set/reset 3 buffer 92" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Trigger transfer to communication controller set/reset 3 buffer 91" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Trigger transfer to communication controller set/reset 3 buffer 90" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Trigger transfer to communication controller set/reset 3 buffer 89" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Trigger transfer to communication controller set/reset 3 buffer 88" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Trigger transfer to communication controller set/reset 3 buffer 87" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Trigger transfer to communication controller set/reset 3 buffer 86" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Trigger transfer to communication controller set/reset 3 buffer 85" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Trigger transfer to communication controller set/reset 3 buffer 84" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Trigger transfer to communication controller set/reset 3 buffer 83" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Trigger transfer to communication controller set/reset 3 buffer 82" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Trigger transfer to communication controller set/reset 3 buffer 81" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Trigger transfer to communication controller set/reset 3 buffer 80" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Trigger transfer to communication controller set/reset 3 buffer 79" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Trigger transfer to communication controller set/reset 3 buffer 78" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Trigger transfer to communication controller set/reset 3 buffer 77" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Trigger transfer to communication controller set/reset 3 buffer 76" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Trigger transfer to communication controller set/reset 3 buffer 75" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Trigger transfer to communication controller set/reset 3 buffer 74" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Trigger transfer to communication controller set/reset 3 buffer 73" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Trigger transfer to communication controller set/reset 3 buffer 72" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Trigger transfer to communication controller set/reset 3 buffer 71" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Trigger transfer to communication controller set/reset 3 buffer 70" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Trigger transfer to communication controller set/reset 3 buffer 69" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Trigger transfer to communication controller set/reset 3 buffer 68" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Trigger transfer to communication controller set/reset 3 buffer 67" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Trigger transfer to communication controller set/reset 3 buffer 66" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Trigger transfer to communication controller set/reset 3 buffer 65" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Trigger transfer to communication controller set/reset 3 buffer 64" "Not requested,Requested"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TTCCS/R4_SET/CLR,Trigger Transfer to Communication Controller Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R4[127] ,Trigger transfer to communication controller set/reset 4 buffer 127" "Not requested,Requested"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Trigger transfer to communication controller set/reset 4 buffer 126" "Not requested,Requested"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Trigger transfer to communication controller set/reset 4 buffer 125" "Not requested,Requested"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Trigger transfer to communication controller set/reset 4 buffer 124" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Trigger transfer to communication controller set/reset 4 buffer 123" "Not requested,Requested"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Trigger transfer to communication controller set/reset 4 buffer 122" "Not requested,Requested"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Trigger transfer to communication controller set/reset 4 buffer 121" "Not requested,Requested"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Trigger transfer to communication controller set/reset 4 buffer 120" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Trigger transfer to communication controller set/reset 4 buffer 119" "Not requested,Requested"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Trigger transfer to communication controller set/reset 4 buffer 118" "Not requested,Requested"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Trigger transfer to communication controller set/reset 4 buffer 117" "Not requested,Requested"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Trigger transfer to communication controller set/reset 4 buffer 116" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Trigger transfer to communication controller set/reset 4 buffer 115" "Not requested,Requested"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Trigger transfer to communication controller set/reset 4 buffer 114" "Not requested,Requested"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Trigger transfer to communication controller set/reset 4 buffer 113" "Not requested,Requested"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Trigger transfer to communication controller set/reset 4 buffer 112" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Trigger transfer to communication controller set/reset 4 buffer 111" "Not requested,Requested"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Trigger transfer to communication controller set/reset 4 buffer 110" "Not requested,Requested"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Trigger transfer to communication controller set/reset 4 buffer 109" "Not requested,Requested"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Trigger transfer to communication controller set/reset 4 buffer 108" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Trigger transfer to communication controller set/reset 4 buffer 107" "Not requested,Requested"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Trigger transfer to communication controller set/reset 4 buffer 106" "Not requested,Requested"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Trigger transfer to communication controller set/reset 4 buffer 105" "Not requested,Requested"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Trigger transfer to communication controller set/reset 4 buffer 104" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Trigger transfer to communication controller set/reset 4 buffer 103" "Not requested,Requested"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Trigger transfer to communication controller set/reset 4 buffer 102" "Not requested,Requested"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Trigger transfer to communication controller set/reset 4 buffer 101" "Not requested,Requested"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [99] ,Trigger transfer to communication controller set/reset 4 buffer 100" "Not requested,Requested"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [98] ,Trigger transfer to communication controller set/reset 4 buffer 99" "Not requested,Requested"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [97] ,Trigger transfer to communication controller set/reset 4 buffer 98" "Not requested,Requested"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [96] ,Trigger transfer to communication controller set/reset 4 buffer 97" "Not requested,Requested"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [95] ,Trigger transfer to communication controller set/reset 4 buffer 96" "Not requested,Requested"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "ETESMS/R1_SET/CLR,Enable Transfer on Event to System Memory Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R1[31] ,Enable transfer on event to system memory set/reset 1 buffer 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Enable transfer on event to system memory set/reset 1 buffer 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Enable transfer on event to system memory set/reset 1 buffer 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Enable transfer on event to system memory set/reset 1 buffer 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Enable transfer on event to system memory set/reset 1 buffer 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Enable transfer on event to system memory set/reset 1 buffer 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Enable transfer on event to system memory set/reset 1 buffer 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Enable transfer on event to system memory set/reset 1 buffer 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Enable transfer on event to system memory set/reset 1 buffer 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Enable transfer on event to system memory set/reset 1 buffer 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Enable transfer on event to system memory set/reset 1 buffer 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Enable transfer on event to system memory set/reset 1 buffer 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Enable transfer on event to system memory set/reset 1 buffer 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Enable transfer on event to system memory set/reset 1 buffer 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Enable transfer on event to system memory set/reset 1 buffer 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Enable transfer on event to system memory set/reset 1 buffer 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Enable transfer on event to system memory set/reset 1 buffer 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Enable transfer on event to system memory set/reset 1 buffer 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Enable transfer on event to system memory set/reset 1 buffer 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Enable transfer on event to system memory set/reset 1 buffer 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Enable transfer on event to system memory set/reset 1 buffer 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Enable transfer on event to system memory set/reset 1 buffer 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Enable transfer on event to system memory set/reset 1 buffer 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Enable transfer on event to system memory set/reset 1 buffer 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Enable transfer on event to system memory set/reset 1 buffer 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Enable transfer on event to system memory set/reset 1 buffer 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Enable transfer on event to system memory set/reset 1 buffer 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Enable transfer on event to system memory set/reset 1 buffer 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Enable transfer on event to system memory set/reset 1 buffer 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Enable transfer on event to system memory set/reset 1 buffer 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Enable transfer on event to system memory set/reset 1 buffer 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Enable transfer on event to system memory set/reset 1 buffer 0" "Disabled,Enabled"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ETESMS/R2_SET/CLR,Enable Transfer on Event to System Memory Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R2[63] ,Enable transfer on event to system memory set/reset 2 buffer 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Enable transfer on event to system memory set/reset 2 buffer 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Enable transfer on event to system memory set/reset 2 buffer 61" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Enable transfer on event to system memory set/reset 2 buffer 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Enable transfer on event to system memory set/reset 2 buffer 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Enable transfer on event to system memory set/reset 2 buffer 58" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Enable transfer on event to system memory set/reset 2 buffer 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Enable transfer on event to system memory set/reset 2 buffer 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Enable transfer on event to system memory set/reset 2 buffer 55" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Enable transfer on event to system memory set/reset 2 buffer 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Enable transfer on event to system memory set/reset 2 buffer 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Enable transfer on event to system memory set/reset 2 buffer 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Enable transfer on event to system memory set/reset 2 buffer 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Enable transfer on event to system memory set/reset 2 buffer 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Enable transfer on event to system memory set/reset 2 buffer 49" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Enable transfer on event to system memory set/reset 2 buffer 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Enable transfer on event to system memory set/reset 2 buffer 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Enable transfer on event to system memory set/reset 2 buffer 46" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Enable transfer on event to system memory set/reset 2 buffer 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Enable transfer on event to system memory set/reset 2 buffer 44" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Enable transfer on event to system memory set/reset 2 buffer 43" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Enable transfer on event to system memory set/reset 2 buffer 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Enable transfer on event to system memory set/reset 2 buffer 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Enable transfer on event to system memory set/reset 2 buffer 40" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Enable transfer on event to system memory set/reset 2 buffer 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Enable transfer on event to system memory set/reset 2 buffer 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Enable transfer on event to system memory set/reset 2 buffer 37" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Enable transfer on event to system memory set/reset 2 buffer 36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Enable transfer on event to system memory set/reset 2 buffer 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Enable transfer on event to system memory set/reset 2 buffer 34" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Enable transfer on event to system memory set/reset 2 buffer 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Enable transfer on event to system memory set/reset 2 buffer 32" "Disabled,Enabled"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "ETESMS/R3_SET/CLR,Enable Transfer on Event to System Memory Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R3[95] ,Enable transfer on event to system memory set/reset 3 buffer 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Enable transfer on event to system memory set/reset 3 buffer 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Enable transfer on event to system memory set/reset 3 buffer 93" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Enable transfer on event to system memory set/reset 3 buffer 92" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Enable transfer on event to system memory set/reset 3 buffer 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Enable transfer on event to system memory set/reset 3 buffer 90" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Enable transfer on event to system memory set/reset 3 buffer 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Enable transfer on event to system memory set/reset 3 buffer 88" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Enable transfer on event to system memory set/reset 3 buffer 87" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Enable transfer on event to system memory set/reset 3 buffer 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Enable transfer on event to system memory set/reset 3 buffer 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Enable transfer on event to system memory set/reset 3 buffer 84" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Enable transfer on event to system memory set/reset 3 buffer 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Enable transfer on event to system memory set/reset 3 buffer 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Enable transfer on event to system memory set/reset 3 buffer 81" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Enable transfer on event to system memory set/reset 3 buffer 80" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Enable transfer on event to system memory set/reset 3 buffer 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Enable transfer on event to system memory set/reset 3 buffer 78" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Enable transfer on event to system memory set/reset 3 buffer 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Enable transfer on event to system memory set/reset 3 buffer 76" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Enable transfer on event to system memory set/reset 3 buffer 75" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Enable transfer on event to system memory set/reset 3 buffer 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Enable transfer on event to system memory set/reset 3 buffer 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Enable transfer on event to system memory set/reset 3 buffer 72" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Enable transfer on event to system memory set/reset 3 buffer 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Enable transfer on event to system memory set/reset 3 buffer 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Enable transfer on event to system memory set/reset 3 buffer 69" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Enable transfer on event to system memory set/reset 3 buffer 68" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Enable transfer on event to system memory set/reset 3 buffer 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Enable transfer on event to system memory set/reset 3 buffer 66" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Enable transfer on event to system memory set/reset 3 buffer 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Enable transfer on event to system memory set/reset 3 buffer 64" "Disabled,Enabled"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "ETESMS/R4_SET/CLR,Enable Transfer on Event to System Memory Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R4[127] ,Enable transfer on event to system memory set/reset 4 buffer 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Enable transfer on event to system memory set/reset 4 buffer 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Enable transfer on event to system memory set/reset 4 buffer 125" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Enable transfer on event to system memory set/reset 4 buffer 124" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Enable transfer on event to system memory set/reset 4 buffer 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Enable transfer on event to system memory set/reset 4 buffer 122" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Enable transfer on event to system memory set/reset 4 buffer 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Enable transfer on event to system memory set/reset 4 buffer 120" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Enable transfer on event to system memory set/reset 4 buffer 119" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Enable transfer on event to system memory set/reset 4 buffer 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Enable transfer on event to system memory set/reset 4 buffer 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Enable transfer on event to system memory set/reset 4 buffer 116" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Enable transfer on event to system memory set/reset 4 buffer 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Enable transfer on event to system memory set/reset 4 buffer 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Enable transfer on event to system memory set/reset 4 buffer 113" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Enable transfer on event to system memory set/reset 4 buffer 112" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Enable transfer on event to system memory set/reset 4 buffer 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Enable transfer on event to system memory set/reset 4 buffer 110" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Enable transfer on event to system memory set/reset 4 buffer 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Enable transfer on event to system memory set/reset 4 buffer 108" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Enable transfer on event to system memory set/reset 4 buffer 107" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Enable transfer on event to system memory set/reset 4 buffer 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Enable transfer on event to system memory set/reset 4 buffer 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Enable transfer on event to system memory set/reset 4 buffer 104" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Enable transfer on event to system memory set/reset 4 buffer 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Enable transfer on event to system memory set/reset 4 buffer 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Enable transfer on event to system memory set/reset 4 buffer 101" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [100] ,Enable transfer on event to system memory set/reset 4 buffer 100" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [99] ,Enable transfer on event to system memory set/reset 4 buffer 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [98] ,Enable transfer on event to system memory set/reset 4 buffer 98" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [97] ,Enable transfer on event to system memory set/reset 4 buffer 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [96] ,Enable transfer on event to system memory set/reset 4 buffer 96" "Disabled,Enabled"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CESMS/R1_SET/CLR,Clear on Event to System Memory Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R1[31] ,Clear on event to system memory set/reset 1 buffer 31" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Clear on event to system memory set/reset 1 buffer 30" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Clear on event to system memory set/reset 1 buffer 29" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Clear on event to system memory set/reset 1 buffer 28" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Clear on event to system memory set/reset 1 buffer 27" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Clear on event to system memory set/reset 1 buffer 26" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Clear on event to system memory set/reset 1 buffer 25" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Clear on event to system memory set/reset 1 buffer 24" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Clear on event to system memory set/reset 1 buffer 23" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Clear on event to system memory set/reset 1 buffer 22" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Clear on event to system memory set/reset 1 buffer 21" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Clear on event to system memory set/reset 1 buffer 20" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Clear on event to system memory set/reset 1 buffer 19" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Clear on event to system memory set/reset 1 buffer 18" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Clear on event to system memory set/reset 1 buffer 17" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Clear on event to system memory set/reset 1 buffer 16" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Clear on event to system memory set/reset 1 buffer 15" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Clear on event to system memory set/reset 1 buffer 14" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Clear on event to system memory set/reset 1 buffer 13" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Clear on event to system memory set/reset 1 buffer 12" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Clear on event to system memory set/reset 1 buffer 11" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Clear on event to system memory set/reset 1 buffer 10" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Clear on event to system memory set/reset 1 buffer 9" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Clear on event to system memory set/reset 1 buffer 8" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Clear on event to system memory set/reset 1 buffer 7" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Clear on event to system memory set/reset 1 buffer 6" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Clear on event to system memory set/reset 1 buffer 5" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Clear on event to system memory set/reset 1 buffer 4" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Clear on event to system memory set/reset 1 buffer 3" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Clear on event to system memory set/reset 1 buffer 2" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Clear on event to system memory set/reset 1 buffer 1" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Clear on event to system memory set/reset 1 buffer 0" "Not cleared,Cleared"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CESMS/R2_SET/CLR,Clear on Event to System Memory Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R2[63] ,Clear on event to system memory set/reset 2 buffer 63" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Clear on event to system memory set/reset 2 buffer 62" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Clear on event to system memory set/reset 2 buffer 61" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Clear on event to system memory set/reset 2 buffer 60" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Clear on event to system memory set/reset 2 buffer 59" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Clear on event to system memory set/reset 2 buffer 58" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Clear on event to system memory set/reset 2 buffer 57" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Clear on event to system memory set/reset 2 buffer 56" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Clear on event to system memory set/reset 2 buffer 55" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Clear on event to system memory set/reset 2 buffer 54" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Clear on event to system memory set/reset 2 buffer 53" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Clear on event to system memory set/reset 2 buffer 52" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Clear on event to system memory set/reset 2 buffer 51" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Clear on event to system memory set/reset 2 buffer 50" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Clear on event to system memory set/reset 2 buffer 49" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Clear on event to system memory set/reset 2 buffer 48" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Clear on event to system memory set/reset 2 buffer 47" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Clear on event to system memory set/reset 2 buffer 46" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Clear on event to system memory set/reset 2 buffer 45" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Clear on event to system memory set/reset 2 buffer 44" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Clear on event to system memory set/reset 2 buffer 43" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Clear on event to system memory set/reset 2 buffer 42" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Clear on event to system memory set/reset 2 buffer 41" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Clear on event to system memory set/reset 2 buffer 40" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Clear on event to system memory set/reset 2 buffer 39" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Clear on event to system memory set/reset 2 buffer 38" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Clear on event to system memory set/reset 2 buffer 37" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Clear on event to system memory set/reset 2 buffer 36" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Clear on event to system memory set/reset 2 buffer 35" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Clear on event to system memory set/reset 2 buffer 34" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Clear on event to system memory set/reset 2 buffer 33" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Clear on event to system memory set/reset 2 buffer 32" "Not cleared,Cleared"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CESMS/R3_SET/CLR,Clear on Event to System Memory Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R3[95] ,Clear on event to system memory set/reset 3 buffer 95" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Clear on event to system memory set/reset 3 buffer 94" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Clear on event to system memory set/reset 3 buffer 93" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Clear on event to system memory set/reset 3 buffer 92" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Clear on event to system memory set/reset 3 buffer 91" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Clear on event to system memory set/reset 3 buffer 90" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Clear on event to system memory set/reset 3 buffer 89" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Clear on event to system memory set/reset 3 buffer 88" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Clear on event to system memory set/reset 3 buffer 87" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Clear on event to system memory set/reset 3 buffer 86" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Clear on event to system memory set/reset 3 buffer 85" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Clear on event to system memory set/reset 3 buffer 84" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Clear on event to system memory set/reset 3 buffer 83" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Clear on event to system memory set/reset 3 buffer 82" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Clear on event to system memory set/reset 3 buffer 81" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Clear on event to system memory set/reset 3 buffer 80" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Clear on event to system memory set/reset 3 buffer 79" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Clear on event to system memory set/reset 3 buffer 78" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Clear on event to system memory set/reset 3 buffer 77" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Clear on event to system memory set/reset 3 buffer 76" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Clear on event to system memory set/reset 3 buffer 75" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Clear on event to system memory set/reset 3 buffer 74" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Clear on event to system memory set/reset 3 buffer 73" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Clear on event to system memory set/reset 3 buffer 72" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Clear on event to system memory set/reset 3 buffer 71" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Clear on event to system memory set/reset 3 buffer 70" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Clear on event to system memory set/reset 3 buffer 69" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Clear on event to system memory set/reset 3 buffer 68" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Clear on event to system memory set/reset 3 buffer 67" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Clear on event to system memory set/reset 3 buffer 66" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Clear on event to system memory set/reset 3 buffer 65" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Clear on event to system memory set/reset 3 buffer 64" "Not cleared,Cleared"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CESMS/R4_SET/CLR,Clear on Event to System Memory Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R4[127] ,Clear on event to system memory set/reset 4 buffer 127" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Clear on event to system memory set/reset 4 buffer 126" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Clear on event to system memory set/reset 4 buffer 125" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Clear on event to system memory set/reset 4 buffer 124" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Clear on event to system memory set/reset 4 buffer 123" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Clear on event to system memory set/reset 4 buffer 122" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Clear on event to system memory set/reset 4 buffer 121" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Clear on event to system memory set/reset 4 buffer 120" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Clear on event to system memory set/reset 4 buffer 119" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Clear on event to system memory set/reset 4 buffer 118" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Clear on event to system memory set/reset 4 buffer 117" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Clear on event to system memory set/reset 4 buffer 116" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Clear on event to system memory set/reset 4 buffer 115" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Clear on event to system memory set/reset 4 buffer 114" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Clear on event to system memory set/reset 4 buffer 113" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Clear on event to system memory set/reset 4 buffer 112" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Clear on event to system memory set/reset 4 buffer 111" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Clear on event to system memory set/reset 4 buffer 110" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Clear on event to system memory set/reset 4 buffer 109" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Clear on event to system memory set/reset 4 buffer 108" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Clear on event to system memory set/reset 4 buffer 107" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Clear on event to system memory set/reset 4 buffer 106" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Clear on event to system memory set/reset 4 buffer 105" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Clear on event to system memory set/reset 4 buffer 104" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Clear on event to system memory set/reset 4 buffer 103" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Clear on event to system memory set/reset 4 buffer 102" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Clear on event to system memory set/reset 4 buffer 101" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [100] ,Clear on event to system memory set/reset 4 buffer 100" "Not cleared,Cleared"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [99] ,Clear on event to system memory set/reset 4 buffer 99" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [98] ,Clear on event to system memory set/reset 4 buffer 98" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [97] ,Clear on event to system memory set/reset 4 buffer 97" "Not cleared,Cleared"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [96] ,Clear on event to system memory set/reset 4 buffer 96" "Not cleared,Cleared"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSMIES/R1_SET/CLR,Transfer to System Memory Interrupt Enable Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R1[31] ,Transfer to system memory interrupt enable set/reset 1 buffer 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to system memory interrupt enable set/reset 1 buffer 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to system memory interrupt enable set/reset 1 buffer 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to system memory interrupt enable set/reset 1 buffer 28" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to system memory interrupt enable set/reset 1 buffer 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to system memory interrupt enable set/reset 1 buffer 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to system memory interrupt enable set/reset 1 buffer 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to system memory interrupt enable set/reset 1 buffer 24" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to system memory interrupt enable set/reset 1 buffer 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to system memory interrupt enable set/reset 1 buffer 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to system memory interrupt enable set/reset 1 buffer 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to system memory interrupt enable set/reset 1 buffer 20" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to system memory interrupt enable set/reset 1 buffer 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to system memory interrupt enable set/reset 1 buffer 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to system memory interrupt enable set/reset 1 buffer 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to system memory interrupt enable set/reset 1 buffer 16" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to system memory interrupt enable set/reset 1 buffer 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to system memory interrupt enable set/reset 1 buffer 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to system memory interrupt enable set/reset 1 buffer 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to system memory interrupt enable set/reset 1 buffer 12" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to system memory interrupt enable set/reset 1 buffer 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to system memory interrupt enable set/reset 1 buffer 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to system memory interrupt enable set/reset 1 buffer 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to system memory interrupt enable set/reset 1 buffer 8" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to system memory interrupt enable set/reset 1 buffer 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to system memory interrupt enable set/reset 1 buffer 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to system memory interrupt enable set/reset 1 buffer 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to system memory interrupt enable set/reset 1 buffer 4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to system memory interrupt enable set/reset 1 buffer 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to system memory interrupt enable set/reset 1 buffer 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to system memory interrupt enable set/reset 1 buffer 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to system memory interrupt enable set/reset 1 buffer 0" "No interrupt,Interrupt"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSMIES/R2_SET/CLR,Transfer to System Memory Interrupt Enable Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R2[63] ,Transfer to system memory interrupt enable set/reset 2 buffer 63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Transfer to system memory interrupt enable set/reset 2 buffer 62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Transfer to system memory interrupt enable set/reset 2 buffer 61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Transfer to system memory interrupt enable set/reset 2 buffer 60" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Transfer to system memory interrupt enable set/reset 2 buffer 59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Transfer to system memory interrupt enable set/reset 2 buffer 58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Transfer to system memory interrupt enable set/reset 2 buffer 57" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Transfer to system memory interrupt enable set/reset 2 buffer 56" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Transfer to system memory interrupt enable set/reset 2 buffer 55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Transfer to system memory interrupt enable set/reset 2 buffer 54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Transfer to system memory interrupt enable set/reset 2 buffer 53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Transfer to system memory interrupt enable set/reset 2 buffer 52" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Transfer to system memory interrupt enable set/reset 2 buffer 51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Transfer to system memory interrupt enable set/reset 2 buffer 50" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Transfer to system memory interrupt enable set/reset 2 buffer 49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Transfer to system memory interrupt enable set/reset 2 buffer 48" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Transfer to system memory interrupt enable set/reset 2 buffer 47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Transfer to system memory interrupt enable set/reset 2 buffer 46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Transfer to system memory interrupt enable set/reset 2 buffer 45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Transfer to system memory interrupt enable set/reset 2 buffer 44" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Transfer to system memory interrupt enable set/reset 2 buffer 43" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Transfer to system memory interrupt enable set/reset 2 buffer 42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Transfer to system memory interrupt enable set/reset 2 buffer 41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Transfer to system memory interrupt enable set/reset 2 buffer 40" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Transfer to system memory interrupt enable set/reset 2 buffer 39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Transfer to system memory interrupt enable set/reset 2 buffer 38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Transfer to system memory interrupt enable set/reset 2 buffer 37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Transfer to system memory interrupt enable set/reset 2 buffer 36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Transfer to system memory interrupt enable set/reset 2 buffer 35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Transfer to system memory interrupt enable set/reset 2 buffer 34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Transfer to system memory interrupt enable set/reset 2 buffer 33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Transfer to system memory interrupt enable set/reset 2 buffer 32" "No interrupt,Interrupt"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSMIES/R3_SET/CLR,Transfer to System Memory Interrupt Enable Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R3[95] ,Transfer to system memory interrupt enable set/reset 3 buffer 95" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Transfer to system memory interrupt enable set/reset 3 buffer 94" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Transfer to system memory interrupt enable set/reset 3 buffer 93" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Transfer to system memory interrupt enable set/reset 3 buffer 92" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Transfer to system memory interrupt enable set/reset 3 buffer 91" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Transfer to system memory interrupt enable set/reset 3 buffer 90" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Transfer to system memory interrupt enable set/reset 3 buffer 89" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Transfer to system memory interrupt enable set/reset 3 buffer 88" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Transfer to system memory interrupt enable set/reset 3 buffer 87" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Transfer to system memory interrupt enable set/reset 3 buffer 86" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Transfer to system memory interrupt enable set/reset 3 buffer 85" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Transfer to system memory interrupt enable set/reset 3 buffer 84" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Transfer to system memory interrupt enable set/reset 3 buffer 83" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Transfer to system memory interrupt enable set/reset 3 buffer 82" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Transfer to system memory interrupt enable set/reset 3 buffer 81" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Transfer to system memory interrupt enable set/reset 3 buffer 80" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Transfer to system memory interrupt enable set/reset 3 buffer 79" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Transfer to system memory interrupt enable set/reset 3 buffer 78" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Transfer to system memory interrupt enable set/reset 3 buffer 77" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Transfer to system memory interrupt enable set/reset 3 buffer 76" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Transfer to system memory interrupt enable set/reset 3 buffer 75" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Transfer to system memory interrupt enable set/reset 3 buffer 74" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Transfer to system memory interrupt enable set/reset 3 buffer 73" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Transfer to system memory interrupt enable set/reset 3 buffer 72" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Transfer to system memory interrupt enable set/reset 3 buffer 71" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Transfer to system memory interrupt enable set/reset 3 buffer 70" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Transfer to system memory interrupt enable set/reset 3 buffer 69" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Transfer to system memory interrupt enable set/reset 3 buffer 68" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Transfer to system memory interrupt enable set/reset 3 buffer 67" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Transfer to system memory interrupt enable set/reset 3 buffer 66" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Transfer to system memory interrupt enable set/reset 3 buffer 65" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Transfer to system memory interrupt enable set/reset 3 buffer 64" "No interrupt,Interrupt"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSMIES/R4_SET/CLR,Transfer to System Memory Interrupt Enable Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R4[127] ,Transfer to system memory interrupt enable set/reset 4 buffer 127" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Transfer to system memory interrupt enable set/reset 4 buffer 126" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Transfer to system memory interrupt enable set/reset 4 buffer 125" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Transfer to system memory interrupt enable set/reset 4 buffer 124" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Transfer to system memory interrupt enable set/reset 4 buffer 123" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Transfer to system memory interrupt enable set/reset 4 buffer 122" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Transfer to system memory interrupt enable set/reset 4 buffer 121" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Transfer to system memory interrupt enable set/reset 4 buffer 120" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Transfer to system memory interrupt enable set/reset 4 buffer 119" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Transfer to system memory interrupt enable set/reset 4 buffer 118" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Transfer to system memory interrupt enable set/reset 4 buffer 117" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Transfer to system memory interrupt enable set/reset 4 buffer 116" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Transfer to system memory interrupt enable set/reset 4 buffer 115" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Transfer to system memory interrupt enable set/reset 4 buffer 114" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Transfer to system memory interrupt enable set/reset 4 buffer 113" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Transfer to system memory interrupt enable set/reset 4 buffer 112" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Transfer to system memory interrupt enable set/reset 4 buffer 111" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Transfer to system memory interrupt enable set/reset 4 buffer 110" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Transfer to system memory interrupt enable set/reset 4 buffer 109" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Transfer to system memory interrupt enable set/reset 4 buffer 108" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Transfer to system memory interrupt enable set/reset 4 buffer 107" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Transfer to system memory interrupt enable set/reset 4 buffer 106" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Transfer to system memory interrupt enable set/reset 4 buffer 105" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Transfer to system memory interrupt enable set/reset 4 buffer 104" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Transfer to system memory interrupt enable set/reset 4 buffer 103" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Transfer to system memory interrupt enable set/reset 4 buffer 102" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Transfer to system memory interrupt enable set/reset 4 buffer 101" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [100] ,Transfer to system memory interrupt enable set/reset 4 buffer 100" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [99] ,Transfer to system memory interrupt enable set/reset 4 buffer 99" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [98] ,Transfer to system memory interrupt enable set/reset 4 buffer 98" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [97] ,Transfer to system memory interrupt enable set/reset 4 buffer 97" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [96] ,Transfer to system memory interrupt enable set/reset 4 buffer 96" "No interrupt,Interrupt"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCCIES/R1_SET/CLR,Transfer to Communication Controller Interrupt Enable Set/Reset 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R1[31] ,Transfer to communication controller interrupt enable set/reset 1 buffer 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to communication controller interrupt enable set/reset 1 buffer 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to communication controller interrupt enable set/reset 1 buffer 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to communication controller interrupt enable set/reset 1 buffer 28" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to communication controller interrupt enable set/reset 1 buffer 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to communication controller interrupt enable set/reset 1 buffer 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to communication controller interrupt enable set/reset 1 buffer 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to communication controller interrupt enable set/reset 1 buffer 24" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to communication controller interrupt enable set/reset 1 buffer 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to communication controller interrupt enable set/reset 1 buffer 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to communication controller interrupt enable set/reset 1 buffer 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to communication controller interrupt enable set/reset 1 buffer 20" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to communication controller interrupt enable set/reset 1 buffer 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to communication controller interrupt enable set/reset 1 buffer 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to communication controller interrupt enable set/reset 1 buffer 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to communication controller interrupt enable set/reset 1 buffer 16" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to communication controller interrupt enable set/reset 1 buffer 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to communication controller interrupt enable set/reset 1 buffer 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to communication controller interrupt enable set/reset 1 buffer 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to communication controller interrupt enable set/reset 1 buffer 12" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to communication controller interrupt enable set/reset 1 buffer 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to communication controller interrupt enable set/reset 1 buffer 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to communication controller interrupt enable set/reset 1 buffer 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to communication controller interrupt enable set/reset 1 buffer 8" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to communication controller interrupt enable set/reset 1 buffer 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to communication controller interrupt enable set/reset 1 buffer 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to communication controller interrupt enable set/reset 1 buffer 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to communication controller interrupt enable set/reset 1 buffer 4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to communication controller interrupt enable set/reset 1 buffer 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to communication controller interrupt enable set/reset 1 buffer 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to communication controller interrupt enable set/reset 1 buffer 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to communication controller interrupt enable set/reset 1 buffer 0" "No interrupt,Interrupt"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TCCIES/R2_SET/CLR,Transfer to Communication Controller Interrupt Enable Set/Reset 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R2[63] ,Transfer to communication controller interrupt enable set/reset 2 buffer 63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Transfer to communication controller interrupt enable set/reset 2 buffer 62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Transfer to communication controller interrupt enable set/reset 2 buffer 61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Transfer to communication controller interrupt enable set/reset 2 buffer 60" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Transfer to communication controller interrupt enable set/reset 2 buffer 59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Transfer to communication controller interrupt enable set/reset 2 buffer 58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Transfer to communication controller interrupt enable set/reset 2 buffer 57" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Transfer to communication controller interrupt enable set/reset 2 buffer 56" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Transfer to communication controller interrupt enable set/reset 2 buffer 55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Transfer to communication controller interrupt enable set/reset 2 buffer 54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Transfer to communication controller interrupt enable set/reset 2 buffer 53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Transfer to communication controller interrupt enable set/reset 2 buffer 52" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Transfer to communication controller interrupt enable set/reset 2 buffer 51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Transfer to communication controller interrupt enable set/reset 2 buffer 50" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Transfer to communication controller interrupt enable set/reset 2 buffer 49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Transfer to communication controller interrupt enable set/reset 2 buffer 48" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Transfer to communication controller interrupt enable set/reset 2 buffer 47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Transfer to communication controller interrupt enable set/reset 2 buffer 46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Transfer to communication controller interrupt enable set/reset 2 buffer 45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Transfer to communication controller interrupt enable set/reset 2 buffer 44" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Transfer to communication controller interrupt enable set/reset 2 buffer 43" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Transfer to communication controller interrupt enable set/reset 2 buffer 42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Transfer to communication controller interrupt enable set/reset 2 buffer 41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Transfer to communication controller interrupt enable set/reset 2 buffer 40" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Transfer to communication controller interrupt enable set/reset 2 buffer 39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Transfer to communication controller interrupt enable set/reset 2 buffer 38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Transfer to communication controller interrupt enable set/reset 2 buffer 37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Transfer to communication controller interrupt enable set/reset 2 buffer 36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Transfer to communication controller interrupt enable set/reset 2 buffer 35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Transfer to communication controller interrupt enable set/reset 2 buffer 34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Transfer to communication controller interrupt enable set/reset 2 buffer 33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Transfer to communication controller interrupt enable set/reset 2 buffer 32" "No interrupt,Interrupt"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TCCIES/R3_SET/CLR,Transfer to Communication Controller Interrupt Enable Set/Reset 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R3[95] ,Transfer to communication controller interrupt enable set/reset 3 buffer 95" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [94] ,Transfer to communication controller interrupt enable set/reset 3 buffer 94" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [93] ,Transfer to communication controller interrupt enable set/reset 3 buffer 93" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [92] ,Transfer to communication controller interrupt enable set/reset 3 buffer 92" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Transfer to communication controller interrupt enable set/reset 3 buffer 91" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Transfer to communication controller interrupt enable set/reset 3 buffer 90" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Transfer to communication controller interrupt enable set/reset 3 buffer 89" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Transfer to communication controller interrupt enable set/reset 3 buffer 88" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [87] ,Transfer to communication controller interrupt enable set/reset 3 buffer 87" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Transfer to communication controller interrupt enable set/reset 3 buffer 86" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Transfer to communication controller interrupt enable set/reset 3 buffer 85" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Transfer to communication controller interrupt enable set/reset 3 buffer 84" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Transfer to communication controller interrupt enable set/reset 3 buffer 83" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Transfer to communication controller interrupt enable set/reset 3 buffer 82" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Transfer to communication controller interrupt enable set/reset 3 buffer 81" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Transfer to communication controller interrupt enable set/reset 3 buffer 80" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Transfer to communication controller interrupt enable set/reset 3 buffer 79" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Transfer to communication controller interrupt enable set/reset 3 buffer 78" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Transfer to communication controller interrupt enable set/reset 3 buffer 77" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Transfer to communication controller interrupt enable set/reset 3 buffer 76" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Transfer to communication controller interrupt enable set/reset 3 buffer 75" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Transfer to communication controller interrupt enable set/reset 3 buffer 74" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Transfer to communication controller interrupt enable set/reset 3 buffer 73" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Transfer to communication controller interrupt enable set/reset 3 buffer 72" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Transfer to communication controller interrupt enable set/reset 3 buffer 71" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Transfer to communication controller interrupt enable set/reset 3 buffer 70" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Transfer to communication controller interrupt enable set/reset 3 buffer 69" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [68] ,Transfer to communication controller interrupt enable set/reset 3 buffer 68" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [67] ,Transfer to communication controller interrupt enable set/reset 3 buffer 67" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [66] ,Transfer to communication controller interrupt enable set/reset 3 buffer 66" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [65] ,Transfer to communication controller interrupt enable set/reset 3 buffer 65" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [64] ,Transfer to communication controller interrupt enable set/reset 3 buffer 64" "No interrupt,Interrupt"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TCCIES/R4_SET/CLR,Transfer to Communication Controller Interrupt Enable Set/Reset 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R4[127] ,Transfer to communication controller interrupt enable set/reset 4 buffer 127" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [126] ,Transfer to communication controller interrupt enable set/reset 4 buffer 126" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [125] ,Transfer to communication controller interrupt enable set/reset 4 buffer 125" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [124] ,Transfer to communication controller interrupt enable set/reset 4 buffer 124" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [123] ,Transfer to communication controller interrupt enable set/reset 4 buffer 123" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [122] ,Transfer to communication controller interrupt enable set/reset 4 buffer 122" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [121] ,Transfer to communication controller interrupt enable set/reset 4 buffer 121" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [120] ,Transfer to communication controller interrupt enable set/reset 4 buffer 120" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [119] ,Transfer to communication controller interrupt enable set/reset 4 buffer 119" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [118] ,Transfer to communication controller interrupt enable set/reset 4 buffer 118" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [117] ,Transfer to communication controller interrupt enable set/reset 4 buffer 117" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [116] ,Transfer to communication controller interrupt enable set/reset 4 buffer 116" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [115] ,Transfer to communication controller interrupt enable set/reset 4 buffer 115" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [114] ,Transfer to communication controller interrupt enable set/reset 4 buffer 114" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [113] ,Transfer to communication controller interrupt enable set/reset 4 buffer 113" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [112] ,Transfer to communication controller interrupt enable set/reset 4 buffer 112" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [111] ,Transfer to communication controller interrupt enable set/reset 4 buffer 111" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [110] ,Transfer to communication controller interrupt enable set/reset 4 buffer 110" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [109] ,Transfer to communication controller interrupt enable set/reset 4 buffer 109" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [108] ,Transfer to communication controller interrupt enable set/reset 4 buffer 108" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [107] ,Transfer to communication controller interrupt enable set/reset 4 buffer 107" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [106] ,Transfer to communication controller interrupt enable set/reset 4 buffer 106" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [105] ,Transfer to communication controller interrupt enable set/reset 4 buffer 105" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [104] ,Transfer to communication controller interrupt enable set/reset 4 buffer 104" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [103] ,Transfer to communication controller interrupt enable set/reset 4 buffer 103" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [102] ,Transfer to communication controller interrupt enable set/reset 4 buffer 102" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [101] ,Transfer to communication controller interrupt enable set/reset 4 buffer 101" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [100] ,Transfer to communication controller interrupt enable set/reset 4 buffer 100" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [99] ,Transfer to communication controller interrupt enable set/reset 4 buffer 99" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [98] ,Transfer to communication controller interrupt enable set/reset 4 buffer 98" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [97] ,Transfer to communication controller interrupt enable set/reset 4 buffer 97" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [96] ,Transfer to communication controller interrupt enable set/reset 4 buffer 96" "No interrupt,Interrupt"
|
|
base ad:0xFF500000
|
|
width 9.
|
|
sif (cpuis("RM48L950*")||cpuis("TMS570LS2124-PGE")||cpuis("TMS570LS2124-ZWT")||cpuis("TMS570LS2134-PGE")||cpuis("TMS570LS2134-ZWT")||cpuis("TMS570LS3134-PGE")||cpuis("TMS570LS3134-ZWT")||cpuis("TMS570LS3135-PGE")||cpuis("TMS570LS3135-ZWT")||cpuis("TMS570LS3136")||cpuis("TMS570LS3137-PGE")||cpuis("TMS570LS3137-ZWT")||cpuis("TMS570LS30336")||cpuis("TMS570LS2126")||cpuis("TMS570LS2127")||cpuis("TMS570LS2136")||cpuis("TMS570LS2137")||cpuis("TMS570LS2125-PGE")||cpuis("TMS570LS2125-ZWT")||cpuis("TMS570LS2135-PGE")||cpuis("TMS570LS2135-ZWT")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
tree "TU RAM (Transfer Configuration RAM)"
|
|
tree "Normal Mode"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCR0,Transfer Configuration RAM 0"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TCR1,Transfer Configuration RAM 1"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TCR2,Transfer Configuration RAM 2"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TCR3,Transfer Configuration RAM 3"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR4,Transfer Configuration RAM 4"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR5,Transfer Configuration RAM 5"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TCR6,Transfer Configuration RAM 6"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TCR7,Transfer Configuration RAM 7"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCR8,Transfer Configuration RAM 8"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TCR9,Transfer Configuration RAM 9"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCR10,Transfer Configuration RAM 10"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCR11,Transfer Configuration RAM 11"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCR12,Transfer Configuration RAM 12"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TCR13,Transfer Configuration RAM 13"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCR14,Transfer Configuration RAM 14"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCR15,Transfer Configuration RAM 15"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCR16,Transfer Configuration RAM 16"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TCR17,Transfer Configuration RAM 17"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCR18,Transfer Configuration RAM 18"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TCR19,Transfer Configuration RAM 19"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCR20,Transfer Configuration RAM 20"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TCR21,Transfer Configuration RAM 21"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCR22,Transfer Configuration RAM 22"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TCR23,Transfer Configuration RAM 23"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR24,Transfer Configuration RAM 24"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TCR25,Transfer Configuration RAM 25"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TCR26,Transfer Configuration RAM 26"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TCR27,Transfer Configuration RAM 27"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TCR28,Transfer Configuration RAM 28"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TCR29,Transfer Configuration RAM 29"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TCR30,Transfer Configuration RAM 30"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TCR31,Transfer Configuration RAM 31"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCR32,Transfer Configuration RAM 32"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TCR33,Transfer Configuration RAM 33"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TCR34,Transfer Configuration RAM 34"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TCR35,Transfer Configuration RAM 35"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TCR36,Transfer Configuration RAM 36"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TCR37,Transfer Configuration RAM 37"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TCR38,Transfer Configuration RAM 38"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TCR39,Transfer Configuration RAM 39"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCR40,Transfer Configuration RAM 40"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TCR41,Transfer Configuration RAM 41"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TCR42,Transfer Configuration RAM 42"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TCR43,Transfer Configuration RAM 43"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TCR44,Transfer Configuration RAM 44"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TCR45,Transfer Configuration RAM 45"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TCR46,Transfer Configuration RAM 46"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TCR47,Transfer Configuration RAM 47"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCR48,Transfer Configuration RAM 48"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TCR49,Transfer Configuration RAM 49"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TCR50,Transfer Configuration RAM 50"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TCR51,Transfer Configuration RAM 51"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TCR52,Transfer Configuration RAM 52"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TCR53,Transfer Configuration RAM 53"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TCR54,Transfer Configuration RAM 54"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TCR55,Transfer Configuration RAM 55"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCR56,Transfer Configuration RAM 56"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TCR57,Transfer Configuration RAM 57"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TCR58,Transfer Configuration RAM 58"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TCR59,Transfer Configuration RAM 59"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TCR60,Transfer Configuration RAM 60"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TCR61,Transfer Configuration RAM 61"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TCR62,Transfer Configuration RAM 62"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TCR63,Transfer Configuration RAM 63"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCR64,Transfer Configuration RAM 64"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TCR65,Transfer Configuration RAM 65"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TCR66,Transfer Configuration RAM 66"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TCR67,Transfer Configuration RAM 67"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TCR68,Transfer Configuration RAM 68"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TCR69,Transfer Configuration RAM 69"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TCR70,Transfer Configuration RAM 70"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TCR71,Transfer Configuration RAM 71"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCR72,Transfer Configuration RAM 72"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TCR73,Transfer Configuration RAM 73"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TCR74,Transfer Configuration RAM 74"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TCR75,Transfer Configuration RAM 75"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TCR76,Transfer Configuration RAM 76"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TCR77,Transfer Configuration RAM 77"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TCR78,Transfer Configuration RAM 78"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TCR79,Transfer Configuration RAM 79"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCR80,Transfer Configuration RAM 80"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TCR81,Transfer Configuration RAM 81"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TCR82,Transfer Configuration RAM 82"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TCR83,Transfer Configuration RAM 83"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TCR84,Transfer Configuration RAM 84"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TCR85,Transfer Configuration RAM 85"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TCR86,Transfer Configuration RAM 86"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TCR87,Transfer Configuration RAM 87"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCR88,Transfer Configuration RAM 88"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TCR89,Transfer Configuration RAM 89"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TCR90,Transfer Configuration RAM 90"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TCR91,Transfer Configuration RAM 91"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TCR92,Transfer Configuration RAM 92"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TCR93,Transfer Configuration RAM 93"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TCR94,Transfer Configuration RAM 94"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TCR95,Transfer Configuration RAM 95"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCR96,Transfer Configuration RAM 96"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TCR97,Transfer Configuration RAM 97"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TCR98,Transfer Configuration RAM 98"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TCR99,Transfer Configuration RAM 99"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TCR100,Transfer Configuration RAM 100"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TCR101,Transfer Configuration RAM 101"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TCR102,Transfer Configuration RAM 102"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TCR103,Transfer Configuration RAM 103"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCR104,Transfer Configuration RAM 104"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TCR105,Transfer Configuration RAM 105"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TCR106,Transfer Configuration RAM 106"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TCR107,Transfer Configuration RAM 107"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TCR108,Transfer Configuration RAM 108"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TCR109,Transfer Configuration RAM 109"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TCR110,Transfer Configuration RAM 110"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TCR111,Transfer Configuration RAM 111"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCR112,Transfer Configuration RAM 112"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TCR113,Transfer Configuration RAM 113"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TCR114,Transfer Configuration RAM 114"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TCR115,Transfer Configuration RAM 115"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TCR116,Transfer Configuration RAM 116"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TCR117,Transfer Configuration RAM 117"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TCR118,Transfer Configuration RAM 118"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TCR119,Transfer Configuration RAM 119"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCR120,Transfer Configuration RAM 120"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TCR121,Transfer Configuration RAM 121"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TCR122,Transfer Configuration RAM 122"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TCR123,Transfer Configuration RAM 123"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TCR124,Transfer Configuration RAM 124"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TCR125,Transfer Configuration RAM 125"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TCR126,Transfer Configuration RAM 126"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "TCR127,Transfer Configuration RAM 127"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
tree.end
|
|
tree "TCR Parity Test Mode"
|
|
sif (cpuis("RM48L950*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCRP0,TCR Parity Test Mode 0"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR0[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR0[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR0 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "TCP0,TCR Parity Test Mode 0"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TCRP1,TCR Parity Test Mode 1"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR1[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR1[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR1 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "TCP1,TCR Parity Test Mode 1"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TCRP2,TCR Parity Test Mode 2"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR2[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR2[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR2 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "TCP2,TCR Parity Test Mode 2"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TCRP3,TCR Parity Test Mode 3"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR3[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR3[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR3 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "TCP3,TCR Parity Test Mode 3"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TCRP4,TCR Parity Test Mode 4"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR4[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR4[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR4 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "TCP4,TCR Parity Test Mode 4"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TCRP5,TCR Parity Test Mode 5"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR5[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR5[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR5 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "TCP5,TCR Parity Test Mode 5"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TCRP6,TCR Parity Test Mode 6"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR6[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR6[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR6 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "TCP6,TCR Parity Test Mode 6"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "TCRP7,TCR Parity Test Mode 7"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR7[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR7[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR7 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "TCP7,TCR Parity Test Mode 7"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCRP8,TCR Parity Test Mode 8"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR8[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR8[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR8 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "TCP8,TCR Parity Test Mode 8"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TCRP9,TCR Parity Test Mode 9"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR9[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR9[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR9 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "TCP9,TCR Parity Test Mode 9"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "TCRP10,TCR Parity Test Mode 10"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR10[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR10[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR10 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "TCP10,TCR Parity Test Mode 10"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "TCRP11,TCR Parity Test Mode 11"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR11[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR11[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR11 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "TCP11,TCR Parity Test Mode 11"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "TCRP12,TCR Parity Test Mode 12"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR12[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR12[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR12 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "TCP12,TCR Parity Test Mode 12"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "TCRP13,TCR Parity Test Mode 13"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR13[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR13[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR13 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "TCP13,TCR Parity Test Mode 13"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "TCRP14,TCR Parity Test Mode 14"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR14[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR14[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR14 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "TCP14,TCR Parity Test Mode 14"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TCRP15,TCR Parity Test Mode 15"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR15[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR15[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR15 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "TCP15,TCR Parity Test Mode 15"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCRP16,TCR Parity Test Mode 16"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR16[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR16[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR16 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "TCP16,TCR Parity Test Mode 16"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "TCRP17,TCR Parity Test Mode 17"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR17[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR17[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR17 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "TCP17,TCR Parity Test Mode 17"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TCRP18,TCR Parity Test Mode 18"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR18[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR18[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR18 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "TCP18,TCR Parity Test Mode 18"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "TCRP19,TCR Parity Test Mode 19"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR19[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR19[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR19 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "TCP19,TCR Parity Test Mode 19"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "TCRP20,TCR Parity Test Mode 20"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR20[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR20[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR20 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "TCP20,TCR Parity Test Mode 20"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TCRP21,TCR Parity Test Mode 21"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR21[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR21[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR21 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "TCP21,TCR Parity Test Mode 21"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TCRP22,TCR Parity Test Mode 22"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR22[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR22[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR22 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "TCP22,TCR Parity Test Mode 22"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "TCRP23,TCR Parity Test Mode 23"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR23[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR23[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR23 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "TCP23,TCR Parity Test Mode 23"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCRP24,TCR Parity Test Mode 24"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR24[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR24[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR24 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "TCP24,TCR Parity Test Mode 24"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TCRP25,TCR Parity Test Mode 25"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR25[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR25[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR25 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "TCP25,TCR Parity Test Mode 25"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TCRP26,TCR Parity Test Mode 26"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR26[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR26[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR26 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "TCP26,TCR Parity Test Mode 26"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "TCRP27,TCR Parity Test Mode 27"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR27[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR27[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR27 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "TCP27,TCR Parity Test Mode 27"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "TCRP28,TCR Parity Test Mode 28"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR28[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR28[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR28 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "TCP28,TCR Parity Test Mode 28"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "TCRP29,TCR Parity Test Mode 29"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR29[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR29[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR29 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "TCP29,TCR Parity Test Mode 29"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "TCRP30,TCR Parity Test Mode 30"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR30[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR30[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR30 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "TCP30,TCR Parity Test Mode 30"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "TCRP31,TCR Parity Test Mode 31"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR31[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR31[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR31 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "TCP31,TCR Parity Test Mode 31"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCRP32,TCR Parity Test Mode 32"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR32[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR32[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR32 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "TCP32,TCR Parity Test Mode 32"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TCRP33,TCR Parity Test Mode 33"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR33[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR33[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR33 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "TCP33,TCR Parity Test Mode 33"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "TCRP34,TCR Parity Test Mode 34"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR34[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR34[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR34 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "TCP34,TCR Parity Test Mode 34"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "TCRP35,TCR Parity Test Mode 35"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR35[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR35[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR35 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "TCP35,TCR Parity Test Mode 35"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TCRP36,TCR Parity Test Mode 36"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR36[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR36[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR36 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "TCP36,TCR Parity Test Mode 36"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TCRP37,TCR Parity Test Mode 37"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR37[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR37[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR37 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "TCP37,TCR Parity Test Mode 37"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TCRP38,TCR Parity Test Mode 38"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR38[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR38[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR38 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "TCP38,TCR Parity Test Mode 38"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TCRP39,TCR Parity Test Mode 39"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR39[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR39[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR39 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "TCP39,TCR Parity Test Mode 39"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCRP40,TCR Parity Test Mode 40"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR40[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR40[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR40 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "TCP40,TCR Parity Test Mode 40"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "TCRP41,TCR Parity Test Mode 41"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR41[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR41[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR41 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "TCP41,TCR Parity Test Mode 41"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "TCRP42,TCR Parity Test Mode 42"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR42[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR42[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR42 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "TCP42,TCR Parity Test Mode 42"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "TCRP43,TCR Parity Test Mode 43"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR43[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR43[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR43 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "TCP43,TCR Parity Test Mode 43"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "TCRP44,TCR Parity Test Mode 44"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR44[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR44[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR44 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "TCP44,TCR Parity Test Mode 44"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TCRP45,TCR Parity Test Mode 45"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR45[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR45[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR45 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "TCP45,TCR Parity Test Mode 45"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "TCRP46,TCR Parity Test Mode 46"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR46[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR46[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR46 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "TCP46,TCR Parity Test Mode 46"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "TCRP47,TCR Parity Test Mode 47"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR47[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR47[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR47 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "TCP47,TCR Parity Test Mode 47"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCRP48,TCR Parity Test Mode 48"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR48[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR48[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR48 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "TCP48,TCR Parity Test Mode 48"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "TCRP49,TCR Parity Test Mode 49"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR49[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR49[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR49 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "TCP49,TCR Parity Test Mode 49"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TCRP50,TCR Parity Test Mode 50"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR50[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR50[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR50 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "TCP50,TCR Parity Test Mode 50"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "TCRP51,TCR Parity Test Mode 51"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR51[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR51[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR51 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "TCP51,TCR Parity Test Mode 51"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "TCRP52,TCR Parity Test Mode 52"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR52[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR52[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR52 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "TCP52,TCR Parity Test Mode 52"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "TCRP53,TCR Parity Test Mode 53"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR53[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR53[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR53 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "TCP53,TCR Parity Test Mode 53"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "TCRP54,TCR Parity Test Mode 54"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR54[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR54[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR54 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "TCP54,TCR Parity Test Mode 54"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "TCRP55,TCR Parity Test Mode 55"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR55[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR55[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR55 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "TCP55,TCR Parity Test Mode 55"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCRP56,TCR Parity Test Mode 56"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR56[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR56[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR56 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "TCP56,TCR Parity Test Mode 56"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TCRP57,TCR Parity Test Mode 57"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR57[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR57[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR57 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "TCP57,TCR Parity Test Mode 57"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TCRP58,TCR Parity Test Mode 58"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR58[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR58[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR58 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "TCP58,TCR Parity Test Mode 58"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TCRP59,TCR Parity Test Mode 59"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR59[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR59[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR59 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "TCP59,TCR Parity Test Mode 59"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TCRP60,TCR Parity Test Mode 60"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR60[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR60[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR60 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "TCP60,TCR Parity Test Mode 60"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TCRP61,TCR Parity Test Mode 61"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR61[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR61[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR61 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "TCP61,TCR Parity Test Mode 61"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TCRP62,TCR Parity Test Mode 62"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR62[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR62[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR62 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "TCP62,TCR Parity Test Mode 62"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TCRP63,TCR Parity Test Mode 63"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR63[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR63[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR63 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "TCP63,TCR Parity Test Mode 63"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCRP64,TCR Parity Test Mode 64"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR64[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR64[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR64 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "TCP64,TCR Parity Test Mode 64"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TCRP65,TCR Parity Test Mode 65"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR65[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR65[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR65 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "TCP65,TCR Parity Test Mode 65"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TCRP66,TCR Parity Test Mode 66"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR66[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR66[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR66 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "TCP66,TCR Parity Test Mode 66"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TCRP67,TCR Parity Test Mode 67"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR67[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR67[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR67 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "TCP67,TCR Parity Test Mode 67"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TCRP68,TCR Parity Test Mode 68"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR68[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR68[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR68 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "TCP68,TCR Parity Test Mode 68"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TCRP69,TCR Parity Test Mode 69"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR69[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR69[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR69 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "TCP69,TCR Parity Test Mode 69"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TCRP70,TCR Parity Test Mode 70"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR70[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR70[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR70 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "TCP70,TCR Parity Test Mode 70"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TCRP71,TCR Parity Test Mode 71"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR71[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR71[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR71 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "TCP71,TCR Parity Test Mode 71"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCRP72,TCR Parity Test Mode 72"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR72[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR72[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR72 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "TCP72,TCR Parity Test Mode 72"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TCRP73,TCR Parity Test Mode 73"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR73[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR73[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR73 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "TCP73,TCR Parity Test Mode 73"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TCRP74,TCR Parity Test Mode 74"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR74[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR74[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR74 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "TCP74,TCR Parity Test Mode 74"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TCRP75,TCR Parity Test Mode 75"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR75[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR75[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR75 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "TCP75,TCR Parity Test Mode 75"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TCRP76,TCR Parity Test Mode 76"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR76[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR76[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR76 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "TCP76,TCR Parity Test Mode 76"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TCRP77,TCR Parity Test Mode 77"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR77[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR77[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR77 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "TCP77,TCR Parity Test Mode 77"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TCRP78,TCR Parity Test Mode 78"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR78[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR78[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR78 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "TCP78,TCR Parity Test Mode 78"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TCRP79,TCR Parity Test Mode 79"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR79[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR79[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR79 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "TCP79,TCR Parity Test Mode 79"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCRP80,TCR Parity Test Mode 80"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR80[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR80[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR80 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "TCP80,TCR Parity Test Mode 80"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TCRP81,TCR Parity Test Mode 81"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR81[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR81[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR81 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "TCP81,TCR Parity Test Mode 81"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TCRP82,TCR Parity Test Mode 82"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR82[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR82[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR82 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "TCP82,TCR Parity Test Mode 82"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TCRP83,TCR Parity Test Mode 83"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR83[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR83[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR83 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "TCP83,TCR Parity Test Mode 83"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TCRP84,TCR Parity Test Mode 84"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR84[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR84[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR84 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "TCP84,TCR Parity Test Mode 84"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TCRP85,TCR Parity Test Mode 85"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR85[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR85[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR85 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "TCP85,TCR Parity Test Mode 85"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TCRP86,TCR Parity Test Mode 86"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR86[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR86[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR86 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "TCP86,TCR Parity Test Mode 86"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TCRP87,TCR Parity Test Mode 87"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR87[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR87[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR87 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "TCP87,TCR Parity Test Mode 87"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCRP88,TCR Parity Test Mode 88"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR88[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR88[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR88 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "TCP88,TCR Parity Test Mode 88"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TCRP89,TCR Parity Test Mode 89"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR89[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR89[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR89 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "TCP89,TCR Parity Test Mode 89"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TCRP90,TCR Parity Test Mode 90"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR90[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR90[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR90 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "TCP90,TCR Parity Test Mode 90"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TCRP91,TCR Parity Test Mode 91"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR91[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR91[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR91 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "TCP91,TCR Parity Test Mode 91"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TCRP92,TCR Parity Test Mode 92"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR92[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR92[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR92 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "TCP92,TCR Parity Test Mode 92"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TCRP93,TCR Parity Test Mode 93"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR93[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR93[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR93 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "TCP93,TCR Parity Test Mode 93"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TCRP94,TCR Parity Test Mode 94"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR94[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR94[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR94 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "TCP94,TCR Parity Test Mode 94"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TCRP95,TCR Parity Test Mode 95"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR95[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR95[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR95 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "TCP95,TCR Parity Test Mode 95"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCRP96,TCR Parity Test Mode 96"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR96[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR96[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR96 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "TCP96,TCR Parity Test Mode 96"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TCRP97,TCR Parity Test Mode 97"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR97[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR97[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR97 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "TCP97,TCR Parity Test Mode 97"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TCRP98,TCR Parity Test Mode 98"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR98[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR98[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR98 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "TCP98,TCR Parity Test Mode 98"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TCRP99,TCR Parity Test Mode 99"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR99[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR99[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR99 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "TCP99,TCR Parity Test Mode 99"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TCRP100,TCR Parity Test Mode 100"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR100[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR100[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR100 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "TCP100,TCR Parity Test Mode 100"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TCRP101,TCR Parity Test Mode 101"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR101[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR101[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR101 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "TCP101,TCR Parity Test Mode 101"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "TCRP102,TCR Parity Test Mode 102"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR102[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR102[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR102 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "TCP102,TCR Parity Test Mode 102"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "TCRP103,TCR Parity Test Mode 103"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR103[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR103[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR103 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "TCP103,TCR Parity Test Mode 103"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCRP104,TCR Parity Test Mode 104"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR104[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR104[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR104 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "TCP104,TCR Parity Test Mode 104"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TCRP105,TCR Parity Test Mode 105"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR105[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR105[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR105 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "TCP105,TCR Parity Test Mode 105"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "TCRP106,TCR Parity Test Mode 106"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR106[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR106[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR106 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "TCP106,TCR Parity Test Mode 106"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "TCRP107,TCR Parity Test Mode 107"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR107[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR107[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR107 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "TCP107,TCR Parity Test Mode 107"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "TCRP108,TCR Parity Test Mode 108"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR108[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR108[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR108 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "TCP108,TCR Parity Test Mode 108"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "TCRP109,TCR Parity Test Mode 109"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR109[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR109[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR109 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "TCP109,TCR Parity Test Mode 109"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "TCRP110,TCR Parity Test Mode 110"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR110[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR110[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR110 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "TCP110,TCR Parity Test Mode 110"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "TCRP111,TCR Parity Test Mode 111"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR111[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR111[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR111 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "TCP111,TCR Parity Test Mode 111"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCRP112,TCR Parity Test Mode 112"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR112[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR112[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR112 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "TCP112,TCR Parity Test Mode 112"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "TCRP113,TCR Parity Test Mode 113"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR113[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR113[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR113 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "TCP113,TCR Parity Test Mode 113"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "TCRP114,TCR Parity Test Mode 114"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR114[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR114[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR114 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "TCP114,TCR Parity Test Mode 114"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "TCRP115,TCR Parity Test Mode 115"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR115[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR115[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR115 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "TCP115,TCR Parity Test Mode 115"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "TCRP116,TCR Parity Test Mode 116"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR116[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR116[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR116 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "TCP116,TCR Parity Test Mode 116"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TCRP117,TCR Parity Test Mode 117"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR117[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR117[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR117 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "TCP117,TCR Parity Test Mode 117"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "TCRP118,TCR Parity Test Mode 118"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR118[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR118[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR118 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "TCP118,TCR Parity Test Mode 118"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "TCRP119,TCR Parity Test Mode 119"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR119[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR119[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR119 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "TCP119,TCR Parity Test Mode 119"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCRP120,TCR Parity Test Mode 120"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR120[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR120[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR120 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "TCP120,TCR Parity Test Mode 120"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "TCRP121,TCR Parity Test Mode 121"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR121[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR121[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR121 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "TCP121,TCR Parity Test Mode 121"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "TCRP122,TCR Parity Test Mode 122"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR122[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR122[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR122 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "TCP122,TCR Parity Test Mode 122"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "TCRP123,TCR Parity Test Mode 123"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR123[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR123[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR123 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "TCP123,TCR Parity Test Mode 123"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "TCRP124,TCR Parity Test Mode 124"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR124[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR124[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR124 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "TCP124,TCR Parity Test Mode 124"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "TCRP125,TCR Parity Test Mode 125"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR125[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR125[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR125 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "TCP125,TCR Parity Test Mode 125"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "TCRP126,TCR Parity Test Mode 126"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR126[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR126[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR126 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "TCP126,TCR Parity Test Mode 126"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x1000)==0x1000)
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "TCRP127,TCR Parity Test Mode 127"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR127[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR127[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR127 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "TCP127,TCR Parity Test Mode 127"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCRP0,TCR Parity Test Mode 0"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR0[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR0[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR0 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "TCRP0,TCR Parity Test Mode 0"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TCRP1,TCR Parity Test Mode 1"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR1[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR1[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR1 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "TCRP1,TCR Parity Test Mode 1"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TCRP2,TCR Parity Test Mode 2"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR2[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR2[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR2 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "TCRP2,TCR Parity Test Mode 2"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TCRP3,TCR Parity Test Mode 3"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR3[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR3[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR3 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "TCRP3,TCR Parity Test Mode 3"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TCRP4,TCR Parity Test Mode 4"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR4[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR4[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR4 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "TCRP4,TCR Parity Test Mode 4"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TCRP5,TCR Parity Test Mode 5"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR5[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR5[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR5 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "TCRP5,TCR Parity Test Mode 5"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TCRP6,TCR Parity Test Mode 6"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR6[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR6[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR6 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "TCRP6,TCR Parity Test Mode 6"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "TCRP7,TCR Parity Test Mode 7"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR7[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR7[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR7 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "TCRP7,TCR Parity Test Mode 7"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCRP8,TCR Parity Test Mode 8"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR8[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR8[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR8 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "TCRP8,TCR Parity Test Mode 8"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TCRP9,TCR Parity Test Mode 9"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR9[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR9[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR9 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "TCRP9,TCR Parity Test Mode 9"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "TCRP10,TCR Parity Test Mode 10"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR10[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR10[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR10 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "TCRP10,TCR Parity Test Mode 10"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "TCRP11,TCR Parity Test Mode 11"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR11[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR11[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR11 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "TCRP11,TCR Parity Test Mode 11"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "TCRP12,TCR Parity Test Mode 12"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR12[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR12[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR12 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "TCRP12,TCR Parity Test Mode 12"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "TCRP13,TCR Parity Test Mode 13"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR13[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR13[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR13 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "TCRP13,TCR Parity Test Mode 13"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "TCRP14,TCR Parity Test Mode 14"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR14[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR14[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR14 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "TCRP14,TCR Parity Test Mode 14"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TCRP15,TCR Parity Test Mode 15"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR15[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR15[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR15 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "TCRP15,TCR Parity Test Mode 15"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCRP16,TCR Parity Test Mode 16"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR16[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR16[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR16 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "TCRP16,TCR Parity Test Mode 16"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "TCRP17,TCR Parity Test Mode 17"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR17[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR17[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR17 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "TCRP17,TCR Parity Test Mode 17"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TCRP18,TCR Parity Test Mode 18"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR18[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR18[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR18 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "TCRP18,TCR Parity Test Mode 18"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "TCRP19,TCR Parity Test Mode 19"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR19[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR19[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR19 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "TCRP19,TCR Parity Test Mode 19"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "TCRP20,TCR Parity Test Mode 20"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR20[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR20[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR20 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "TCRP20,TCR Parity Test Mode 20"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TCRP21,TCR Parity Test Mode 21"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR21[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR21[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR21 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "TCRP21,TCR Parity Test Mode 21"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TCRP22,TCR Parity Test Mode 22"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR22[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR22[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR22 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "TCRP22,TCR Parity Test Mode 22"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "TCRP23,TCR Parity Test Mode 23"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR23[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR23[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR23 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "TCRP23,TCR Parity Test Mode 23"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCRP24,TCR Parity Test Mode 24"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR24[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR24[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR24 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "TCRP24,TCR Parity Test Mode 24"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TCRP25,TCR Parity Test Mode 25"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR25[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR25[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR25 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "TCRP25,TCR Parity Test Mode 25"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TCRP26,TCR Parity Test Mode 26"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR26[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR26[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR26 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "TCRP26,TCR Parity Test Mode 26"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "TCRP27,TCR Parity Test Mode 27"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR27[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR27[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR27 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "TCRP27,TCR Parity Test Mode 27"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "TCRP28,TCR Parity Test Mode 28"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR28[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR28[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR28 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "TCRP28,TCR Parity Test Mode 28"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "TCRP29,TCR Parity Test Mode 29"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR29[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR29[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR29 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "TCRP29,TCR Parity Test Mode 29"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "TCRP30,TCR Parity Test Mode 30"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR30[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR30[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR30 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "TCRP30,TCR Parity Test Mode 30"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "TCRP31,TCR Parity Test Mode 31"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR31[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR31[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR31 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "TCRP31,TCR Parity Test Mode 31"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCRP32,TCR Parity Test Mode 32"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR32[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR32[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR32 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "TCRP32,TCR Parity Test Mode 32"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TCRP33,TCR Parity Test Mode 33"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR33[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR33[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR33 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "TCRP33,TCR Parity Test Mode 33"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "TCRP34,TCR Parity Test Mode 34"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR34[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR34[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR34 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "TCRP34,TCR Parity Test Mode 34"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "TCRP35,TCR Parity Test Mode 35"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR35[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR35[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR35 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "TCRP35,TCR Parity Test Mode 35"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TCRP36,TCR Parity Test Mode 36"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR36[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR36[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR36 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "TCRP36,TCR Parity Test Mode 36"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TCRP37,TCR Parity Test Mode 37"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR37[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR37[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR37 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "TCRP37,TCR Parity Test Mode 37"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TCRP38,TCR Parity Test Mode 38"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR38[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR38[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR38 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "TCRP38,TCR Parity Test Mode 38"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TCRP39,TCR Parity Test Mode 39"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR39[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR39[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR39 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "TCRP39,TCR Parity Test Mode 39"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCRP40,TCR Parity Test Mode 40"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR40[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR40[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR40 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "TCRP40,TCR Parity Test Mode 40"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "TCRP41,TCR Parity Test Mode 41"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR41[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR41[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR41 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "TCRP41,TCR Parity Test Mode 41"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "TCRP42,TCR Parity Test Mode 42"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR42[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR42[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR42 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "TCRP42,TCR Parity Test Mode 42"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "TCRP43,TCR Parity Test Mode 43"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR43[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR43[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR43 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "TCRP43,TCR Parity Test Mode 43"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "TCRP44,TCR Parity Test Mode 44"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR44[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR44[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR44 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "TCRP44,TCR Parity Test Mode 44"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TCRP45,TCR Parity Test Mode 45"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR45[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR45[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR45 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "TCRP45,TCR Parity Test Mode 45"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "TCRP46,TCR Parity Test Mode 46"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR46[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR46[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR46 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "TCRP46,TCR Parity Test Mode 46"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "TCRP47,TCR Parity Test Mode 47"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR47[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR47[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR47 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "TCRP47,TCR Parity Test Mode 47"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCRP48,TCR Parity Test Mode 48"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR48[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR48[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR48 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "TCRP48,TCR Parity Test Mode 48"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "TCRP49,TCR Parity Test Mode 49"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR49[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR49[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR49 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "TCRP49,TCR Parity Test Mode 49"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TCRP50,TCR Parity Test Mode 50"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR50[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR50[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR50 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "TCRP50,TCR Parity Test Mode 50"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "TCRP51,TCR Parity Test Mode 51"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR51[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR51[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR51 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "TCRP51,TCR Parity Test Mode 51"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "TCRP52,TCR Parity Test Mode 52"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR52[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR52[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR52 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "TCRP52,TCR Parity Test Mode 52"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "TCRP53,TCR Parity Test Mode 53"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR53[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR53[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR53 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "TCRP53,TCR Parity Test Mode 53"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "TCRP54,TCR Parity Test Mode 54"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR54[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR54[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR54 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "TCRP54,TCR Parity Test Mode 54"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "TCRP55,TCR Parity Test Mode 55"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR55[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR55[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR55 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "TCRP55,TCR Parity Test Mode 55"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCRP56,TCR Parity Test Mode 56"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR56[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR56[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR56 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "TCRP56,TCR Parity Test Mode 56"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TCRP57,TCR Parity Test Mode 57"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR57[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR57[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR57 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "TCRP57,TCR Parity Test Mode 57"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TCRP58,TCR Parity Test Mode 58"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR58[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR58[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR58 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "TCRP58,TCR Parity Test Mode 58"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TCRP59,TCR Parity Test Mode 59"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR59[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR59[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR59 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "TCRP59,TCR Parity Test Mode 59"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TCRP60,TCR Parity Test Mode 60"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR60[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR60[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR60 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "TCRP60,TCR Parity Test Mode 60"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TCRP61,TCR Parity Test Mode 61"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR61[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR61[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR61 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "TCRP61,TCR Parity Test Mode 61"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TCRP62,TCR Parity Test Mode 62"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR62[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR62[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR62 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "TCRP62,TCR Parity Test Mode 62"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TCRP63,TCR Parity Test Mode 63"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR63[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR63[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR63 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "TCRP63,TCR Parity Test Mode 63"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCRP64,TCR Parity Test Mode 64"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR64[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR64[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR64 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "TCRP64,TCR Parity Test Mode 64"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TCRP65,TCR Parity Test Mode 65"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR65[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR65[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR65 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "TCRP65,TCR Parity Test Mode 65"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TCRP66,TCR Parity Test Mode 66"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR66[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR66[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR66 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "TCRP66,TCR Parity Test Mode 66"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TCRP67,TCR Parity Test Mode 67"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR67[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR67[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR67 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "TCRP67,TCR Parity Test Mode 67"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TCRP68,TCR Parity Test Mode 68"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR68[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR68[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR68 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "TCRP68,TCR Parity Test Mode 68"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TCRP69,TCR Parity Test Mode 69"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR69[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR69[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR69 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "TCRP69,TCR Parity Test Mode 69"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TCRP70,TCR Parity Test Mode 70"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR70[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR70[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR70 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "TCRP70,TCR Parity Test Mode 70"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TCRP71,TCR Parity Test Mode 71"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR71[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR71[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR71 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "TCRP71,TCR Parity Test Mode 71"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCRP72,TCR Parity Test Mode 72"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR72[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR72[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR72 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "TCRP72,TCR Parity Test Mode 72"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TCRP73,TCR Parity Test Mode 73"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR73[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR73[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR73 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "TCRP73,TCR Parity Test Mode 73"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TCRP74,TCR Parity Test Mode 74"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR74[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR74[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR74 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "TCRP74,TCR Parity Test Mode 74"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TCRP75,TCR Parity Test Mode 75"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR75[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR75[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR75 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "TCRP75,TCR Parity Test Mode 75"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TCRP76,TCR Parity Test Mode 76"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR76[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR76[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR76 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "TCRP76,TCR Parity Test Mode 76"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TCRP77,TCR Parity Test Mode 77"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR77[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR77[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR77 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "TCRP77,TCR Parity Test Mode 77"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TCRP78,TCR Parity Test Mode 78"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR78[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR78[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR78 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "TCRP78,TCR Parity Test Mode 78"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TCRP79,TCR Parity Test Mode 79"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR79[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR79[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR79 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "TCRP79,TCR Parity Test Mode 79"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCRP80,TCR Parity Test Mode 80"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR80[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR80[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR80 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "TCRP80,TCR Parity Test Mode 80"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TCRP81,TCR Parity Test Mode 81"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR81[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR81[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR81 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "TCRP81,TCR Parity Test Mode 81"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TCRP82,TCR Parity Test Mode 82"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR82[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR82[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR82 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "TCRP82,TCR Parity Test Mode 82"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TCRP83,TCR Parity Test Mode 83"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR83[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR83[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR83 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "TCRP83,TCR Parity Test Mode 83"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TCRP84,TCR Parity Test Mode 84"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR84[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR84[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR84 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "TCRP84,TCR Parity Test Mode 84"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TCRP85,TCR Parity Test Mode 85"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR85[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR85[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR85 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "TCRP85,TCR Parity Test Mode 85"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TCRP86,TCR Parity Test Mode 86"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR86[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR86[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR86 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "TCRP86,TCR Parity Test Mode 86"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TCRP87,TCR Parity Test Mode 87"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR87[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR87[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR87 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "TCRP87,TCR Parity Test Mode 87"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCRP88,TCR Parity Test Mode 88"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR88[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR88[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR88 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "TCRP88,TCR Parity Test Mode 88"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TCRP89,TCR Parity Test Mode 89"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR89[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR89[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR89 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "TCRP89,TCR Parity Test Mode 89"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TCRP90,TCR Parity Test Mode 90"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR90[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR90[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR90 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "TCRP90,TCR Parity Test Mode 90"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TCRP91,TCR Parity Test Mode 91"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR91[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR91[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR91 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "TCRP91,TCR Parity Test Mode 91"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TCRP92,TCR Parity Test Mode 92"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR92[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR92[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR92 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "TCRP92,TCR Parity Test Mode 92"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TCRP93,TCR Parity Test Mode 93"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR93[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR93[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR93 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "TCRP93,TCR Parity Test Mode 93"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TCRP94,TCR Parity Test Mode 94"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR94[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR94[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR94 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "TCRP94,TCR Parity Test Mode 94"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TCRP95,TCR Parity Test Mode 95"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR95[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR95[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR95 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "TCRP95,TCR Parity Test Mode 95"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCRP96,TCR Parity Test Mode 96"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR96[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR96[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR96 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "TCRP96,TCR Parity Test Mode 96"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TCRP97,TCR Parity Test Mode 97"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR97[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR97[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR97 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "TCRP97,TCR Parity Test Mode 97"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TCRP98,TCR Parity Test Mode 98"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR98[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR98[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR98 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "TCRP98,TCR Parity Test Mode 98"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TCRP99,TCR Parity Test Mode 99"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR99[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR99[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR99 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "TCRP99,TCR Parity Test Mode 99"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TCRP100,TCR Parity Test Mode 100"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR100[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR100[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR100 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "TCRP100,TCR Parity Test Mode 100"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TCRP101,TCR Parity Test Mode 101"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR101[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR101[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR101 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "TCRP101,TCR Parity Test Mode 101"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "TCRP102,TCR Parity Test Mode 102"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR102[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR102[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR102 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "TCRP102,TCR Parity Test Mode 102"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "TCRP103,TCR Parity Test Mode 103"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR103[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR103[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR103 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "TCRP103,TCR Parity Test Mode 103"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCRP104,TCR Parity Test Mode 104"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR104[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR104[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR104 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "TCRP104,TCR Parity Test Mode 104"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TCRP105,TCR Parity Test Mode 105"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR105[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR105[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR105 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "TCRP105,TCR Parity Test Mode 105"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "TCRP106,TCR Parity Test Mode 106"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR106[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR106[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR106 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "TCRP106,TCR Parity Test Mode 106"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "TCRP107,TCR Parity Test Mode 107"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR107[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR107[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR107 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "TCRP107,TCR Parity Test Mode 107"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "TCRP108,TCR Parity Test Mode 108"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR108[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR108[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR108 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "TCRP108,TCR Parity Test Mode 108"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "TCRP109,TCR Parity Test Mode 109"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR109[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR109[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR109 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "TCRP109,TCR Parity Test Mode 109"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "TCRP110,TCR Parity Test Mode 110"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR110[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR110[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR110 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "TCRP110,TCR Parity Test Mode 110"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "TCRP111,TCR Parity Test Mode 111"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR111[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR111[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR111 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "TCRP111,TCR Parity Test Mode 111"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCRP112,TCR Parity Test Mode 112"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR112[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR112[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR112 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "TCRP112,TCR Parity Test Mode 112"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "TCRP113,TCR Parity Test Mode 113"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR113[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR113[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR113 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "TCRP113,TCR Parity Test Mode 113"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "TCRP114,TCR Parity Test Mode 114"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR114[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR114[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR114 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "TCRP114,TCR Parity Test Mode 114"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "TCRP115,TCR Parity Test Mode 115"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR115[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR115[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR115 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "TCRP115,TCR Parity Test Mode 115"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "TCRP116,TCR Parity Test Mode 116"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR116[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR116[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR116 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "TCRP116,TCR Parity Test Mode 116"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TCRP117,TCR Parity Test Mode 117"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR117[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR117[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR117 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "TCRP117,TCR Parity Test Mode 117"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "TCRP118,TCR Parity Test Mode 118"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR118[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR118[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR118 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "TCRP118,TCR Parity Test Mode 118"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "TCRP119,TCR Parity Test Mode 119"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR119[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR119[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR119 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "TCRP119,TCR Parity Test Mode 119"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCRP120,TCR Parity Test Mode 120"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR120[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR120[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR120 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "TCRP120,TCR Parity Test Mode 120"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "TCRP121,TCR Parity Test Mode 121"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR121[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR121[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR121 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "TCRP121,TCR Parity Test Mode 121"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "TCRP122,TCR Parity Test Mode 122"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR122[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR122[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR122 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "TCRP122,TCR Parity Test Mode 122"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "TCRP123,TCR Parity Test Mode 123"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR123[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR123[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR123 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "TCRP123,TCR Parity Test Mode 123"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "TCRP124,TCR Parity Test Mode 124"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR124[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR124[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR124 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "TCRP124,TCR Parity Test Mode 124"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "TCRP125,TCR Parity Test Mode 125"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR125[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR125[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR125 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "TCRP125,TCR Parity Test Mode 125"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "TCRP126,TCR Parity Test Mode 126"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR126[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR126[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR126 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "TCRP126,TCR Parity Test Mode 126"
|
|
endif
|
|
if (((per.l(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "TCRP127,TCR Parity Test Mode 127"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR127[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR127[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR127 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "TCRP127,TCR Parity Test Mode 127"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
tree "TU RAM (Transfer Configuration RAM)"
|
|
tree "Normal Mode"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCR0,Transfer Configuration RAM 0"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TCR1,Transfer Configuration RAM 1"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TCR2,Transfer Configuration RAM 2"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TCR3,Transfer Configuration RAM 3"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR4,Transfer Configuration RAM 4"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR5,Transfer Configuration RAM 5"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TCR6,Transfer Configuration RAM 6"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TCR7,Transfer Configuration RAM 7"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCR8,Transfer Configuration RAM 8"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TCR9,Transfer Configuration RAM 9"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCR10,Transfer Configuration RAM 10"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCR11,Transfer Configuration RAM 11"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCR12,Transfer Configuration RAM 12"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TCR13,Transfer Configuration RAM 13"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCR14,Transfer Configuration RAM 14"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCR15,Transfer Configuration RAM 15"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCR16,Transfer Configuration RAM 16"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TCR17,Transfer Configuration RAM 17"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCR18,Transfer Configuration RAM 18"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TCR19,Transfer Configuration RAM 19"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCR20,Transfer Configuration RAM 20"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TCR21,Transfer Configuration RAM 21"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCR22,Transfer Configuration RAM 22"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TCR23,Transfer Configuration RAM 23"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR24,Transfer Configuration RAM 24"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TCR25,Transfer Configuration RAM 25"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TCR26,Transfer Configuration RAM 26"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TCR27,Transfer Configuration RAM 27"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TCR28,Transfer Configuration RAM 28"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TCR29,Transfer Configuration RAM 29"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TCR30,Transfer Configuration RAM 30"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TCR31,Transfer Configuration RAM 31"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCR32,Transfer Configuration RAM 32"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TCR33,Transfer Configuration RAM 33"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TCR34,Transfer Configuration RAM 34"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TCR35,Transfer Configuration RAM 35"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TCR36,Transfer Configuration RAM 36"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TCR37,Transfer Configuration RAM 37"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TCR38,Transfer Configuration RAM 38"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TCR39,Transfer Configuration RAM 39"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCR40,Transfer Configuration RAM 40"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TCR41,Transfer Configuration RAM 41"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TCR42,Transfer Configuration RAM 42"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TCR43,Transfer Configuration RAM 43"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TCR44,Transfer Configuration RAM 44"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TCR45,Transfer Configuration RAM 45"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TCR46,Transfer Configuration RAM 46"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TCR47,Transfer Configuration RAM 47"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCR48,Transfer Configuration RAM 48"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TCR49,Transfer Configuration RAM 49"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TCR50,Transfer Configuration RAM 50"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TCR51,Transfer Configuration RAM 51"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TCR52,Transfer Configuration RAM 52"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TCR53,Transfer Configuration RAM 53"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TCR54,Transfer Configuration RAM 54"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TCR55,Transfer Configuration RAM 55"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCR56,Transfer Configuration RAM 56"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TCR57,Transfer Configuration RAM 57"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TCR58,Transfer Configuration RAM 58"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TCR59,Transfer Configuration RAM 59"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TCR60,Transfer Configuration RAM 60"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TCR61,Transfer Configuration RAM 61"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TCR62,Transfer Configuration RAM 62"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TCR63,Transfer Configuration RAM 63"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCR64,Transfer Configuration RAM 64"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TCR65,Transfer Configuration RAM 65"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TCR66,Transfer Configuration RAM 66"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TCR67,Transfer Configuration RAM 67"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TCR68,Transfer Configuration RAM 68"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TCR69,Transfer Configuration RAM 69"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TCR70,Transfer Configuration RAM 70"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TCR71,Transfer Configuration RAM 71"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCR72,Transfer Configuration RAM 72"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TCR73,Transfer Configuration RAM 73"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TCR74,Transfer Configuration RAM 74"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TCR75,Transfer Configuration RAM 75"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TCR76,Transfer Configuration RAM 76"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TCR77,Transfer Configuration RAM 77"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TCR78,Transfer Configuration RAM 78"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TCR79,Transfer Configuration RAM 79"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCR80,Transfer Configuration RAM 80"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TCR81,Transfer Configuration RAM 81"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TCR82,Transfer Configuration RAM 82"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TCR83,Transfer Configuration RAM 83"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TCR84,Transfer Configuration RAM 84"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TCR85,Transfer Configuration RAM 85"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TCR86,Transfer Configuration RAM 86"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TCR87,Transfer Configuration RAM 87"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCR88,Transfer Configuration RAM 88"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TCR89,Transfer Configuration RAM 89"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TCR90,Transfer Configuration RAM 90"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TCR91,Transfer Configuration RAM 91"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TCR92,Transfer Configuration RAM 92"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TCR93,Transfer Configuration RAM 93"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TCR94,Transfer Configuration RAM 94"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TCR95,Transfer Configuration RAM 95"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCR96,Transfer Configuration RAM 96"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TCR97,Transfer Configuration RAM 97"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TCR98,Transfer Configuration RAM 98"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TCR99,Transfer Configuration RAM 99"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TCR100,Transfer Configuration RAM 100"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TCR101,Transfer Configuration RAM 101"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TCR102,Transfer Configuration RAM 102"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TCR103,Transfer Configuration RAM 103"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCR104,Transfer Configuration RAM 104"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TCR105,Transfer Configuration RAM 105"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TCR106,Transfer Configuration RAM 106"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TCR107,Transfer Configuration RAM 107"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TCR108,Transfer Configuration RAM 108"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TCR109,Transfer Configuration RAM 109"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TCR110,Transfer Configuration RAM 110"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TCR111,Transfer Configuration RAM 111"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCR112,Transfer Configuration RAM 112"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TCR113,Transfer Configuration RAM 113"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TCR114,Transfer Configuration RAM 114"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TCR115,Transfer Configuration RAM 115"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TCR116,Transfer Configuration RAM 116"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TCR117,Transfer Configuration RAM 117"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TCR118,Transfer Configuration RAM 118"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TCR119,Transfer Configuration RAM 119"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCR120,Transfer Configuration RAM 120"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TCR121,Transfer Configuration RAM 121"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TCR122,Transfer Configuration RAM 122"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TCR123,Transfer Configuration RAM 123"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TCR124,Transfer Configuration RAM 124"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TCR125,Transfer Configuration RAM 125"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TCR126,Transfer Configuration RAM 126"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "TCR127,Transfer Configuration RAM 127"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
tree.end
|
|
sif (cpu()!="TMS570LC4357")
|
|
tree "TCR Parity Test Mode"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCRP0,TCR Parity test mode 0"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR0[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR0[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR0 byte 0" "No parity,Parity"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TCRP1,TCR Parity test mode 1"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR1[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR1[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR1 byte 0" "No parity,Parity"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TCRP2,TCR Parity test mode 2"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR2[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR2[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR2 byte 0" "No parity,Parity"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TCRP3,TCR Parity test mode 3"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR3[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR3[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR3 byte 0" "No parity,Parity"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TCRP4,TCR Parity test mode 4"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR4[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR4[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR4 byte 0" "No parity,Parity"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TCRP5,TCR Parity test mode 5"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR5[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR5[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR5 byte 0" "No parity,Parity"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TCRP6,TCR Parity test mode 6"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR6[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR6[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR6 byte 0" "No parity,Parity"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "TCRP7,TCR Parity test mode 7"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR7[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR7[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR7 byte 0" "No parity,Parity"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCRP8,TCR Parity test mode 8"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR8[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR8[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR8 byte 0" "No parity,Parity"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TCRP9,TCR Parity test mode 9"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR9[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR9[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR9 byte 0" "No parity,Parity"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "TCRP10,TCR Parity test mode 10"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR10[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR10[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR10 byte 0" "No parity,Parity"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "TCRP11,TCR Parity test mode 11"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR11[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR11[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR11 byte 0" "No parity,Parity"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "TCRP12,TCR Parity test mode 12"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR12[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR12[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR12 byte 0" "No parity,Parity"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "TCRP13,TCR Parity test mode 13"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR13[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR13[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR13 byte 0" "No parity,Parity"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "TCRP14,TCR Parity test mode 14"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR14[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR14[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR14 byte 0" "No parity,Parity"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TCRP15,TCR Parity test mode 15"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR15[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR15[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR15 byte 0" "No parity,Parity"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCRP16,TCR Parity test mode 16"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR16[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR16[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR16 byte 0" "No parity,Parity"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "TCRP17,TCR Parity test mode 17"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR17[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR17[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR17 byte 0" "No parity,Parity"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TCRP18,TCR Parity test mode 18"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR18[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR18[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR18 byte 0" "No parity,Parity"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "TCRP19,TCR Parity test mode 19"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR19[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR19[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR19 byte 0" "No parity,Parity"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "TCRP20,TCR Parity test mode 20"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR20[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR20[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR20 byte 0" "No parity,Parity"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TCRP21,TCR Parity test mode 21"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR21[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR21[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR21 byte 0" "No parity,Parity"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TCRP22,TCR Parity test mode 22"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR22[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR22[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR22 byte 0" "No parity,Parity"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "TCRP23,TCR Parity test mode 23"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR23[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR23[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR23 byte 0" "No parity,Parity"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCRP24,TCR Parity test mode 24"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR24[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR24[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR24 byte 0" "No parity,Parity"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TCRP25,TCR Parity test mode 25"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR25[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR25[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR25 byte 0" "No parity,Parity"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TCRP26,TCR Parity test mode 26"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR26[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR26[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR26 byte 0" "No parity,Parity"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "TCRP27,TCR Parity test mode 27"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR27[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR27[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR27 byte 0" "No parity,Parity"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "TCRP28,TCR Parity test mode 28"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR28[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR28[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR28 byte 0" "No parity,Parity"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "TCRP29,TCR Parity test mode 29"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR29[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR29[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR29 byte 0" "No parity,Parity"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "TCRP30,TCR Parity test mode 30"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR30[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR30[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR30 byte 0" "No parity,Parity"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "TCRP31,TCR Parity test mode 31"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR31[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR31[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR31 byte 0" "No parity,Parity"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCRP32,TCR Parity test mode 32"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR32[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR32[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR32 byte 0" "No parity,Parity"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TCRP33,TCR Parity test mode 33"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR33[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR33[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR33 byte 0" "No parity,Parity"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "TCRP34,TCR Parity test mode 34"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR34[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR34[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR34 byte 0" "No parity,Parity"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "TCRP35,TCR Parity test mode 35"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR35[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR35[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR35 byte 0" "No parity,Parity"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TCRP36,TCR Parity test mode 36"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR36[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR36[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR36 byte 0" "No parity,Parity"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TCRP37,TCR Parity test mode 37"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR37[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR37[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR37 byte 0" "No parity,Parity"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TCRP38,TCR Parity test mode 38"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR38[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR38[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR38 byte 0" "No parity,Parity"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TCRP39,TCR Parity test mode 39"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR39[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR39[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR39 byte 0" "No parity,Parity"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCRP40,TCR Parity test mode 40"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR40[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR40[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR40 byte 0" "No parity,Parity"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "TCRP41,TCR Parity test mode 41"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR41[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR41[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR41 byte 0" "No parity,Parity"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "TCRP42,TCR Parity test mode 42"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR42[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR42[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR42 byte 0" "No parity,Parity"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "TCRP43,TCR Parity test mode 43"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR43[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR43[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR43 byte 0" "No parity,Parity"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "TCRP44,TCR Parity test mode 44"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR44[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR44[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR44 byte 0" "No parity,Parity"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TCRP45,TCR Parity test mode 45"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR45[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR45[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR45 byte 0" "No parity,Parity"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "TCRP46,TCR Parity test mode 46"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR46[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR46[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR46 byte 0" "No parity,Parity"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "TCRP47,TCR Parity test mode 47"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR47[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR47[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR47 byte 0" "No parity,Parity"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCRP48,TCR Parity test mode 48"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR48[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR48[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR48 byte 0" "No parity,Parity"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "TCRP49,TCR Parity test mode 49"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR49[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR49[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR49 byte 0" "No parity,Parity"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TCRP50,TCR Parity test mode 50"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR50[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR50[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR50 byte 0" "No parity,Parity"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "TCRP51,TCR Parity test mode 51"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR51[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR51[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR51 byte 0" "No parity,Parity"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "TCRP52,TCR Parity test mode 52"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR52[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR52[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR52 byte 0" "No parity,Parity"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "TCRP53,TCR Parity test mode 53"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR53[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR53[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR53 byte 0" "No parity,Parity"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "TCRP54,TCR Parity test mode 54"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR54[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR54[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR54 byte 0" "No parity,Parity"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "TCRP55,TCR Parity test mode 55"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR55[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR55[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR55 byte 0" "No parity,Parity"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCRP56,TCR Parity test mode 56"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR56[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR56[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR56 byte 0" "No parity,Parity"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TCRP57,TCR Parity test mode 57"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR57[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR57[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR57 byte 0" "No parity,Parity"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TCRP58,TCR Parity test mode 58"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR58[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR58[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR58 byte 0" "No parity,Parity"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TCRP59,TCR Parity test mode 59"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR59[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR59[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR59 byte 0" "No parity,Parity"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TCRP60,TCR Parity test mode 60"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR60[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR60[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR60 byte 0" "No parity,Parity"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TCRP61,TCR Parity test mode 61"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR61[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR61[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR61 byte 0" "No parity,Parity"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TCRP62,TCR Parity test mode 62"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR62[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR62[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR62 byte 0" "No parity,Parity"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TCRP63,TCR Parity test mode 63"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR63[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR63[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR63 byte 0" "No parity,Parity"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCRP64,TCR Parity test mode 64"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR64[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR64[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR64 byte 0" "No parity,Parity"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TCRP65,TCR Parity test mode 65"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR65[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR65[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR65 byte 0" "No parity,Parity"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TCRP66,TCR Parity test mode 66"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR66[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR66[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR66 byte 0" "No parity,Parity"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TCRP67,TCR Parity test mode 67"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR67[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR67[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR67 byte 0" "No parity,Parity"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TCRP68,TCR Parity test mode 68"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR68[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR68[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR68 byte 0" "No parity,Parity"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TCRP69,TCR Parity test mode 69"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR69[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR69[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR69 byte 0" "No parity,Parity"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TCRP70,TCR Parity test mode 70"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR70[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR70[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR70 byte 0" "No parity,Parity"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TCRP71,TCR Parity test mode 71"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR71[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR71[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR71 byte 0" "No parity,Parity"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCRP72,TCR Parity test mode 72"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR72[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR72[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR72 byte 0" "No parity,Parity"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TCRP73,TCR Parity test mode 73"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR73[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR73[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR73 byte 0" "No parity,Parity"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TCRP74,TCR Parity test mode 74"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR74[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR74[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR74 byte 0" "No parity,Parity"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TCRP75,TCR Parity test mode 75"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR75[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR75[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR75 byte 0" "No parity,Parity"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TCRP76,TCR Parity test mode 76"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR76[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR76[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR76 byte 0" "No parity,Parity"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TCRP77,TCR Parity test mode 77"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR77[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR77[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR77 byte 0" "No parity,Parity"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TCRP78,TCR Parity test mode 78"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR78[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR78[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR78 byte 0" "No parity,Parity"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TCRP79,TCR Parity test mode 79"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR79[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR79[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR79 byte 0" "No parity,Parity"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCRP80,TCR Parity test mode 80"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR80[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR80[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR80 byte 0" "No parity,Parity"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TCRP81,TCR Parity test mode 81"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR81[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR81[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR81 byte 0" "No parity,Parity"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TCRP82,TCR Parity test mode 82"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR82[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR82[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR82 byte 0" "No parity,Parity"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TCRP83,TCR Parity test mode 83"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR83[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR83[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR83 byte 0" "No parity,Parity"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TCRP84,TCR Parity test mode 84"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR84[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR84[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR84 byte 0" "No parity,Parity"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TCRP85,TCR Parity test mode 85"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR85[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR85[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR85 byte 0" "No parity,Parity"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TCRP86,TCR Parity test mode 86"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR86[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR86[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR86 byte 0" "No parity,Parity"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TCRP87,TCR Parity test mode 87"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR87[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR87[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR87 byte 0" "No parity,Parity"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCRP88,TCR Parity test mode 88"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR88[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR88[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR88 byte 0" "No parity,Parity"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TCRP89,TCR Parity test mode 89"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR89[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR89[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR89 byte 0" "No parity,Parity"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TCRP90,TCR Parity test mode 90"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR90[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR90[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR90 byte 0" "No parity,Parity"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TCRP91,TCR Parity test mode 91"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR91[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR91[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR91 byte 0" "No parity,Parity"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TCRP92,TCR Parity test mode 92"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR92[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR92[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR92 byte 0" "No parity,Parity"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TCRP93,TCR Parity test mode 93"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR93[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR93[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR93 byte 0" "No parity,Parity"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TCRP94,TCR Parity test mode 94"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR94[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR94[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR94 byte 0" "No parity,Parity"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TCRP95,TCR Parity test mode 95"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR95[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR95[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR95 byte 0" "No parity,Parity"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCRP96,TCR Parity test mode 96"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR96[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR96[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR96 byte 0" "No parity,Parity"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TCRP97,TCR Parity test mode 97"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR97[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR97[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR97 byte 0" "No parity,Parity"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TCRP98,TCR Parity test mode 98"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR98[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR98[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR98 byte 0" "No parity,Parity"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TCRP99,TCR Parity test mode 99"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR99[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR99[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR99 byte 0" "No parity,Parity"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TCRP100,TCR Parity test mode 100"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR100[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR100[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR100 byte 0" "No parity,Parity"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TCRP101,TCR Parity test mode 101"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR101[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR101[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR101 byte 0" "No parity,Parity"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "TCRP102,TCR Parity test mode 102"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR102[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR102[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR102 byte 0" "No parity,Parity"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "TCRP103,TCR Parity test mode 103"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR103[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR103[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR103 byte 0" "No parity,Parity"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCRP104,TCR Parity test mode 104"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR104[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR104[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR104 byte 0" "No parity,Parity"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TCRP105,TCR Parity test mode 105"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR105[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR105[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR105 byte 0" "No parity,Parity"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "TCRP106,TCR Parity test mode 106"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR106[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR106[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR106 byte 0" "No parity,Parity"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "TCRP107,TCR Parity test mode 107"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR107[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR107[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR107 byte 0" "No parity,Parity"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "TCRP108,TCR Parity test mode 108"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR108[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR108[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR108 byte 0" "No parity,Parity"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "TCRP109,TCR Parity test mode 109"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR109[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR109[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR109 byte 0" "No parity,Parity"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "TCRP110,TCR Parity test mode 110"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR110[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR110[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR110 byte 0" "No parity,Parity"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "TCRP111,TCR Parity test mode 111"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR111[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR111[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR111 byte 0" "No parity,Parity"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCRP112,TCR Parity test mode 112"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR112[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR112[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR112 byte 0" "No parity,Parity"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "TCRP113,TCR Parity test mode 113"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR113[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR113[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR113 byte 0" "No parity,Parity"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "TCRP114,TCR Parity test mode 114"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR114[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR114[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR114 byte 0" "No parity,Parity"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "TCRP115,TCR Parity test mode 115"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR115[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR115[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR115 byte 0" "No parity,Parity"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "TCRP116,TCR Parity test mode 116"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR116[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR116[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR116 byte 0" "No parity,Parity"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TCRP117,TCR Parity test mode 117"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR117[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR117[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR117 byte 0" "No parity,Parity"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "TCRP118,TCR Parity test mode 118"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR118[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR118[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR118 byte 0" "No parity,Parity"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "TCRP119,TCR Parity test mode 119"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR119[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR119[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR119 byte 0" "No parity,Parity"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCRP120,TCR Parity test mode 120"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR120[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR120[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR120 byte 0" "No parity,Parity"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "TCRP121,TCR Parity test mode 121"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR121[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR121[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR121 byte 0" "No parity,Parity"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "TCRP122,TCR Parity test mode 122"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR122[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR122[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR122 byte 0" "No parity,Parity"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "TCRP123,TCR Parity test mode 123"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR123[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR123[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR123 byte 0" "No parity,Parity"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "TCRP124,TCR Parity test mode 124"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR124[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR124[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR124 byte 0" "No parity,Parity"
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "TCRP125,TCR Parity test mode 125"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR125[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR125[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR125 byte 0" "No parity,Parity"
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "TCRP126,TCR Parity test mode 126"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR126[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR126[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR126 byte 0" "No parity,Parity"
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "TCRP127,TCR Parity test mode 127"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR127[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR127[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR127 byte 0" "No parity,Parity"
|
|
tree.end
|
|
endif
|
|
tree "TCR ECC Test Mode"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCRE0,TCR Parity Test Mode 0"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 0"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TCRE1,TCR Parity Test Mode 1"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 1"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TCRE2,TCR Parity Test Mode 2"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 2"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TCRE3,TCR Parity Test Mode 3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 3"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TCRE4,TCR Parity Test Mode 4"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 4"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TCRE5,TCR Parity Test Mode 5"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 5"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TCRE6,TCR Parity Test Mode 6"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 6"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "TCRE7,TCR Parity Test Mode 7"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 7"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCRE8,TCR Parity Test Mode 8"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 8"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TCRE9,TCR Parity Test Mode 9"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 9"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "TCRE10,TCR Parity Test Mode 10"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 10"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "TCRE11,TCR Parity Test Mode 11"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 11"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "TCRE12,TCR Parity Test Mode 12"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 12"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "TCRE13,TCR Parity Test Mode 13"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 13"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "TCRE14,TCR Parity Test Mode 14"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 14"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TCRE15,TCR Parity Test Mode 15"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 15"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCRE16,TCR Parity Test Mode 16"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 16"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "TCRE17,TCR Parity Test Mode 17"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 17"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TCRE18,TCR Parity Test Mode 18"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 18"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "TCRE19,TCR Parity Test Mode 19"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 19"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "TCRE20,TCR Parity Test Mode 20"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 20"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TCRE21,TCR Parity Test Mode 21"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 21"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TCRE22,TCR Parity Test Mode 22"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 22"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "TCRE23,TCR Parity Test Mode 23"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 23"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCRE24,TCR Parity Test Mode 24"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 24"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TCRE25,TCR Parity Test Mode 25"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 25"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TCRE26,TCR Parity Test Mode 26"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 26"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "TCRE27,TCR Parity Test Mode 27"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 27"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "TCRE28,TCR Parity Test Mode 28"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 28"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "TCRE29,TCR Parity Test Mode 29"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 29"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "TCRE30,TCR Parity Test Mode 30"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 30"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "TCRE31,TCR Parity Test Mode 31"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 31"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCRE32,TCR Parity Test Mode 32"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 32"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TCRE33,TCR Parity Test Mode 33"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 33"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "TCRE34,TCR Parity Test Mode 34"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 34"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "TCRE35,TCR Parity Test Mode 35"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 35"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TCRE36,TCR Parity Test Mode 36"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 36"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TCRE37,TCR Parity Test Mode 37"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 37"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TCRE38,TCR Parity Test Mode 38"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 38"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TCRE39,TCR Parity Test Mode 39"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 39"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCRE40,TCR Parity Test Mode 40"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 40"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "TCRE41,TCR Parity Test Mode 41"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 41"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "TCRE42,TCR Parity Test Mode 42"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 42"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "TCRE43,TCR Parity Test Mode 43"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 43"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "TCRE44,TCR Parity Test Mode 44"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 44"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TCRE45,TCR Parity Test Mode 45"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 45"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "TCRE46,TCR Parity Test Mode 46"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 46"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "TCRE47,TCR Parity Test Mode 47"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 47"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCRE48,TCR Parity Test Mode 48"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 48"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "TCRE49,TCR Parity Test Mode 49"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 49"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TCRE50,TCR Parity Test Mode 50"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 50"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "TCRE51,TCR Parity Test Mode 51"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 51"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "TCRE52,TCR Parity Test Mode 52"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 52"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "TCRE53,TCR Parity Test Mode 53"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 53"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "TCRE54,TCR Parity Test Mode 54"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 54"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "TCRE55,TCR Parity Test Mode 55"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 55"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCRE56,TCR Parity Test Mode 56"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 56"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TCRE57,TCR Parity Test Mode 57"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 57"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TCRE58,TCR Parity Test Mode 58"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 58"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TCRE59,TCR Parity Test Mode 59"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 59"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TCRE60,TCR Parity Test Mode 60"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 60"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TCRE61,TCR Parity Test Mode 61"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 61"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TCRE62,TCR Parity Test Mode 62"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 62"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TCRE63,TCR Parity Test Mode 63"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 63"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCRE64,TCR Parity Test Mode 64"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 64"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TCRE65,TCR Parity Test Mode 65"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 65"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TCRE66,TCR Parity Test Mode 66"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 66"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TCRE67,TCR Parity Test Mode 67"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 67"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TCRE68,TCR Parity Test Mode 68"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 68"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TCRE69,TCR Parity Test Mode 69"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 69"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TCRE70,TCR Parity Test Mode 70"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 70"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TCRE71,TCR Parity Test Mode 71"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 71"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCRE72,TCR Parity Test Mode 72"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 72"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TCRE73,TCR Parity Test Mode 73"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 73"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TCRE74,TCR Parity Test Mode 74"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 74"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TCRE75,TCR Parity Test Mode 75"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 75"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TCRE76,TCR Parity Test Mode 76"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 76"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TCRE77,TCR Parity Test Mode 77"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 77"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TCRE78,TCR Parity Test Mode 78"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 78"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TCRE79,TCR Parity Test Mode 79"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 79"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCRE80,TCR Parity Test Mode 80"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 80"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TCRE81,TCR Parity Test Mode 81"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 81"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TCRE82,TCR Parity Test Mode 82"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 82"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TCRE83,TCR Parity Test Mode 83"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 83"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TCRE84,TCR Parity Test Mode 84"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 84"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TCRE85,TCR Parity Test Mode 85"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 85"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TCRE86,TCR Parity Test Mode 86"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 86"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TCRE87,TCR Parity Test Mode 87"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 87"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCRE88,TCR Parity Test Mode 88"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 88"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TCRE89,TCR Parity Test Mode 89"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 89"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TCRE90,TCR Parity Test Mode 90"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 90"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TCRE91,TCR Parity Test Mode 91"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 91"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TCRE92,TCR Parity Test Mode 92"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 92"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TCRE93,TCR Parity Test Mode 93"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 93"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TCRE94,TCR Parity Test Mode 94"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 94"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TCRE95,TCR Parity Test Mode 95"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 95"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCRE96,TCR Parity Test Mode 96"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 96"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TCRE97,TCR Parity Test Mode 97"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 97"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TCRE98,TCR Parity Test Mode 98"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 98"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TCRE99,TCR Parity Test Mode 99"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 99"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TCRE100,TCR Parity Test Mode 100"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 100"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TCRE101,TCR Parity Test Mode 101"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 101"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "TCRE102,TCR Parity Test Mode 102"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 102"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "TCRE103,TCR Parity Test Mode 103"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 103"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCRE104,TCR Parity Test Mode 104"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 104"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TCRE105,TCR Parity Test Mode 105"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 105"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "TCRE106,TCR Parity Test Mode 106"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 106"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "TCRE107,TCR Parity Test Mode 107"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 107"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "TCRE108,TCR Parity Test Mode 108"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 108"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "TCRE109,TCR Parity Test Mode 109"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 109"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "TCRE110,TCR Parity Test Mode 110"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 110"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "TCRE111,TCR Parity Test Mode 111"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 111"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCRE112,TCR Parity Test Mode 112"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 112"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "TCRE113,TCR Parity Test Mode 113"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 113"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "TCRE114,TCR Parity Test Mode 114"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 114"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "TCRE115,TCR Parity Test Mode 115"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 115"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "TCRE116,TCR Parity Test Mode 116"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 116"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TCRE117,TCR Parity Test Mode 117"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 117"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "TCRE118,TCR Parity Test Mode 118"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 118"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "TCRE119,TCR Parity Test Mode 119"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 119"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCRE120,TCR Parity Test Mode 120"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 120"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "TCRE121,TCR Parity Test Mode 121"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 121"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "TCRE122,TCR Parity Test Mode 122"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 122"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "TCRE123,TCR Parity Test Mode 123"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 123"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "TCRE124,TCR Parity Test Mode 124"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 124"
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "TCRE125,TCR Parity Test Mode 125"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 125"
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "TCRE126,TCR Parity Test Mode 126"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 126"
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "TCRE127,TCR Parity Test Mode 127"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ECCINF ,ECC data of TCR RAM location 127"
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "TU RAM (Transfer Configuration RAM)"
|
|
tree "Normal Mode"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCR0,Transfer Configuration RAM 0"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TCR1,Transfer Configuration RAM 1"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TCR2,Transfer Configuration RAM 2"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TCR3,Transfer Configuration RAM 3"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR4,Transfer Configuration RAM 4"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR5,Transfer Configuration RAM 5"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TCR6,Transfer Configuration RAM 6"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TCR7,Transfer Configuration RAM 7"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCR8,Transfer Configuration RAM 8"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TCR9,Transfer Configuration RAM 9"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCR10,Transfer Configuration RAM 10"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCR11,Transfer Configuration RAM 11"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCR12,Transfer Configuration RAM 12"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TCR13,Transfer Configuration RAM 13"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCR14,Transfer Configuration RAM 14"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TCR15,Transfer Configuration RAM 15"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCR16,Transfer Configuration RAM 16"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TCR17,Transfer Configuration RAM 17"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCR18,Transfer Configuration RAM 18"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TCR19,Transfer Configuration RAM 19"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TCR20,Transfer Configuration RAM 20"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TCR21,Transfer Configuration RAM 21"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCR22,Transfer Configuration RAM 22"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TCR23,Transfer Configuration RAM 23"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR24,Transfer Configuration RAM 24"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TCR25,Transfer Configuration RAM 25"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TCR26,Transfer Configuration RAM 26"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TCR27,Transfer Configuration RAM 27"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TCR28,Transfer Configuration RAM 28"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TCR29,Transfer Configuration RAM 29"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TCR30,Transfer Configuration RAM 30"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TCR31,Transfer Configuration RAM 31"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCR32,Transfer Configuration RAM 32"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TCR33,Transfer Configuration RAM 33"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TCR34,Transfer Configuration RAM 34"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TCR35,Transfer Configuration RAM 35"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TCR36,Transfer Configuration RAM 36"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TCR37,Transfer Configuration RAM 37"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TCR38,Transfer Configuration RAM 38"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TCR39,Transfer Configuration RAM 39"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCR40,Transfer Configuration RAM 40"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TCR41,Transfer Configuration RAM 41"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TCR42,Transfer Configuration RAM 42"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TCR43,Transfer Configuration RAM 43"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TCR44,Transfer Configuration RAM 44"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TCR45,Transfer Configuration RAM 45"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TCR46,Transfer Configuration RAM 46"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TCR47,Transfer Configuration RAM 47"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCR48,Transfer Configuration RAM 48"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TCR49,Transfer Configuration RAM 49"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TCR50,Transfer Configuration RAM 50"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TCR51,Transfer Configuration RAM 51"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TCR52,Transfer Configuration RAM 52"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TCR53,Transfer Configuration RAM 53"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TCR54,Transfer Configuration RAM 54"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TCR55,Transfer Configuration RAM 55"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCR56,Transfer Configuration RAM 56"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TCR57,Transfer Configuration RAM 57"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TCR58,Transfer Configuration RAM 58"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TCR59,Transfer Configuration RAM 59"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TCR60,Transfer Configuration RAM 60"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TCR61,Transfer Configuration RAM 61"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TCR62,Transfer Configuration RAM 62"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TCR63,Transfer Configuration RAM 63"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCR64,Transfer Configuration RAM 64"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TCR65,Transfer Configuration RAM 65"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TCR66,Transfer Configuration RAM 66"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TCR67,Transfer Configuration RAM 67"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TCR68,Transfer Configuration RAM 68"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TCR69,Transfer Configuration RAM 69"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TCR70,Transfer Configuration RAM 70"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TCR71,Transfer Configuration RAM 71"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCR72,Transfer Configuration RAM 72"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TCR73,Transfer Configuration RAM 73"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TCR74,Transfer Configuration RAM 74"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TCR75,Transfer Configuration RAM 75"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TCR76,Transfer Configuration RAM 76"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TCR77,Transfer Configuration RAM 77"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TCR78,Transfer Configuration RAM 78"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TCR79,Transfer Configuration RAM 79"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCR80,Transfer Configuration RAM 80"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TCR81,Transfer Configuration RAM 81"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TCR82,Transfer Configuration RAM 82"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TCR83,Transfer Configuration RAM 83"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TCR84,Transfer Configuration RAM 84"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TCR85,Transfer Configuration RAM 85"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TCR86,Transfer Configuration RAM 86"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TCR87,Transfer Configuration RAM 87"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCR88,Transfer Configuration RAM 88"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TCR89,Transfer Configuration RAM 89"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TCR90,Transfer Configuration RAM 90"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TCR91,Transfer Configuration RAM 91"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TCR92,Transfer Configuration RAM 92"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TCR93,Transfer Configuration RAM 93"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TCR94,Transfer Configuration RAM 94"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TCR95,Transfer Configuration RAM 95"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCR96,Transfer Configuration RAM 96"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TCR97,Transfer Configuration RAM 97"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TCR98,Transfer Configuration RAM 98"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TCR99,Transfer Configuration RAM 99"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TCR100,Transfer Configuration RAM 100"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TCR101,Transfer Configuration RAM 101"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TCR102,Transfer Configuration RAM 102"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TCR103,Transfer Configuration RAM 103"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCR104,Transfer Configuration RAM 104"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TCR105,Transfer Configuration RAM 105"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TCR106,Transfer Configuration RAM 106"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TCR107,Transfer Configuration RAM 107"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TCR108,Transfer Configuration RAM 108"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TCR109,Transfer Configuration RAM 109"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TCR110,Transfer Configuration RAM 110"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TCR111,Transfer Configuration RAM 111"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCR112,Transfer Configuration RAM 112"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TCR113,Transfer Configuration RAM 113"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TCR114,Transfer Configuration RAM 114"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TCR115,Transfer Configuration RAM 115"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TCR116,Transfer Configuration RAM 116"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TCR117,Transfer Configuration RAM 117"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TCR118,Transfer Configuration RAM 118"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TCR119,Transfer Configuration RAM 119"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCR120,Transfer Configuration RAM 120"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TCR121,Transfer Configuration RAM 121"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TCR122,Transfer Configuration RAM 122"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TCR123,Transfer Configuration RAM 123"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TCR124,Transfer Configuration RAM 124"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TCR125,Transfer Configuration RAM 125"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TCR126,Transfer Configuration RAM 126"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "TCR127,Transfer Configuration RAM 127"
|
|
bitfld.long 0x00 18. " STXR ,Set transmit request" "Not set,Set"
|
|
bitfld.long 0x00 17. " THTSM ,Transfer header to system memory" "No transfer,Transfer"
|
|
bitfld.long 0x00 16. " TPTSM ,Transfer payload to system memory" "No transfer,Transfer"
|
|
newline
|
|
bitfld.long 0x00 15. " THTCC ,Transfer header to communication controller" "No transfer,Transfer"
|
|
bitfld.long 0x00 14. " TPTCC ,Transfer payload to communication controller" "No transfer,Transfer"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " TSO ,Transfer start offset"
|
|
tree.end
|
|
tree "TCR Parity Test Mode"
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCRP0,TCR Parity Test Mode 0"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR0[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR0[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR0 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "TCRP0,TCR Parity Test Mode 0"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TCRP1,TCR Parity Test Mode 1"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR1[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR1[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR1 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "TCRP1,TCR Parity Test Mode 1"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TCRP2,TCR Parity Test Mode 2"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR2[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR2[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR2 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "TCRP2,TCR Parity Test Mode 2"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TCRP3,TCR Parity Test Mode 3"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR3[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR3[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR3 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "TCRP3,TCR Parity Test Mode 3"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TCRP4,TCR Parity Test Mode 4"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR4[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR4[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR4 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "TCRP4,TCR Parity Test Mode 4"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TCRP5,TCR Parity Test Mode 5"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR5[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR5[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR5 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "TCRP5,TCR Parity Test Mode 5"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TCRP6,TCR Parity Test Mode 6"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR6[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR6[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR6 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "TCRP6,TCR Parity Test Mode 6"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "TCRP7,TCR Parity Test Mode 7"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR7[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR7[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR7 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "TCRP7,TCR Parity Test Mode 7"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCRP8,TCR Parity Test Mode 8"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR8[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR8[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR8 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "TCRP8,TCR Parity Test Mode 8"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "TCRP9,TCR Parity Test Mode 9"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR9[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR9[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR9 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "TCRP9,TCR Parity Test Mode 9"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "TCRP10,TCR Parity Test Mode 10"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR10[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR10[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR10 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "TCRP10,TCR Parity Test Mode 10"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "TCRP11,TCR Parity Test Mode 11"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR11[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR11[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR11 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "TCRP11,TCR Parity Test Mode 11"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "TCRP12,TCR Parity Test Mode 12"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR12[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR12[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR12 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "TCRP12,TCR Parity Test Mode 12"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "TCRP13,TCR Parity Test Mode 13"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR13[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR13[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR13 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "TCRP13,TCR Parity Test Mode 13"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "TCRP14,TCR Parity Test Mode 14"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR14[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR14[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR14 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "TCRP14,TCR Parity Test Mode 14"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TCRP15,TCR Parity Test Mode 15"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR15[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR15[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR15 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "TCRP15,TCR Parity Test Mode 15"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCRP16,TCR Parity Test Mode 16"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR16[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR16[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR16 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "TCRP16,TCR Parity Test Mode 16"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "TCRP17,TCR Parity Test Mode 17"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR17[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR17[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR17 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "TCRP17,TCR Parity Test Mode 17"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TCRP18,TCR Parity Test Mode 18"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR18[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR18[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR18 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "TCRP18,TCR Parity Test Mode 18"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "TCRP19,TCR Parity Test Mode 19"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR19[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR19[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR19 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "TCRP19,TCR Parity Test Mode 19"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "TCRP20,TCR Parity Test Mode 20"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR20[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR20[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR20 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "TCRP20,TCR Parity Test Mode 20"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "TCRP21,TCR Parity Test Mode 21"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR21[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR21[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR21 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "TCRP21,TCR Parity Test Mode 21"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TCRP22,TCR Parity Test Mode 22"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR22[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR22[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR22 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "TCRP22,TCR Parity Test Mode 22"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "TCRP23,TCR Parity Test Mode 23"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR23[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR23[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR23 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "TCRP23,TCR Parity Test Mode 23"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCRP24,TCR Parity Test Mode 24"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR24[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR24[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR24 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "TCRP24,TCR Parity Test Mode 24"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "TCRP25,TCR Parity Test Mode 25"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR25[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR25[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR25 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "TCRP25,TCR Parity Test Mode 25"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "TCRP26,TCR Parity Test Mode 26"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR26[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR26[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR26 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "TCRP26,TCR Parity Test Mode 26"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "TCRP27,TCR Parity Test Mode 27"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR27[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR27[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR27 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "TCRP27,TCR Parity Test Mode 27"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "TCRP28,TCR Parity Test Mode 28"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR28[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR28[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR28 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "TCRP28,TCR Parity Test Mode 28"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "TCRP29,TCR Parity Test Mode 29"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR29[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR29[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR29 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "TCRP29,TCR Parity Test Mode 29"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "TCRP30,TCR Parity Test Mode 30"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR30[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR30[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR30 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "TCRP30,TCR Parity Test Mode 30"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "TCRP31,TCR Parity Test Mode 31"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR31[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR31[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR31 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "TCRP31,TCR Parity Test Mode 31"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCRP32,TCR Parity Test Mode 32"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR32[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR32[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR32 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "TCRP32,TCR Parity Test Mode 32"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "TCRP33,TCR Parity Test Mode 33"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR33[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR33[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR33 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "TCRP33,TCR Parity Test Mode 33"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "TCRP34,TCR Parity Test Mode 34"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR34[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR34[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR34 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "TCRP34,TCR Parity Test Mode 34"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "TCRP35,TCR Parity Test Mode 35"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR35[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR35[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR35 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "TCRP35,TCR Parity Test Mode 35"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "TCRP36,TCR Parity Test Mode 36"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR36[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR36[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR36 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "TCRP36,TCR Parity Test Mode 36"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "TCRP37,TCR Parity Test Mode 37"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR37[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR37[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR37 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "TCRP37,TCR Parity Test Mode 37"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "TCRP38,TCR Parity Test Mode 38"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR38[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR38[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR38 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "TCRP38,TCR Parity Test Mode 38"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "TCRP39,TCR Parity Test Mode 39"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR39[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR39[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR39 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "TCRP39,TCR Parity Test Mode 39"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCRP40,TCR Parity Test Mode 40"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR40[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR40[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR40 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "TCRP40,TCR Parity Test Mode 40"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "TCRP41,TCR Parity Test Mode 41"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR41[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR41[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR41 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "TCRP41,TCR Parity Test Mode 41"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "TCRP42,TCR Parity Test Mode 42"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR42[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR42[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR42 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "TCRP42,TCR Parity Test Mode 42"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "TCRP43,TCR Parity Test Mode 43"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR43[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR43[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR43 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "TCRP43,TCR Parity Test Mode 43"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "TCRP44,TCR Parity Test Mode 44"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR44[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR44[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR44 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "TCRP44,TCR Parity Test Mode 44"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "TCRP45,TCR Parity Test Mode 45"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR45[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR45[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR45 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "TCRP45,TCR Parity Test Mode 45"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "TCRP46,TCR Parity Test Mode 46"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR46[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR46[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR46 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "TCRP46,TCR Parity Test Mode 46"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "TCRP47,TCR Parity Test Mode 47"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR47[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR47[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR47 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "TCRP47,TCR Parity Test Mode 47"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCRP48,TCR Parity Test Mode 48"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR48[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR48[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR48 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "TCRP48,TCR Parity Test Mode 48"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "TCRP49,TCR Parity Test Mode 49"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR49[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR49[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR49 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "TCRP49,TCR Parity Test Mode 49"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TCRP50,TCR Parity Test Mode 50"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR50[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR50[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR50 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "TCRP50,TCR Parity Test Mode 50"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "TCRP51,TCR Parity Test Mode 51"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR51[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR51[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR51 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "TCRP51,TCR Parity Test Mode 51"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "TCRP52,TCR Parity Test Mode 52"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR52[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR52[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR52 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "TCRP52,TCR Parity Test Mode 52"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "TCRP53,TCR Parity Test Mode 53"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR53[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR53[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR53 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "TCRP53,TCR Parity Test Mode 53"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "TCRP54,TCR Parity Test Mode 54"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR54[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR54[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR54 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "TCRP54,TCR Parity Test Mode 54"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "TCRP55,TCR Parity Test Mode 55"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR55[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR55[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR55 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "TCRP55,TCR Parity Test Mode 55"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCRP56,TCR Parity Test Mode 56"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR56[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR56[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR56 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "TCRP56,TCR Parity Test Mode 56"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "TCRP57,TCR Parity Test Mode 57"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR57[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR57[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR57 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "TCRP57,TCR Parity Test Mode 57"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TCRP58,TCR Parity Test Mode 58"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR58[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR58[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR58 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "TCRP58,TCR Parity Test Mode 58"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TCRP59,TCR Parity Test Mode 59"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR59[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR59[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR59 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "TCRP59,TCR Parity Test Mode 59"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TCRP60,TCR Parity Test Mode 60"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR60[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR60[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR60 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "TCRP60,TCR Parity Test Mode 60"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TCRP61,TCR Parity Test Mode 61"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR61[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR61[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR61 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "TCRP61,TCR Parity Test Mode 61"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TCRP62,TCR Parity Test Mode 62"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR62[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR62[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR62 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "TCRP62,TCR Parity Test Mode 62"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TCRP63,TCR Parity Test Mode 63"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR63[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR63[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR63 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "TCRP63,TCR Parity Test Mode 63"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCRP64,TCR Parity Test Mode 64"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR64[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR64[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR64 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "TCRP64,TCR Parity Test Mode 64"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TCRP65,TCR Parity Test Mode 65"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR65[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR65[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR65 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "TCRP65,TCR Parity Test Mode 65"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TCRP66,TCR Parity Test Mode 66"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR66[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR66[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR66 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "TCRP66,TCR Parity Test Mode 66"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TCRP67,TCR Parity Test Mode 67"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR67[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR67[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR67 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "TCRP67,TCR Parity Test Mode 67"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TCRP68,TCR Parity Test Mode 68"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR68[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR68[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR68 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "TCRP68,TCR Parity Test Mode 68"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TCRP69,TCR Parity Test Mode 69"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR69[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR69[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR69 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "TCRP69,TCR Parity Test Mode 69"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TCRP70,TCR Parity Test Mode 70"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR70[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR70[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR70 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "TCRP70,TCR Parity Test Mode 70"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TCRP71,TCR Parity Test Mode 71"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR71[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR71[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR71 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "TCRP71,TCR Parity Test Mode 71"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCRP72,TCR Parity Test Mode 72"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR72[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR72[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR72 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "TCRP72,TCR Parity Test Mode 72"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TCRP73,TCR Parity Test Mode 73"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR73[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR73[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR73 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "TCRP73,TCR Parity Test Mode 73"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TCRP74,TCR Parity Test Mode 74"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR74[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR74[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR74 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "TCRP74,TCR Parity Test Mode 74"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TCRP75,TCR Parity Test Mode 75"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR75[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR75[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR75 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "TCRP75,TCR Parity Test Mode 75"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TCRP76,TCR Parity Test Mode 76"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR76[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR76[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR76 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "TCRP76,TCR Parity Test Mode 76"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TCRP77,TCR Parity Test Mode 77"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR77[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR77[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR77 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "TCRP77,TCR Parity Test Mode 77"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TCRP78,TCR Parity Test Mode 78"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR78[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR78[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR78 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "TCRP78,TCR Parity Test Mode 78"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TCRP79,TCR Parity Test Mode 79"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR79[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR79[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR79 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "TCRP79,TCR Parity Test Mode 79"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCRP80,TCR Parity Test Mode 80"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR80[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR80[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR80 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "TCRP80,TCR Parity Test Mode 80"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TCRP81,TCR Parity Test Mode 81"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR81[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR81[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR81 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "TCRP81,TCR Parity Test Mode 81"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TCRP82,TCR Parity Test Mode 82"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR82[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR82[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR82 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "TCRP82,TCR Parity Test Mode 82"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TCRP83,TCR Parity Test Mode 83"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR83[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR83[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR83 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "TCRP83,TCR Parity Test Mode 83"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TCRP84,TCR Parity Test Mode 84"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR84[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR84[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR84 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "TCRP84,TCR Parity Test Mode 84"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TCRP85,TCR Parity Test Mode 85"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR85[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR85[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR85 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "TCRP85,TCR Parity Test Mode 85"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TCRP86,TCR Parity Test Mode 86"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR86[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR86[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR86 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "TCRP86,TCR Parity Test Mode 86"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TCRP87,TCR Parity Test Mode 87"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR87[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR87[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR87 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "TCRP87,TCR Parity Test Mode 87"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCRP88,TCR Parity Test Mode 88"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR88[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR88[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR88 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "TCRP88,TCR Parity Test Mode 88"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TCRP89,TCR Parity Test Mode 89"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR89[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR89[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR89 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "TCRP89,TCR Parity Test Mode 89"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TCRP90,TCR Parity Test Mode 90"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR90[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR90[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR90 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "TCRP90,TCR Parity Test Mode 90"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TCRP91,TCR Parity Test Mode 91"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR91[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR91[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR91 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "TCRP91,TCR Parity Test Mode 91"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TCRP92,TCR Parity Test Mode 92"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR92[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR92[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR92 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "TCRP92,TCR Parity Test Mode 92"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TCRP93,TCR Parity Test Mode 93"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR93[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR93[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR93 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "TCRP93,TCR Parity Test Mode 93"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TCRP94,TCR Parity Test Mode 94"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR94[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR94[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR94 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "TCRP94,TCR Parity Test Mode 94"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TCRP95,TCR Parity Test Mode 95"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR95[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR95[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR95 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "TCRP95,TCR Parity Test Mode 95"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCRP96,TCR Parity Test Mode 96"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR96[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR96[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR96 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "TCRP96,TCR Parity Test Mode 96"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TCRP97,TCR Parity Test Mode 97"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR97[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR97[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR97 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "TCRP97,TCR Parity Test Mode 97"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TCRP98,TCR Parity Test Mode 98"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR98[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR98[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR98 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "TCRP98,TCR Parity Test Mode 98"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TCRP99,TCR Parity Test Mode 99"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR99[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR99[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR99 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "TCRP99,TCR Parity Test Mode 99"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TCRP100,TCR Parity Test Mode 100"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR100[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR100[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR100 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "TCRP100,TCR Parity Test Mode 100"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TCRP101,TCR Parity Test Mode 101"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR101[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR101[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR101 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "TCRP101,TCR Parity Test Mode 101"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "TCRP102,TCR Parity Test Mode 102"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR102[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR102[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR102 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "TCRP102,TCR Parity Test Mode 102"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "TCRP103,TCR Parity Test Mode 103"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR103[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR103[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR103 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "TCRP103,TCR Parity Test Mode 103"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCRP104,TCR Parity Test Mode 104"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR104[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR104[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR104 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "TCRP104,TCR Parity Test Mode 104"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "TCRP105,TCR Parity Test Mode 105"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR105[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR105[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR105 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "TCRP105,TCR Parity Test Mode 105"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "TCRP106,TCR Parity Test Mode 106"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR106[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR106[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR106 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "TCRP106,TCR Parity Test Mode 106"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "TCRP107,TCR Parity Test Mode 107"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR107[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR107[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR107 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "TCRP107,TCR Parity Test Mode 107"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "TCRP108,TCR Parity Test Mode 108"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR108[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR108[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR108 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "TCRP108,TCR Parity Test Mode 108"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "TCRP109,TCR Parity Test Mode 109"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR109[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR109[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR109 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "TCRP109,TCR Parity Test Mode 109"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "TCRP110,TCR Parity Test Mode 110"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR110[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR110[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR110 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "TCRP110,TCR Parity Test Mode 110"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "TCRP111,TCR Parity Test Mode 111"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR111[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR111[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR111 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "TCRP111,TCR Parity Test Mode 111"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCRP112,TCR Parity Test Mode 112"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR112[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR112[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR112 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "TCRP112,TCR Parity Test Mode 112"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "TCRP113,TCR Parity Test Mode 113"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR113[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR113[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR113 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "TCRP113,TCR Parity Test Mode 113"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "TCRP114,TCR Parity Test Mode 114"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR114[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR114[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR114 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "TCRP114,TCR Parity Test Mode 114"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "TCRP115,TCR Parity Test Mode 115"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR115[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR115[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR115 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "TCRP115,TCR Parity Test Mode 115"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "TCRP116,TCR Parity Test Mode 116"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR116[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR116[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR116 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "TCRP116,TCR Parity Test Mode 116"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "TCRP117,TCR Parity Test Mode 117"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR117[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR117[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR117 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "TCRP117,TCR Parity Test Mode 117"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "TCRP118,TCR Parity Test Mode 118"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR118[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR118[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR118 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "TCRP118,TCR Parity Test Mode 118"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "TCRP119,TCR Parity Test Mode 119"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR119[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR119[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR119 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "TCRP119,TCR Parity Test Mode 119"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCRP120,TCR Parity Test Mode 120"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR120[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR120[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR120 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "TCRP120,TCR Parity Test Mode 120"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "TCRP121,TCR Parity Test Mode 121"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR121[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR121[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR121 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "TCRP121,TCR Parity Test Mode 121"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "TCRP122,TCR Parity Test Mode 122"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR122[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR122[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR122 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "TCRP122,TCR Parity Test Mode 122"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "TCRP123,TCR Parity Test Mode 123"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR123[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR123[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR123 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "TCRP123,TCR Parity Test Mode 123"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "TCRP124,TCR Parity Test Mode 124"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR124[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR124[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR124 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "TCRP124,TCR Parity Test Mode 124"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "TCRP125,TCR Parity Test Mode 125"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR125[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR125[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR125 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "TCRP125,TCR Parity Test Mode 125"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "TCRP126,TCR Parity Test Mode 126"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR126[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR126[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR126 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "TCRP126,TCR Parity Test Mode 126"
|
|
endif
|
|
if (((per.l.be(ad:0xFFF7A000+0x10))&0x100000)==0x100000)
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "TCRP127,TCR Parity Test Mode 127"
|
|
bitfld.long 0x00 16. " PAB2 ,Parity information for byte 2 of TCR127[18:16]" "No parity,Parity"
|
|
bitfld.long 0x00 8. " PAB1 ,Parity information for byte 1 of TCR127[15:8]" "No parity,Parity"
|
|
bitfld.long 0x00 0. " PAB0 ,Parity bit for TCR127 byte 0" "No parity,Parity"
|
|
else
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "TCRP127,TCR Parity Test Mode 127"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General-Purpose Input/Output)"
|
|
tree "GIO"
|
|
base ad:0xFFF7BC00
|
|
width 6.
|
|
sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L530-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L550-PGE"||cpu()=="RM48L550-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM42L432"||cpu()=="RM46L430-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM48L550-ZWT")
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal"
|
|
else
|
|
group.long 0x0++0x7
|
|
line.long 0x00 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal"
|
|
line.long 0x04 "PWDN,Power Down"
|
|
endif
|
|
width 8.
|
|
tree "GIO Interrupt Registers"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "INTDET,Interrupt Detect"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " INTDET_1_7 ,GIOB7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 14. " INTDET_1_6 ,GIOB6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTDET_1_5 ,GIOB5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 12. " INTDET_1_4 ,GIOB4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 Interrupt Detection Select" "Falling/rising,Both"
|
|
width 8.
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "POL,Interrupt Polarity"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " GIOPOL_1_7 ,GIOB7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 14. " GIOPOL_1_6 ,GIOB6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GIOPOL_1_5 ,GIOB5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 12. " GIOPOL_1_4 ,GIOB4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GIOPOL_1_3 ,GIOB3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 10. " GIOPOL_1_2 ,GIOB2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIOPOL_1_1 ,GIOB1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 8. " GIOPOL_1_0 ,GIOB0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " GIOPOL_0_7 ,GIOA7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 6. " GIOPOL_0_6 ,GIOA6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOPOL_0_5 ,GIOA5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 4. " GIOPOL_0_4 ,GIOA4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOPOL_0_3 ,GIOA3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 2. " GIOPOL_0_2 ,GIOA2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOPOL_0_1 ,GIOA1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 0. " GIOPOL_0_0 ,GIOA0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
width 8.
|
|
tree "GIO Interrupt Enable Registers"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ENASET,Interrupt Enable Set"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " GIOENASET_1_7 ,GIOB7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " GIOENASET_1_6 ,GIOB6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GIOENASET_1_5 ,GIOB5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " GIOENASET_1_4 ,GIOB4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GIOENASET_1_3 ,GIOB3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " GIOENASET_1_2 ,GIOB2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIOENASET_1_1 ,GIOB1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GIOENASET_1_0 ,GIOB0 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " GIOENASET_0_7 ,GIOA7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GIOENASET_0_6 ,GIOA6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOENASET_0_5 ,GIOA5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GIOENASET_0_4 ,GIOA4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOENASET_0_3 ,GIOA3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GIOENASET_0_2 ,GIOA2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOENASET_0_1 ,GIOA1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOENASET_0_0 ,GIOA0 Interrupt Enable" "Disabled,Enabled"
|
|
width 8.
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ENACLR,Interrupt Enable Clear"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " GIOENACLR_1_7 ,GIOB7 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " GIOENACLR_1_6 ,GIOB6 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GIOENACLR_1_5 ,GIOB5 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " GIOENACLR_1_4 ,GIOB4 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GIOENACLR_1_3 ,GIOB3 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " GIOENACLR_1_2 ,GIOB2 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIOENACLR_1_1 ,GIOB1 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " GIOENACLR_1_0 ,GIOB0 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " GIOENACLR_0_7 ,GIOA7 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " GIOENACLR_0_6 ,GIOA6 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOENACLR_0_5 ,GIOA5 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 4. " GIOENACLR_0_4 ,GIOA4 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOENACLR_0_3 ,GIOA3 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " GIOENACLR_0_2 ,GIOA2 Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOENACLR_0_1 ,GIOA1 Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " GIOENACLR_0_0 ,GIOA0 Interrupt Disable" "No,Yes"
|
|
tree.end
|
|
width 8.
|
|
tree "GIO Interrupt Priority Registers"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "LVLSET,Interrupt Priority Set"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " GIOLVLSET_1_7 ,GIOB7 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 14. " GIOLVLSET_1_6 ,GIOB6 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GIOLVLSET_1_5 ,GIOB5 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 12. " GIOLVLSET_1_4 ,GIOB4 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GIOLVLSET_1_3 ,GIOB3 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 10. " GIOLVLSET_1_2 ,GIOB2 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIOLVLSET_1_1 ,GIOB1 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 8. " GIOLVLSET_1_0 ,GIOB0 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " GIOLVLSET_0_7 ,GIOA7 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 6. " GIOLVLSET_0_6 ,GIOA6 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOLVLSET_0_5 ,GIOA5 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 4. " GIOLVLSET_0_4 ,GIOA4 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOLVLSET_0_3 ,GIOA3 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 2. " GIOLVLSET_0_2 ,GIOA2 High Priority Interrupt" "No effect,High priority"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOLVLSET_0_1 ,GIOA1 High Priority Interrupt" "No effect,High priority"
|
|
bitfld.long 0x00 0. " GIOLVLSET_0_0 ,GIOA0 High Priority Interrupt" "No effect,High priority"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "LVLCLR,Interrupt Priority Clear"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 15. " GIOLVLCLR_1_7 ,GIOB7 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 14. " GIOLVLCLR_1_6 ,GIOB6 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GIOLVLCLR_1_5 ,GIOB5 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 12. " GIOLVLCLR_1_4 ,GIOB4 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GIOLVLCLR_1_3 ,GIOB3 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 10. " GIOLVLCLR_1_2 ,GIOB2 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIOLVLCLR_1_1 ,GIOB1 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 8. " GIOLVLCLR_1_0 ,GIOB0 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " GIOLVLCLR_0_7 ,GIOA7 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 6. " GIOLVLCLR_0_6 ,GIOA6 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOLVLCLR_0_5 ,GIOA5 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 4. " GIOLVLCLR_0_4 ,GIOA4 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOLVLCLR_0_3 ,GIOA3 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 2. " GIOLVLCLR_0_2 ,GIOA2 Low Priority Interrupt" "No effect,Low priority"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOLVLCLR_0_1 ,GIOA1 Low Priority Interrupt" "No effect,Low priority"
|
|
bitfld.long 0x00 0. " GIOLVLCLR_0_0 ,GIOA0 Low Priority Interrupt" "No effect,Low priority"
|
|
tree.end
|
|
width 8.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLG,Interrupt Flag"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
eventfld.long 0x00 15. " GIOFLG_1_7 ,GIOB7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " GIOFLG_1_6 ,GIOB6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " GIOFLG_1_5 ,GIOB5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " GIOFLG_1_4 ,GIOB4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 Flag" "Not occurred,Occurred"
|
|
width 6.
|
|
tree "GIO Interrupt Offset Registers"
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "OFFA,Offset A"
|
|
in
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "EMUA,Emulation A"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..."
|
|
else
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
endif
|
|
hgroup.long 0x28++0x3
|
|
hide.long 0x0 "OFFB,Offset B"
|
|
in
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "EMUB,Emulation B"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..."
|
|
else
|
|
bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "GIOA"
|
|
base ad:0xFFF7BC00
|
|
width 9.
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DIR,Data Direction GIOA"
|
|
sif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE")
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled"
|
|
endif
|
|
width 9.
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DIN,Data Input GIOA"
|
|
bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High"
|
|
width 9.
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DOUT,Data Output GIOA"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High"
|
|
width 9.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PDR,Open Drain GIOA"
|
|
bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled"
|
|
width 9.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PULLDIS,Pull Disable GIOA"
|
|
bitfld.long 0x0 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes"
|
|
bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes"
|
|
bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes"
|
|
bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes"
|
|
bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes"
|
|
width 9.
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PSL,Pull Select GIOA"
|
|
bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up"
|
|
bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up"
|
|
bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up"
|
|
bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up"
|
|
bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT")
|
|
width 9.
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "SRS,Slew Rate Select GIOA"
|
|
bitfld.long 0x00 7. " GIOSRS7 ,GIO Slew Rate Select 7" "Normal,Slow"
|
|
bitfld.long 0x00 6. " GIOSRS6 ,GIO Slew Rate Select 6" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOSRS5 ,GIO Slew Rate Select 5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " GIOSRS4 ,GIO Slew Rate Select 4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOSRS3 ,GIO Slew Rate Select 3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " GIOSRS2 ,GIO Slew Rate Select 2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow"
|
|
bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "GIOB"
|
|
base ad:0xFFF7BC00
|
|
width 9.
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "DIR,Data Direction GIOB"
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled"
|
|
elif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled"
|
|
endif
|
|
width 9.
|
|
sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "DIN,Data Input GIOB"
|
|
bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High"
|
|
bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High"
|
|
bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High"
|
|
bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High"
|
|
else
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "DIN,Data Input GIOB"
|
|
bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High"
|
|
bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High"
|
|
endif
|
|
width 9.
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "DOUT,Data Output GIOB"
|
|
sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High"
|
|
width 9.
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PDR,Open Drain GIOB"
|
|
sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PULLDIS,Pull Disable GIOB"
|
|
sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
bitfld.long 0x0 7. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes"
|
|
bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes"
|
|
bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes"
|
|
bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes"
|
|
bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PSL,Pull Select GIOB"
|
|
sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT")
|
|
bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up"
|
|
bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up"
|
|
bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up"
|
|
bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up"
|
|
bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()=="RM48L550-ZWT")
|
|
group.long 0x138++0x3
|
|
line.long 0x0 "SRS,Slew Rate Select GIOB"
|
|
bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow"
|
|
bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0xFFF7D400
|
|
width 14.
|
|
sif (cpuis("RM48L950*"))
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x010000)==0x010000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word 0x00 0.--9. 1. " OA(9-0) ,Own address"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA(6-0) ,Own address"
|
|
endif
|
|
elif (cpu()=="TMS570LS3137-EP")
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word 0x00 0.--9. 1. " OA(9-0) ,Own address"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA(6-0) ,Own address"
|
|
endif
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2CIMR,I2C Interrupt Mask Register"
|
|
bitfld.word 0x00 6. " AASEN ,Address as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " SCDEN ,Stop condition interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " TXRDYEN ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RXRDYEN ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " ARDYEN ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " NACKEN ,No acknowledgement interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " ALEN ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CSTR,I2C Status Register"
|
|
sif (cpu()=="TMS570LS3137-EP")
|
|
eventfld.word 0x00 14. " SDIR ,Slave direction" "Receiver,Transmitter"
|
|
eventfld.word 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
|
|
newline
|
|
rbitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy"
|
|
rbitfld.word 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full"
|
|
newline
|
|
bitfld.word 0x00 10. " XSMT ,Transmit shift empty" "Empty,Not empty"
|
|
rbitfld.word 0x00 9. " AAS ,Address as slave" "Not slave,Slave"
|
|
newline
|
|
rbitfld.word 0x00 8. " AD0 ,Address zero status" "Not detected,Detected"
|
|
else
|
|
eventfld.word 0x00 14. " SDIR ,Slave transmitter direction enable" "Disabled,Enabled"
|
|
eventfld.word 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
|
|
newline
|
|
bitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy"
|
|
bitfld.word 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full"
|
|
newline
|
|
bitfld.word 0x00 10. " XSMT ,Transmit shift empty not" "Empty,Not empty"
|
|
bitfld.word 0x00 9. " AAS ,Address as slave" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8. " AD0 ,Address zero status" "Not detected,Detected"
|
|
endif
|
|
eventfld.word 0x00 5. " SCD ,Stop condition detect interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
sif (cpu()=="TMS570LS3137-EP")
|
|
bitfld.word 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.word 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.word 0x00 3. " RXRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgement interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2CCKL,I2C Clock Divider Low Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2CCKH,I2C Clock Control High Register"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2CCNT,I2C Data Count Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "I2CDRR,I2C Data Receive Register"
|
|
in
|
|
sif (cpuis("RM48L950*"))
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x010000)==0x010000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Receive data"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data"
|
|
endif
|
|
elif (cpu()=="TMS570LS3137-EP")
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Receive data"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Receive data"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data"
|
|
endif
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2CDXR,I2C Data Transmit Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATATX ,Transmit data"
|
|
sif (cpuis("RM48L950*"))
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08000000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08040000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x040000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x060000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08060000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08020000)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
endif
|
|
elif (cpu()=="TMS570LS3137-EP")
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x400)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x600)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x008)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x408)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x400)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x600)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x608)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x208)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
endif
|
|
endif
|
|
hgroup.word 0x28++0x01
|
|
hide.word 0x00 "I2CIVR,I2C Interrupt Vector Register"
|
|
in
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2CEMDR,I2C Extended Mode Register"
|
|
bitfld.word 0x00 1. " IGNACK ,Ignore NACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2CPSC,I2C Prescale Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Prescale"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "I2CPID1,I2C Peripheral ID Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLASS ,Peripheral class"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "I2CPID2,I2C Peripheral ID Register 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TYPE ,Peripheral type"
|
|
else
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2CPID2,I2C Peripheral ID Register 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TYPE ,Peripheral type"
|
|
endif
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "I2CDMACR,I2C DMA Control Register"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2CPFNC,I2C Pin Function Register"
|
|
bitfld.word 0x00 0. " PINFUNC ,SDA and SCL pin function" "I2C,I/O"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2CPDIR,I2C Pin Direction Register"
|
|
bitfld.word 0x00 1. " SDADIR ,SDA direction" "Input,Output"
|
|
bitfld.word 0x00 0. " SCLDIR ,SCL direction" "Input,Output"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2CDIN,I2C Data Input Register"
|
|
bitfld.word 0x00 1. " SDAIN ,Serial data in" "Low,High"
|
|
bitfld.word 0x00 0. " SCLIN ,Serial clock data in" "Low,High"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2CDOUT,I2C Data Output Register"
|
|
bitfld.word 0x00 1. " SDAOUT ,SDA data output" "Low,High"
|
|
bitfld.word 0x00 0. " SCLOUT ,SCL data output" "Low,High"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "I2CD_SET/CLR,I2C Data Register"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x04 1. " SDA ,Serial data" "Not set,Set"
|
|
setclrfld.word 0x00 0. 0x00 0. 0x04 0. " SCL ,Serial clock" "Not set,Set"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "I2CPDR,I2C Pin Open Drain Register"
|
|
bitfld.word 0x00 1. " SDAPDR ,SDA pin open drain disable" "No,Yes"
|
|
bitfld.word 0x00 0. " SCLPDR ,SCL pin open drain disable" "No,Yes"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "I2CPDIS,I2C Pull Disable Register"
|
|
bitfld.word 0x00 1. " SDAPDIS ,SDA pull disable" "No,Yes"
|
|
bitfld.word 0x00 0. " SCLPDIS ,SCL pull disable" "No,Yes"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "I2CPSEL,I2C Pull Select Register"
|
|
bitfld.word 0x00 1. " SDAPSEL ,SDA pull select" "Pull down,Pull up"
|
|
bitfld.word 0x00 0. " SCLPSEL ,SCL pull select" "Pull down,Pull up"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "I2CSRS,I2C Pins Slew Rate Select Register"
|
|
bitfld.word 0x00 1. " SDASRS ,SDA slew rate select" "Slow,Normal"
|
|
bitfld.word 0x00 0. " SCLSRS ,SCL slew rate select" "Slow,Normal"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NHET (New High End Timer)"
|
|
tree "NHET1"
|
|
base ad:0xFFF7B800
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "GCR,Global Control Register"
|
|
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..."
|
|
bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On"
|
|
line.long 0x04 "PFR,Prescaler Factor Register"
|
|
bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x0 "ADDR,Current Address Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address"
|
|
line.long 0x04 "OFF1,Offset Level 1 Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
line.long 0x08 "OFF2,Offset Level 2 Register"
|
|
hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "EXC1,Exception Control Register 1"
|
|
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
line.long 0x04 "EXC2,Exception Control Register 2"
|
|
eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET"
|
|
eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PRY,Interrupt Priority Register"
|
|
bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1"
|
|
bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1"
|
|
bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1"
|
|
bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1"
|
|
bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1"
|
|
bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1"
|
|
bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1"
|
|
bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1"
|
|
bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1"
|
|
bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1"
|
|
bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1"
|
|
bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1"
|
|
bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1"
|
|
bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1"
|
|
bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1"
|
|
bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1"
|
|
bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1"
|
|
bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1"
|
|
bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1"
|
|
bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1"
|
|
bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1"
|
|
bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1"
|
|
line.long 0x0C "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt"
|
|
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "HETAND,And Share Control Register"
|
|
bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x0 "HRSH,HR Share Control Register"
|
|
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared"
|
|
line.long 0x04 "XOR,HR XOR Control Register"
|
|
bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "REQDS,Request Destination Select Register"
|
|
bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both"
|
|
bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both"
|
|
bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both"
|
|
bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both"
|
|
bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both"
|
|
bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both"
|
|
bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA"
|
|
bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA"
|
|
bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA"
|
|
bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA"
|
|
newline
|
|
bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA"
|
|
bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA"
|
|
bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA"
|
|
bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA"
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "DIR,Direction Register"
|
|
bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output"
|
|
newline
|
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bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output"
|
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bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output"
|
|
rgroup.long 0x50++0x3
|
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line.long 0x00 "DIN,Input Data Register"
|
|
bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High"
|
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bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High"
|
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bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High"
|
|
newline
|
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bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High"
|
|
newline
|
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bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High"
|
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bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High"
|
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bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High"
|
|
newline
|
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bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High"
|
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bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High"
|
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bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High"
|
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bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High"
|
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newline
|
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bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High"
|
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bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High"
|
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bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High"
|
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bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High"
|
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newline
|
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bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High"
|
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bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High"
|
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bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High"
|
|
newline
|
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bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High"
|
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bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High"
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bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High"
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bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High"
|
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newline
|
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bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High"
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bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High"
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bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High"
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bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High"
|
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group.long 0x54++0x3
|
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line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register"
|
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setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High"
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setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High"
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setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High"
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newline
|
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setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High"
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setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High"
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newline
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setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High"
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setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High"
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setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High"
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setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High"
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setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High"
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setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High"
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newline
|
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setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High"
|
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setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High"
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setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High"
|
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setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High"
|
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setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High"
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setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High"
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High"
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setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High"
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High"
|
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group.long 0x60++0x0B
|
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line.long 0x00 "PDR,Open Drain Register"
|
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bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled"
|
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bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled"
|
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bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled"
|
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bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled"
|
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bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled"
|
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bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled"
|
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bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled"
|
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bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled"
|
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bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled"
|
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bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled"
|
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bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled"
|
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bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled"
|
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bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled"
|
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bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled"
|
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bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled"
|
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line.long 0x04 "PULDIS,Pull Disable Register"
|
|
bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select Register"
|
|
bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up"
|
|
bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up"
|
|
bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up"
|
|
bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up"
|
|
bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up"
|
|
bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up"
|
|
bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up"
|
|
bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up"
|
|
bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up"
|
|
bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "PAR,Parity Address Register"
|
|
hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset"
|
|
group.long 0x7C++0x0B
|
|
line.long 0x0 "PPR,Parity Pin Register"
|
|
bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High"
|
|
line.long 0x04 "SFPRLD,Suppresion Filter Preload Register"
|
|
bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
|
|
hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value"
|
|
line.long 0x08 "SFENA,Suppresion Filter Enable Register"
|
|
bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if ((per.l.be(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
endif
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
|
|
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output"
|
|
line.long 0x04 "PINDIS,Pin Disable Register"
|
|
bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
width 16.
|
|
group.long 0x9C++0x13 "HWAG Registers"
|
|
line.long 0x00 "HWAPINSEL,HWAG Pin Select Register"
|
|
bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "HWAGCR0,HWAG Control Register 0"
|
|
bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset"
|
|
line.long 0x08 "HWAGCR1,HWAG Control Register 1"
|
|
bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down"
|
|
line.long 0x0C "HWAGCR2,HWAG Control Register 2"
|
|
bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset"
|
|
bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising"
|
|
bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started"
|
|
line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High"
|
|
group.long 0xB8++0x27
|
|
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
|
|
eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending"
|
|
line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset"
|
|
line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset"
|
|
line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value"
|
|
line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value"
|
|
line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value"
|
|
line.long 0x18 "HWASTWD,HWAG Step Register"
|
|
bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072"
|
|
line.long 0x1C "HWATHNB,HWAG Teeth Number Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number"
|
|
line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value"
|
|
line.long 0x24 "HWAFIL,HWAG Filter Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value"
|
|
elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
|
|
group.long 0xA0++0x43
|
|
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
|
|
line.long 0x04 "HWAGCR1,HWAG Control Register 1"
|
|
line.long 0x08 "HWAGCR2,HWAG Control Register 2"
|
|
line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register"
|
|
line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register"
|
|
line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register"
|
|
line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
|
|
line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register"
|
|
line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
|
|
line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
|
|
line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
line.long 0x34 "HWASTWD,HWAG Step Register"
|
|
line.long 0x38 "HWATHNB,HWAG Teeth Number Register"
|
|
line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register"
|
|
line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "NHET2"
|
|
base ad:0xFFF7B900
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "GCR,Global Control Register"
|
|
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..."
|
|
bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On"
|
|
line.long 0x04 "PFR,Prescaler Factor Register"
|
|
bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x0 "ADDR,Current Address Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address"
|
|
line.long 0x04 "OFF1,Offset Level 1 Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
line.long 0x08 "OFF2,Offset Level 2 Register"
|
|
hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "EXC1,Exception Control Register 1"
|
|
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
line.long 0x04 "EXC2,Exception Control Register 2"
|
|
eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET"
|
|
eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PRY,Interrupt Priority Register"
|
|
bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1"
|
|
bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1"
|
|
bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1"
|
|
bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1"
|
|
bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1"
|
|
bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1"
|
|
bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1"
|
|
bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1"
|
|
bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1"
|
|
bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1"
|
|
bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1"
|
|
bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1"
|
|
bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1"
|
|
bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1"
|
|
bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1"
|
|
bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1"
|
|
bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1"
|
|
bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1"
|
|
bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1"
|
|
bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1"
|
|
bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1"
|
|
bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1"
|
|
line.long 0x0C "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt"
|
|
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "HETAND,And Share Control Register"
|
|
bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x0 "HRSH,HR Share Control Register"
|
|
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared"
|
|
line.long 0x04 "XOR,HR XOR Control Register"
|
|
bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "REQDS,Request Destination Select Register"
|
|
bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both"
|
|
bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both"
|
|
bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both"
|
|
bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both"
|
|
bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both"
|
|
bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both"
|
|
bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA"
|
|
bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA"
|
|
bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA"
|
|
bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA"
|
|
newline
|
|
bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA"
|
|
bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA"
|
|
bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA"
|
|
bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA"
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "DIR,Direction Register"
|
|
bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "DIN,Input Data Register"
|
|
bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High"
|
|
newline
|
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bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High"
|
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bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High"
|
|
newline
|
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bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High"
|
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bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High"
|
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bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High"
|
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newline
|
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bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High"
|
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bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High"
|
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bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High"
|
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bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High"
|
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group.long 0x54++0x3
|
|
line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High"
|
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setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High"
|
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setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High"
|
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setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High"
|
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setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High"
|
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setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High"
|
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High"
|
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group.long 0x60++0x0B
|
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line.long 0x00 "PDR,Open Drain Register"
|
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bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled"
|
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bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled"
|
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bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled"
|
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bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled"
|
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bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled"
|
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bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled"
|
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bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled"
|
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bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled"
|
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bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled"
|
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bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled"
|
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bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled"
|
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bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled"
|
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bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled"
|
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bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled"
|
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bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled"
|
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line.long 0x04 "PULDIS,Pull Disable Register"
|
|
bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select Register"
|
|
bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up"
|
|
bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up"
|
|
bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up"
|
|
bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up"
|
|
bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up"
|
|
bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up"
|
|
bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up"
|
|
bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up"
|
|
bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up"
|
|
bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "PAR,Parity Address Register"
|
|
hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset"
|
|
group.long 0x7C++0x0B
|
|
line.long 0x0 "PPR,Parity Pin Register"
|
|
bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High"
|
|
line.long 0x04 "SFPRLD,Suppresion Filter Preload Register"
|
|
bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
|
|
hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value"
|
|
line.long 0x08 "SFENA,Suppresion Filter Enable Register"
|
|
bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
if ((per.l(ad:0xFFF7B900+0x90)&0xF00)==0xA00)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if ((per.l.be(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
endif
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
|
|
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output"
|
|
line.long 0x04 "PINDIS,Pin Disable Register"
|
|
bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
width 16.
|
|
group.long 0x9C++0x13 "HWAG Registers"
|
|
line.long 0x00 "HWAPINSEL,HWAG Pin Select Register"
|
|
bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "HWAGCR0,HWAG Control Register 0"
|
|
bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset"
|
|
line.long 0x08 "HWAGCR1,HWAG Control Register 1"
|
|
bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down"
|
|
line.long 0x0C "HWAGCR2,HWAG Control Register 2"
|
|
bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset"
|
|
bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising"
|
|
bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started"
|
|
line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High"
|
|
group.long 0xB8++0x27
|
|
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
|
|
eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending"
|
|
line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset"
|
|
line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset"
|
|
line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value"
|
|
line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value"
|
|
line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value"
|
|
line.long 0x18 "HWASTWD,HWAG Step Register"
|
|
bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072"
|
|
line.long 0x1C "HWATHNB,HWAG Teeth Number Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number"
|
|
line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value"
|
|
line.long 0x24 "HWAFIL,HWAG Filter Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value"
|
|
elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
|
|
group.long 0xA0++0x43
|
|
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
|
|
line.long 0x04 "HWAGCR1,HWAG Control Register 1"
|
|
line.long 0x08 "HWAGCR2,HWAG Control Register 2"
|
|
line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register"
|
|
line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register"
|
|
line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register"
|
|
line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
|
|
line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register"
|
|
line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
|
|
line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
|
|
line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
line.long 0x34 "HWASTWD,HWAG Step Register"
|
|
line.long 0x38 "HWATHNB,HWAG Teeth Number Register"
|
|
line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register"
|
|
line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HTU (High End Timer Transfer Unit)"
|
|
tree "HTU1"
|
|
base ad:0xFFF7A400
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GC,Global Control Register"
|
|
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
|
|
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
|
|
line.long 0x04 "CPENA,Control Packet Enable Register"
|
|
bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0"
|
|
eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1"
|
|
eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2"
|
|
eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3"
|
|
eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number"
|
|
bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet"
|
|
endif
|
|
newline
|
|
width 16.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register"
|
|
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
|
|
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTMAP,Interrupt Mapping Register"
|
|
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
|
|
bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1"
|
|
bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1"
|
|
bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1"
|
|
bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1"
|
|
bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1"
|
|
bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1"
|
|
bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1"
|
|
bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1"
|
|
bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1"
|
|
bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1"
|
|
bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1"
|
|
newline
|
|
width 10.
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "INTOFF0,Interrupt Offset Register 0"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x0 "INTOFF1,Interrupt Offset Register 1"
|
|
in
|
|
newline
|
|
group.long 0x3C++0x23
|
|
line.long 0x00 "BIM,Buffer Initialization Mode Register"
|
|
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
|
|
bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special"
|
|
bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special"
|
|
bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special"
|
|
newline
|
|
bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special"
|
|
bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special"
|
|
bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special"
|
|
bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special"
|
|
line.long 0x04 "RLOSTFL,Request Lost Flag Register"
|
|
eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
|
|
eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested"
|
|
eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested"
|
|
eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested"
|
|
eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested"
|
|
eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested"
|
|
eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested"
|
|
eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested"
|
|
eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested"
|
|
line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register"
|
|
eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x0C "BERINTFL,BER Interrupt Flag Register"
|
|
eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "MP1S,Memory Protection 1 Start Address"
|
|
line.long 0x14 "MP1E,Memory Protection 1 End Address"
|
|
line.long 0x18 "DCTRL,Debug Control Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
|
|
bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled"
|
|
line.long 0x1C "WPR,Watch Point Register"
|
|
line.long 0x20 "WMR,Watch Mask Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ID,Module Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
|
|
group.long 0x64++0x07
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR,Parity Address Register"
|
|
eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected"
|
|
hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MPCS,Memory Protection Control and Status Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
|
|
line.long 0x04 "MP0S,Memory Protection Start Address Register"
|
|
line.long 0x08 "MP0E,Memory Protection End Address Register"
|
|
sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP"))
|
|
tree "Double Control Packet Configuration Memory"
|
|
base ad:0xFF4E0000
|
|
sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP")
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "IFADDRA,Initial main memory address Control Packet A"
|
|
line.long 0x04 "IFADDRB,Initial main memory address Control Packet B"
|
|
line.long 0x08 "IHADDRCT,Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "ITCOUNT,Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long 0x100++0xB
|
|
line.long 0x00 "CFADDRA,Current main memory address Control Packet A"
|
|
line.long 0x04 "CFADDRB,Current main memory address Control Packet B"
|
|
line.long 0x08 "CFCOUNT,Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
else
|
|
width 15.
|
|
group.long 0x0++0x0F "DCP0"
|
|
line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x0+0x100)++0xB
|
|
line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A"
|
|
line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B"
|
|
line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x10++0x0F "DCP1"
|
|
line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x10+0x100)++0xB
|
|
line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A"
|
|
line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B"
|
|
line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x20++0x0F "DCP2"
|
|
line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x20+0x100)++0xB
|
|
line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A"
|
|
line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B"
|
|
line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x30++0x0F "DCP3"
|
|
line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x30+0x100)++0xB
|
|
line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A"
|
|
line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B"
|
|
line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x40++0x0F "DCP4"
|
|
line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x40+0x100)++0xB
|
|
line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A"
|
|
line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B"
|
|
line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x50++0x0F "DCP5"
|
|
line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x50+0x100)++0xB
|
|
line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A"
|
|
line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B"
|
|
line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x60++0x0F "DCP6"
|
|
line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x60+0x100)++0xB
|
|
line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A"
|
|
line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B"
|
|
line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x70++0x0F "DCP7"
|
|
line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x70+0x100)++0xB
|
|
line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A"
|
|
line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B"
|
|
line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "HTU2"
|
|
base ad:0xFFF7A500
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GC,Global Control Register"
|
|
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
|
|
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
|
|
line.long 0x04 "CPENA,Control Packet Enable Register"
|
|
bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0"
|
|
eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1"
|
|
eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2"
|
|
eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3"
|
|
eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number"
|
|
bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet"
|
|
endif
|
|
newline
|
|
width 16.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register"
|
|
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
|
|
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTMAP,Interrupt Mapping Register"
|
|
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
|
|
bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1"
|
|
bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1"
|
|
bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1"
|
|
bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1"
|
|
bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1"
|
|
bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1"
|
|
bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1"
|
|
bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1"
|
|
bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1"
|
|
bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1"
|
|
bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1"
|
|
newline
|
|
width 10.
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "INTOFF0,Interrupt Offset Register 0"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x0 "INTOFF1,Interrupt Offset Register 1"
|
|
in
|
|
newline
|
|
group.long 0x3C++0x23
|
|
line.long 0x00 "BIM,Buffer Initialization Mode Register"
|
|
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
|
|
bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special"
|
|
bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special"
|
|
bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special"
|
|
newline
|
|
bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special"
|
|
bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special"
|
|
bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special"
|
|
bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special"
|
|
line.long 0x04 "RLOSTFL,Request Lost Flag Register"
|
|
eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
|
|
eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested"
|
|
eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested"
|
|
eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested"
|
|
eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested"
|
|
eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested"
|
|
eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested"
|
|
eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested"
|
|
eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested"
|
|
line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register"
|
|
eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x0C "BERINTFL,BER Interrupt Flag Register"
|
|
eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "MP1S,Memory Protection 1 Start Address"
|
|
line.long 0x14 "MP1E,Memory Protection 1 End Address"
|
|
line.long 0x18 "DCTRL,Debug Control Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
|
|
bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled"
|
|
line.long 0x1C "WPR,Watch Point Register"
|
|
line.long 0x20 "WMR,Watch Mask Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ID,Module Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
|
|
group.long 0x64++0x07
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR,Parity Address Register"
|
|
eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected"
|
|
hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MPCS,Memory Protection Control and Status Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
|
|
line.long 0x04 "MP0S,Memory Protection Start Address Register"
|
|
line.long 0x08 "MP0E,Memory Protection End Address Register"
|
|
sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP"))
|
|
tree "Double Control Packet Configuration Memory"
|
|
base ad:0xFF4C0000
|
|
sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP")
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "IFADDRA,Initial main memory address Control Packet A"
|
|
line.long 0x04 "IFADDRB,Initial main memory address Control Packet B"
|
|
line.long 0x08 "IHADDRCT,Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "ITCOUNT,Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long 0x100++0xB
|
|
line.long 0x00 "CFADDRA,Current main memory address Control Packet A"
|
|
line.long 0x04 "CFADDRB,Current main memory address Control Packet B"
|
|
line.long 0x08 "CFCOUNT,Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
else
|
|
width 15.
|
|
group.long 0x0++0x0F "DCP0"
|
|
line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x0+0x100)++0xB
|
|
line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A"
|
|
line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B"
|
|
line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x10++0x0F "DCP1"
|
|
line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x10+0x100)++0xB
|
|
line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A"
|
|
line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B"
|
|
line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x20++0x0F "DCP2"
|
|
line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x20+0x100)++0xB
|
|
line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A"
|
|
line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B"
|
|
line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x30++0x0F "DCP3"
|
|
line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x30+0x100)++0xB
|
|
line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A"
|
|
line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B"
|
|
line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x40++0x0F "DCP4"
|
|
line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x40+0x100)++0xB
|
|
line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A"
|
|
line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B"
|
|
line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x50++0x0F "DCP5"
|
|
line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x50+0x100)++0xB
|
|
line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A"
|
|
line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B"
|
|
line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x60++0x0F "DCP6"
|
|
line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x60+0x100)++0xB
|
|
line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A"
|
|
line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B"
|
|
line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x70++0x0F "DCP7"
|
|
line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x70+0x100)++0xB
|
|
line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A"
|
|
line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B"
|
|
line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IOMM (I/O Multiplexing and Control Module)"
|
|
base ad:0xFFFFEA00
|
|
width 24.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVISION_REG,Module Revision Register"
|
|
bitfld.long 0x00 30.--31. " REV_SCHEME , Revision scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " REV_MODULE , Module id"
|
|
newline
|
|
bitfld.long 0x00 11.--15. " REV_RTL , RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " REV_MAJOR , Major revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " REV_CUSTOM , Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " REV_MINOR , Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ENDIAN_REG, Device Endianness Register"
|
|
bitfld.long 0x00 0. " ENDIAN , Device endianness" "Little-endian,Big-endian"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DIEID0,Die ID Register 0"
|
|
line.long 0x04 "DIEID1,Die ID Register 1"
|
|
line.long 0x08 "DIEID2,Die ID Register 2"
|
|
line.long 0x0C "DIEID3,Die ID Register 3"
|
|
line.long 0x10 "DEVID0,Device ID Register 0"
|
|
line.long 0x14 "DEVID1,Device ID Register 1"
|
|
endif
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "KICK_REG0,Kicker Register 0"
|
|
line.long 0x04 "KICK_REG1,Kicker Register 1"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "ERR_RAW_STATUS_SET/CLR,Error Raw Status_Set/Clr"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ADDR_ERR , Addressing error status and error signaling enable" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PROT_ERR , Protection error status and error signaling enable" "No error,Error"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "ERR_ENABLE_SET/CLR,Error Enable_Set/Clr"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " ADDR_ERR_EN , Addressing error signaling enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PROT_ERR_EN , Protection error signaling enable" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "ADDRESS_REG,Fault Address Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long.word 0x00 0.--8. 0x01 " FAULT_ADDR , Fault address"
|
|
endif
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "STATUS_REG,Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " ID , Faulting transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MSTID , ID of master that initiated the faulting transaction"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " PRIVID , Faulting privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 7. " FAULT_NS , Fault: Non-secure access detected" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--5. " FAULT_TYPE , Type of fault detected" "No fault,User execute,User write,,User read,,,,Supervisor execute,,,,,,,,Supervisor write,,,,,,,,,,,,,,,,Supervisor read,?..."
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CLEAR_REG,Fault Clear Register"
|
|
bitfld.long 0x00 0. " FAULT_CLEAR , Fault clear" "Not cleared,Cleared"
|
|
if (0.<10.)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PINMMR0,Pin Multiplexing Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR0[31-24] , Pin multiplexing [31-24] register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR0[23-16] , Pin multiplexing [23-16] register 0"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR0[15-8] , Pin multiplexing [15-8] register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR0[7-0] , Pin multiplexing [7-0] register 0"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PINMMR0,Pin Multiplexing Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR0[31-24] , Pin multiplexing [31-24] register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR0[23-16] , Pin multiplexing [23-16] register 0"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR0[15-8] , Pin multiplexing [15-8] register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR0[7-0] , Pin multiplexing [7-0] register 0"
|
|
endif
|
|
if (1.<10.)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PINMMR1,Pin Multiplexing Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR1[31-24] , Pin multiplexing [31-24] register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR1[23-16] , Pin multiplexing [23-16] register 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR1[15-8] , Pin multiplexing [15-8] register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR1[7-0] , Pin multiplexing [7-0] register 1"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PINMMR1,Pin Multiplexing Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR1[31-24] , Pin multiplexing [31-24] register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR1[23-16] , Pin multiplexing [23-16] register 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR1[15-8] , Pin multiplexing [15-8] register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR1[7-0] , Pin multiplexing [7-0] register 1"
|
|
endif
|
|
if (2.<10.)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PINMMR2,Pin Multiplexing Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR2[31-24] , Pin multiplexing [31-24] register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR2[23-16] , Pin multiplexing [23-16] register 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR2[15-8] , Pin multiplexing [15-8] register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR2[7-0] , Pin multiplexing [7-0] register 2"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PINMMR2,Pin Multiplexing Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR2[31-24] , Pin multiplexing [31-24] register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR2[23-16] , Pin multiplexing [23-16] register 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR2[15-8] , Pin multiplexing [15-8] register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR2[7-0] , Pin multiplexing [7-0] register 2"
|
|
endif
|
|
if (3.<10.)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PINMMR3,Pin Multiplexing Control Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR3[31-24] , Pin multiplexing [31-24] register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR3[23-16] , Pin multiplexing [23-16] register 3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR3[15-8] , Pin multiplexing [15-8] register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR3[7-0] , Pin multiplexing [7-0] register 3"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PINMMR3,Pin Multiplexing Control Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR3[31-24] , Pin multiplexing [31-24] register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR3[23-16] , Pin multiplexing [23-16] register 3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR3[15-8] , Pin multiplexing [15-8] register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR3[7-0] , Pin multiplexing [7-0] register 3"
|
|
endif
|
|
if (4.<10.)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PINMMR4,Pin Multiplexing Control Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR4[31-24] , Pin multiplexing [31-24] register 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR4[23-16] , Pin multiplexing [23-16] register 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR4[15-8] , Pin multiplexing [15-8] register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR4[7-0] , Pin multiplexing [7-0] register 4"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PINMMR4,Pin Multiplexing Control Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR4[31-24] , Pin multiplexing [31-24] register 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR4[23-16] , Pin multiplexing [23-16] register 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR4[15-8] , Pin multiplexing [15-8] register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR4[7-0] , Pin multiplexing [7-0] register 4"
|
|
endif
|
|
if (5.<10.)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PINMMR5,Pin Multiplexing Control Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR5[31-24] , Pin multiplexing [31-24] register 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR5[23-16] , Pin multiplexing [23-16] register 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR5[15-8] , Pin multiplexing [15-8] register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR5[7-0] , Pin multiplexing [7-0] register 5"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PINMMR5,Pin Multiplexing Control Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR5[31-24] , Pin multiplexing [31-24] register 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR5[23-16] , Pin multiplexing [23-16] register 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR5[15-8] , Pin multiplexing [15-8] register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR5[7-0] , Pin multiplexing [7-0] register 5"
|
|
endif
|
|
if (6.<10.)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PINMMR6,Pin Multiplexing Control Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR6[31-24] , Pin multiplexing [31-24] register 6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR6[23-16] , Pin multiplexing [23-16] register 6"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR6[15-8] , Pin multiplexing [15-8] register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR6[7-0] , Pin multiplexing [7-0] register 6"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PINMMR6,Pin Multiplexing Control Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR6[31-24] , Pin multiplexing [31-24] register 6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR6[23-16] , Pin multiplexing [23-16] register 6"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR6[15-8] , Pin multiplexing [15-8] register 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR6[7-0] , Pin multiplexing [7-0] register 6"
|
|
endif
|
|
if (7.<10.)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PINMMR7,Pin Multiplexing Control Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR7[31-24] , Pin multiplexing [31-24] register 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR7[23-16] , Pin multiplexing [23-16] register 7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR7[15-8] , Pin multiplexing [15-8] register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR7[7-0] , Pin multiplexing [7-0] register 7"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PINMMR7,Pin Multiplexing Control Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR7[31-24] , Pin multiplexing [31-24] register 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR7[23-16] , Pin multiplexing [23-16] register 7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR7[15-8] , Pin multiplexing [15-8] register 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR7[7-0] , Pin multiplexing [7-0] register 7"
|
|
endif
|
|
if (8.<10.)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PINMMR8,Pin Multiplexing Control Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR8[31-24] , Pin multiplexing [31-24] register 8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR8[23-16] , Pin multiplexing [23-16] register 8"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR8[15-8] , Pin multiplexing [15-8] register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR8[7-0] , Pin multiplexing [7-0] register 8"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PINMMR8,Pin Multiplexing Control Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR8[31-24] , Pin multiplexing [31-24] register 8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR8[23-16] , Pin multiplexing [23-16] register 8"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR8[15-8] , Pin multiplexing [15-8] register 8"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR8[7-0] , Pin multiplexing [7-0] register 8"
|
|
endif
|
|
if (9.<10.)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PINMMR9,Pin Multiplexing Control Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR9[31-24] , Pin multiplexing [31-24] register 9"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR9[23-16] , Pin multiplexing [23-16] register 9"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR9[15-8] , Pin multiplexing [15-8] register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR9[7-0] , Pin multiplexing [7-0] register 9"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PINMMR9,Pin Multiplexing Control Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR9[31-24] , Pin multiplexing [31-24] register 9"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR9[23-16] , Pin multiplexing [23-16] register 9"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR9[15-8] , Pin multiplexing [15-8] register 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR9[7-0] , Pin multiplexing [7-0] register 9"
|
|
endif
|
|
if (10.<10.)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PINMMR10,Pin Multiplexing Control Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR10[31-24] , Pin multiplexing [31-24] register 10"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR10[23-16] , Pin multiplexing [23-16] register 10"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR10[15-8] , Pin multiplexing [15-8] register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR10[7-0] , Pin multiplexing [7-0] register 10"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PINMMR10,Pin Multiplexing Control Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR10[31-24] , Pin multiplexing [31-24] register 10"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR10[23-16] , Pin multiplexing [23-16] register 10"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR10[15-8] , Pin multiplexing [15-8] register 10"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR10[7-0] , Pin multiplexing [7-0] register 10"
|
|
endif
|
|
if (11.<10.)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PINMMR11,Pin Multiplexing Control Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR11[31-24] , Pin multiplexing [31-24] register 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR11[23-16] , Pin multiplexing [23-16] register 11"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR11[15-8] , Pin multiplexing [15-8] register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR11[7-0] , Pin multiplexing [7-0] register 11"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PINMMR11,Pin Multiplexing Control Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR11[31-24] , Pin multiplexing [31-24] register 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR11[23-16] , Pin multiplexing [23-16] register 11"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR11[15-8] , Pin multiplexing [15-8] register 11"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR11[7-0] , Pin multiplexing [7-0] register 11"
|
|
endif
|
|
if (12.<10.)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PINMMR12,Pin Multiplexing Control Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR12[31-24] , Pin multiplexing [31-24] register 12"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR12[23-16] , Pin multiplexing [23-16] register 12"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR12[15-8] , Pin multiplexing [15-8] register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR12[7-0] , Pin multiplexing [7-0] register 12"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PINMMR12,Pin Multiplexing Control Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR12[31-24] , Pin multiplexing [31-24] register 12"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR12[23-16] , Pin multiplexing [23-16] register 12"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR12[15-8] , Pin multiplexing [15-8] register 12"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR12[7-0] , Pin multiplexing [7-0] register 12"
|
|
endif
|
|
if (13.<10.)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "PINMMR13,Pin Multiplexing Control Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR13[31-24] , Pin multiplexing [31-24] register 13"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR13[23-16] , Pin multiplexing [23-16] register 13"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR13[15-8] , Pin multiplexing [15-8] register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR13[7-0] , Pin multiplexing [7-0] register 13"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "PINMMR13,Pin Multiplexing Control Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR13[31-24] , Pin multiplexing [31-24] register 13"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR13[23-16] , Pin multiplexing [23-16] register 13"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR13[15-8] , Pin multiplexing [15-8] register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR13[7-0] , Pin multiplexing [7-0] register 13"
|
|
endif
|
|
if (14.<10.)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "PINMMR14,Pin Multiplexing Control Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR14[31-24] , Pin multiplexing [31-24] register 14"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR14[23-16] , Pin multiplexing [23-16] register 14"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR14[15-8] , Pin multiplexing [15-8] register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR14[7-0] , Pin multiplexing [7-0] register 14"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "PINMMR14,Pin Multiplexing Control Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR14[31-24] , Pin multiplexing [31-24] register 14"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR14[23-16] , Pin multiplexing [23-16] register 14"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR14[15-8] , Pin multiplexing [15-8] register 14"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR14[7-0] , Pin multiplexing [7-0] register 14"
|
|
endif
|
|
if (15.<10.)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "PINMMR15,Pin Multiplexing Control Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR15[31-24] , Pin multiplexing [31-24] register 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR15[23-16] , Pin multiplexing [23-16] register 15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR15[15-8] , Pin multiplexing [15-8] register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR15[7-0] , Pin multiplexing [7-0] register 15"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "PINMMR15,Pin Multiplexing Control Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR15[31-24] , Pin multiplexing [31-24] register 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR15[23-16] , Pin multiplexing [23-16] register 15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR15[15-8] , Pin multiplexing [15-8] register 15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR15[7-0] , Pin multiplexing [7-0] register 15"
|
|
endif
|
|
if (16.<10.)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PINMMR16,Pin Multiplexing Control Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR16[31-24] , Pin multiplexing [31-24] register 16"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR16[23-16] , Pin multiplexing [23-16] register 16"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR16[15-8] , Pin multiplexing [15-8] register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR16[7-0] , Pin multiplexing [7-0] register 16"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PINMMR16,Pin Multiplexing Control Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR16[31-24] , Pin multiplexing [31-24] register 16"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR16[23-16] , Pin multiplexing [23-16] register 16"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR16[15-8] , Pin multiplexing [15-8] register 16"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR16[7-0] , Pin multiplexing [7-0] register 16"
|
|
endif
|
|
if (17.<10.)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PINMMR17,Pin Multiplexing Control Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR17[31-24] , Pin multiplexing [31-24] register 17"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR17[23-16] , Pin multiplexing [23-16] register 17"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR17[15-8] , Pin multiplexing [15-8] register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR17[7-0] , Pin multiplexing [7-0] register 17"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PINMMR17,Pin Multiplexing Control Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR17[31-24] , Pin multiplexing [31-24] register 17"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR17[23-16] , Pin multiplexing [23-16] register 17"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR17[15-8] , Pin multiplexing [15-8] register 17"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR17[7-0] , Pin multiplexing [7-0] register 17"
|
|
endif
|
|
if (18.<10.)
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "PINMMR18,Pin Multiplexing Control Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR18[31-24] , Pin multiplexing [31-24] register 18"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR18[23-16] , Pin multiplexing [23-16] register 18"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR18[15-8] , Pin multiplexing [15-8] register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR18[7-0] , Pin multiplexing [7-0] register 18"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "PINMMR18,Pin Multiplexing Control Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR18[31-24] , Pin multiplexing [31-24] register 18"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR18[23-16] , Pin multiplexing [23-16] register 18"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR18[15-8] , Pin multiplexing [15-8] register 18"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR18[7-0] , Pin multiplexing [7-0] register 18"
|
|
endif
|
|
if (19.<10.)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PINMMR19,Pin Multiplexing Control Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR19[31-24] , Pin multiplexing [31-24] register 19"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR19[23-16] , Pin multiplexing [23-16] register 19"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR19[15-8] , Pin multiplexing [15-8] register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR19[7-0] , Pin multiplexing [7-0] register 19"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PINMMR19,Pin Multiplexing Control Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR19[31-24] , Pin multiplexing [31-24] register 19"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR19[23-16] , Pin multiplexing [23-16] register 19"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR19[15-8] , Pin multiplexing [15-8] register 19"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR19[7-0] , Pin multiplexing [7-0] register 19"
|
|
endif
|
|
if (20.<10.)
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "PINMMR20,Pin Multiplexing Control Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR20[31-24] , Pin multiplexing [31-24] register 20"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR20[23-16] , Pin multiplexing [23-16] register 20"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR20[15-8] , Pin multiplexing [15-8] register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR20[7-0] , Pin multiplexing [7-0] register 20"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "PINMMR20,Pin Multiplexing Control Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR20[31-24] , Pin multiplexing [31-24] register 20"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR20[23-16] , Pin multiplexing [23-16] register 20"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR20[15-8] , Pin multiplexing [15-8] register 20"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR20[7-0] , Pin multiplexing [7-0] register 20"
|
|
endif
|
|
if (21.<10.)
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "PINMMR21,Pin Multiplexing Control Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR21[31-24] , Pin multiplexing [31-24] register 21"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR21[23-16] , Pin multiplexing [23-16] register 21"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR21[15-8] , Pin multiplexing [15-8] register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR21[7-0] , Pin multiplexing [7-0] register 21"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "PINMMR21,Pin Multiplexing Control Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR21[31-24] , Pin multiplexing [31-24] register 21"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR21[23-16] , Pin multiplexing [23-16] register 21"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR21[15-8] , Pin multiplexing [15-8] register 21"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR21[7-0] , Pin multiplexing [7-0] register 21"
|
|
endif
|
|
if (22.<10.)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PINMMR22,Pin Multiplexing Control Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR22[31-24] , Pin multiplexing [31-24] register 22"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR22[23-16] , Pin multiplexing [23-16] register 22"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR22[15-8] , Pin multiplexing [15-8] register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR22[7-0] , Pin multiplexing [7-0] register 22"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PINMMR22,Pin Multiplexing Control Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR22[31-24] , Pin multiplexing [31-24] register 22"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR22[23-16] , Pin multiplexing [23-16] register 22"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR22[15-8] , Pin multiplexing [15-8] register 22"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR22[7-0] , Pin multiplexing [7-0] register 22"
|
|
endif
|
|
if (23.<10.)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "PINMMR23,Pin Multiplexing Control Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR23[31-24] , Pin multiplexing [31-24] register 23"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR23[23-16] , Pin multiplexing [23-16] register 23"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR23[15-8] , Pin multiplexing [15-8] register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR23[7-0] , Pin multiplexing [7-0] register 23"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "PINMMR23,Pin Multiplexing Control Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR23[31-24] , Pin multiplexing [31-24] register 23"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR23[23-16] , Pin multiplexing [23-16] register 23"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR23[15-8] , Pin multiplexing [15-8] register 23"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR23[7-0] , Pin multiplexing [7-0] register 23"
|
|
endif
|
|
if (24.<10.)
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "PINMMR24,Pin Multiplexing Control Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR24[31-24] , Pin multiplexing [31-24] register 24"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR24[23-16] , Pin multiplexing [23-16] register 24"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR24[15-8] , Pin multiplexing [15-8] register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR24[7-0] , Pin multiplexing [7-0] register 24"
|
|
else
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "PINMMR24,Pin Multiplexing Control Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR24[31-24] , Pin multiplexing [31-24] register 24"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR24[23-16] , Pin multiplexing [23-16] register 24"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR24[15-8] , Pin multiplexing [15-8] register 24"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR24[7-0] , Pin multiplexing [7-0] register 24"
|
|
endif
|
|
if (25.<10.)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "PINMMR25,Pin Multiplexing Control Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR25[31-24] , Pin multiplexing [31-24] register 25"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR25[23-16] , Pin multiplexing [23-16] register 25"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR25[15-8] , Pin multiplexing [15-8] register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR25[7-0] , Pin multiplexing [7-0] register 25"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "PINMMR25,Pin Multiplexing Control Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR25[31-24] , Pin multiplexing [31-24] register 25"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR25[23-16] , Pin multiplexing [23-16] register 25"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR25[15-8] , Pin multiplexing [15-8] register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR25[7-0] , Pin multiplexing [7-0] register 25"
|
|
endif
|
|
if (26.<10.)
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "PINMMR26,Pin Multiplexing Control Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR26[31-24] , Pin multiplexing [31-24] register 26"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR26[23-16] , Pin multiplexing [23-16] register 26"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR26[15-8] , Pin multiplexing [15-8] register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR26[7-0] , Pin multiplexing [7-0] register 26"
|
|
else
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "PINMMR26,Pin Multiplexing Control Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR26[31-24] , Pin multiplexing [31-24] register 26"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR26[23-16] , Pin multiplexing [23-16] register 26"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR26[15-8] , Pin multiplexing [15-8] register 26"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR26[7-0] , Pin multiplexing [7-0] register 26"
|
|
endif
|
|
if (27.<10.)
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PINMMR27,Pin Multiplexing Control Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR27[31-24] , Pin multiplexing [31-24] register 27"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR27[23-16] , Pin multiplexing [23-16] register 27"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR27[15-8] , Pin multiplexing [15-8] register 27"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR27[7-0] , Pin multiplexing [7-0] register 27"
|
|
else
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PINMMR27,Pin Multiplexing Control Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR27[31-24] , Pin multiplexing [31-24] register 27"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR27[23-16] , Pin multiplexing [23-16] register 27"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR27[15-8] , Pin multiplexing [15-8] register 27"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR27[7-0] , Pin multiplexing [7-0] register 27"
|
|
endif
|
|
if (28.<10.)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "PINMMR28,Pin Multiplexing Control Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR28[31-24] , Pin multiplexing [31-24] register 28"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR28[23-16] , Pin multiplexing [23-16] register 28"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR28[15-8] , Pin multiplexing [15-8] register 28"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR28[7-0] , Pin multiplexing [7-0] register 28"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "PINMMR28,Pin Multiplexing Control Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR28[31-24] , Pin multiplexing [31-24] register 28"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR28[23-16] , Pin multiplexing [23-16] register 28"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR28[15-8] , Pin multiplexing [15-8] register 28"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR28[7-0] , Pin multiplexing [7-0] register 28"
|
|
endif
|
|
if (29.<10.)
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PINMMR29,Pin Multiplexing Control Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR29[31-24] , Pin multiplexing [31-24] register 29"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR29[23-16] , Pin multiplexing [23-16] register 29"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR29[15-8] , Pin multiplexing [15-8] register 29"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR29[7-0] , Pin multiplexing [7-0] register 29"
|
|
else
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PINMMR29,Pin Multiplexing Control Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR29[31-24] , Pin multiplexing [31-24] register 29"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR29[23-16] , Pin multiplexing [23-16] register 29"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR29[15-8] , Pin multiplexing [15-8] register 29"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR29[7-0] , Pin multiplexing [7-0] register 29"
|
|
endif
|
|
if (30.<10.)
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PINMMR30,Pin Multiplexing Control Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR30[31-24] , Pin multiplexing [31-24] register 30"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR30[23-16] , Pin multiplexing [23-16] register 30"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR30[15-8] , Pin multiplexing [15-8] register 30"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR30[7-0] , Pin multiplexing [7-0] register 30"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PINMMR30,Pin Multiplexing Control Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PINMMR30[31-24] , Pin multiplexing [31-24] register 30"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PINMMR30[23-16] , Pin multiplexing [23-16] register 30"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " PINMMR30[15-8] , Pin multiplexing [15-8] register 30"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PINMMR30[7-0] , Pin multiplexing [7-0] register 30"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
tree "MIBSPI1"
|
|
base ad:0xFFF7F400
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register 0"
|
|
bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset"
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x03)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x02)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
width 5.
|
|
tree "SPI Pin Control Registers"
|
|
tree "SPI Pin Control Registers 0-5"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PC0,Pin Control Register 0"
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PC1,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output"
|
|
bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output"
|
|
bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output"
|
|
bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output"
|
|
bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output"
|
|
bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output"
|
|
bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output"
|
|
bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output"
|
|
bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output"
|
|
bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PC2,Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High"
|
|
bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High"
|
|
bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High"
|
|
bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High"
|
|
bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High"
|
|
bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High"
|
|
bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High"
|
|
bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High"
|
|
bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High"
|
|
bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High"
|
|
bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High"
|
|
bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High"
|
|
bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High"
|
|
bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High"
|
|
bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High"
|
|
bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High"
|
|
width 5.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PC3,Pin Control Register 3"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High"
|
|
tree.end
|
|
width 5.
|
|
tree "SPI Pin Control Registers 6-8"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PC6,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PC7,Pin Control Register 7"
|
|
bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PC8,Pin Control Register 8"
|
|
bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x01000000)==0x01000000)
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active"
|
|
bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
endif
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "BUF,Receive Buffer Register"
|
|
in
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "DELAY,Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "DELAY,Delay Register"
|
|
endif
|
|
width 7.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEF,Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High"
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High"
|
|
width 6.
|
|
tree "SPI Data Format Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "FMT0,Data Format Register 0"
|
|
bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FMT1,Data Format Register 1"
|
|
bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "FMT2,Data Format Register 2"
|
|
bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMT3,Data Format Register 3"
|
|
bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
tree.end
|
|
width 12.
|
|
tree "SPI Interrupt Vector Registers"
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT")))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SRSEL,Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow"
|
|
bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow"
|
|
bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow"
|
|
bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow"
|
|
bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow"
|
|
bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow"
|
|
bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow"
|
|
bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow"
|
|
bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow"
|
|
bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow"
|
|
bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow"
|
|
bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow"
|
|
bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow"
|
|
bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x00)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x01000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x02000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
else
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
endif
|
|
width 11.
|
|
tree "MibSPI Registers"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W"
|
|
bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled"
|
|
width 11.
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1"
|
|
width 11.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
width 11.
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer"
|
|
else
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "TICKCNT,Tick Count Register"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
endif
|
|
width 9.
|
|
tree "MibSPI Transfer Group Control Registers"
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
else
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer"
|
|
endif
|
|
else
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x108++0x3
|
|
hide.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x10C++0x3
|
|
hide.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01)
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
in
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
hgroup.long 0x120++0x3
|
|
hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
if ((((d.l((ad:0xFFF7F400+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7F400+0x0134)))&0x02)==0x02))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive"
|
|
elif ((((data.long((ad:0xFFF7F400+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7F400+0x0134)))&0x02)==0x00))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
else
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Spi2"
|
|
base ad:0xFFF7F600
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register 0"
|
|
bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset"
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x03)==0x03)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F600+0x04)))&0x03)==0x02)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F600+0x04)))&0x03)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x01)==0x01)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x01)==0x01)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x01)==0x01)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
width 5.
|
|
tree "SPI Pin Control Registers"
|
|
tree "SPI Pin Control Registers 0-5"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PC0,Pin Control Register 0"
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PC1,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output"
|
|
bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output"
|
|
bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output"
|
|
bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output"
|
|
bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output"
|
|
bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output"
|
|
bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output"
|
|
bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output"
|
|
bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output"
|
|
bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PC2,Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High"
|
|
bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High"
|
|
bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High"
|
|
bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High"
|
|
bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High"
|
|
bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High"
|
|
bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High"
|
|
bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High"
|
|
bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High"
|
|
bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High"
|
|
bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High"
|
|
bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High"
|
|
bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High"
|
|
bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High"
|
|
bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High"
|
|
bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High"
|
|
width 5.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PC3,Pin Control Register 3"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High"
|
|
tree.end
|
|
width 5.
|
|
tree "SPI Pin Control Registers 6-8"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PC6,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PC7,Pin Control Register 7"
|
|
bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PC8,Pin Control Register 8"
|
|
bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x01000000)==0x01000000)
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x04)))&0x01)==0x01)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active"
|
|
bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
endif
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "BUF,Receive Buffer Register"
|
|
in
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "DELAY,Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "DELAY,Delay Register"
|
|
endif
|
|
width 7.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEF,Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High"
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High"
|
|
width 6.
|
|
tree "SPI Data Format Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "FMT0,Data Format Register 0"
|
|
bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FMT1,Data Format Register 1"
|
|
bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "FMT2,Data Format Register 2"
|
|
bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMT3,Data Format Register 3"
|
|
bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
tree.end
|
|
width 12.
|
|
tree "SPI Interrupt Vector Registers"
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT")))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SRSEL,Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow"
|
|
bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow"
|
|
bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow"
|
|
bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow"
|
|
bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow"
|
|
bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow"
|
|
bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow"
|
|
bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow"
|
|
bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow"
|
|
bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow"
|
|
bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow"
|
|
bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow"
|
|
bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow"
|
|
bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x3c)))&0x03000000)==0x00)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F600+0x3c)))&0x03000000)==0x01000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F600+0x3c)))&0x03000000)==0x02000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
else
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
endif
|
|
width 11.
|
|
tree "MibSPI Registers"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W"
|
|
bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled"
|
|
width 11.
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1"
|
|
width 11.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
width 11.
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer"
|
|
else
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "TICKCNT,Tick Count Register"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
endif
|
|
width 9.
|
|
tree "MibSPI Transfer Group Control Registers"
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
else
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer"
|
|
endif
|
|
else
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F600+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F600+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x108++0x3
|
|
hide.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x10C++0x3
|
|
hide.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F600+0x70)))&0x01)==0x01)
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
in
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
hgroup.long 0x120++0x3
|
|
hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
if ((((d.l((ad:0xFFF7F600+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7F600+0x0134)))&0x02)==0x02))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive"
|
|
elif ((((data.long((ad:0xFFF7F600+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7F600+0x0134)))&0x02)==0x00))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
else
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "MibSpi3"
|
|
base ad:0xFFF7F800
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register 0"
|
|
bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset"
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x03)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x02)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
width 5.
|
|
tree "SPI Pin Control Registers"
|
|
tree "SPI Pin Control Registers 0-5"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PC0,Pin Control Register 0"
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PC1,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output"
|
|
bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output"
|
|
bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output"
|
|
bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output"
|
|
bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output"
|
|
bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output"
|
|
bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output"
|
|
bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output"
|
|
bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output"
|
|
bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PC2,Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High"
|
|
bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High"
|
|
bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High"
|
|
bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High"
|
|
bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High"
|
|
bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High"
|
|
bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High"
|
|
bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High"
|
|
bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High"
|
|
bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High"
|
|
bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High"
|
|
bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High"
|
|
bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High"
|
|
bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High"
|
|
bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High"
|
|
bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High"
|
|
width 5.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PC3,Pin Control Register 3"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High"
|
|
tree.end
|
|
width 5.
|
|
tree "SPI Pin Control Registers 6-8"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PC6,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PC7,Pin Control Register 7"
|
|
bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PC8,Pin Control Register 8"
|
|
bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x01000000)==0x01000000)
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active"
|
|
bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
endif
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "BUF,Receive Buffer Register"
|
|
in
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "DELAY,Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "DELAY,Delay Register"
|
|
endif
|
|
width 7.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEF,Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High"
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High"
|
|
width 6.
|
|
tree "SPI Data Format Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "FMT0,Data Format Register 0"
|
|
bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FMT1,Data Format Register 1"
|
|
bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "FMT2,Data Format Register 2"
|
|
bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMT3,Data Format Register 3"
|
|
bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
tree.end
|
|
width 12.
|
|
tree "SPI Interrupt Vector Registers"
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT")))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SRSEL,Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow"
|
|
bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow"
|
|
bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow"
|
|
bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow"
|
|
bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow"
|
|
bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow"
|
|
bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow"
|
|
bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow"
|
|
bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow"
|
|
bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow"
|
|
bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow"
|
|
bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow"
|
|
bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow"
|
|
bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x00)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x01000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x02000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
else
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
endif
|
|
width 11.
|
|
tree "MibSPI Registers"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W"
|
|
bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled"
|
|
width 11.
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1"
|
|
width 11.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
width 11.
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer"
|
|
else
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "TICKCNT,Tick Count Register"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
endif
|
|
width 9.
|
|
tree "MibSPI Transfer Group Control Registers"
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
else
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer"
|
|
endif
|
|
else
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x108++0x3
|
|
hide.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x10C++0x3
|
|
hide.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
endif
|
|
if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01)
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
in
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
hgroup.long 0x120++0x3
|
|
hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
if ((((d.l((ad:0xFFF7F800+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7F800+0x0134)))&0x02)==0x02))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive"
|
|
elif ((((data.long((ad:0xFFF7F800+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7F800+0x0134)))&0x02)==0x00))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
else
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Spi4"
|
|
base ad:0xFFF7FA00
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register 0"
|
|
bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset"
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x03)==0x03)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7FA00+0x04)))&0x03)==0x02)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7FA00+0x04)))&0x03)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x01)==0x01)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x01)==0x01)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x01)==0x01)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
width 5.
|
|
tree "SPI Pin Control Registers"
|
|
tree "SPI Pin Control Registers 0-5"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PC0,Pin Control Register 0"
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PC1,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output"
|
|
bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output"
|
|
bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output"
|
|
bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output"
|
|
bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output"
|
|
bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output"
|
|
bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output"
|
|
bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output"
|
|
bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output"
|
|
bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PC2,Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High"
|
|
bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High"
|
|
bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High"
|
|
bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High"
|
|
bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High"
|
|
bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High"
|
|
bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High"
|
|
bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High"
|
|
bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High"
|
|
bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High"
|
|
bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High"
|
|
bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High"
|
|
bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High"
|
|
bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High"
|
|
bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High"
|
|
bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High"
|
|
width 5.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PC3,Pin Control Register 3"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High"
|
|
tree.end
|
|
width 5.
|
|
tree "SPI Pin Control Registers 6-8"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PC6,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PC7,Pin Control Register 7"
|
|
bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PC8,Pin Control Register 8"
|
|
bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x01000000)==0x01000000)
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x04)))&0x01)==0x01)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active"
|
|
bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
endif
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "BUF,Receive Buffer Register"
|
|
in
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "DELAY,Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "DELAY,Delay Register"
|
|
endif
|
|
width 7.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEF,Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High"
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High"
|
|
width 6.
|
|
tree "SPI Data Format Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "FMT0,Data Format Register 0"
|
|
bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FMT1,Data Format Register 1"
|
|
bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "FMT2,Data Format Register 2"
|
|
bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMT3,Data Format Register 3"
|
|
bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
tree.end
|
|
width 12.
|
|
tree "SPI Interrupt Vector Registers"
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT")))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SRSEL,Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow"
|
|
bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow"
|
|
bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow"
|
|
bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow"
|
|
bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow"
|
|
bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow"
|
|
bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow"
|
|
bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow"
|
|
bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow"
|
|
bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow"
|
|
bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow"
|
|
bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow"
|
|
bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow"
|
|
bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x3c)))&0x03000000)==0x00)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7FA00+0x3c)))&0x03000000)==0x01000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7FA00+0x3c)))&0x03000000)==0x02000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
else
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
endif
|
|
width 11.
|
|
tree "MibSPI Registers"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W"
|
|
bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled"
|
|
width 11.
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1"
|
|
width 11.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
width 11.
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer"
|
|
else
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "TICKCNT,Tick Count Register"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
endif
|
|
width 9.
|
|
tree "MibSPI Transfer Group Control Registers"
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
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|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
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|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
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|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
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|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
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|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
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|
group.long 0xA4++0x3
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|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
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|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
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|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
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|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
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|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
else
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
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group.long 0x9C++0x3
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|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
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|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
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bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
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|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
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group.long 0xA0++0x3
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line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
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|
textline " "
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|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
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hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
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group.long 0xA4++0x3
|
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line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
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bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer"
|
|
endif
|
|
else
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FA00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FA00+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x108++0x3
|
|
hide.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x10C++0x3
|
|
hide.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FA00+0x70)))&0x01)==0x01)
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
in
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
hgroup.long 0x120++0x3
|
|
hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
if ((((d.l((ad:0xFFF7FA00+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7FA00+0x0134)))&0x02)==0x02))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive"
|
|
elif ((((data.long((ad:0xFFF7FA00+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7FA00+0x0134)))&0x02)==0x00))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
else
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "MIBSPIP5"
|
|
base ad:0xFFF7FC00
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register 0"
|
|
bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset"
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x03)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x02)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
elif (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "INT0,Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "LVL,Interrupt Level Register"
|
|
bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
else
|
|
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1"
|
|
bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1"
|
|
endif
|
|
width 6.
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLG,Flag Register"
|
|
bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full"
|
|
eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
width 5.
|
|
tree "SPI Pin Control Registers"
|
|
tree "SPI Pin Control Registers 0-5"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PC0,Pin Control Register 0"
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PC1,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output"
|
|
bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output"
|
|
bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output"
|
|
bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output"
|
|
bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output"
|
|
bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output"
|
|
bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output"
|
|
bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output"
|
|
bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output"
|
|
bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PC2,Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High"
|
|
bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High"
|
|
bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High"
|
|
bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High"
|
|
bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High"
|
|
bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High"
|
|
bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High"
|
|
bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High"
|
|
bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High"
|
|
bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High"
|
|
bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High"
|
|
bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High"
|
|
bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High"
|
|
bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High"
|
|
bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High"
|
|
bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High"
|
|
width 5.
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PC3,Pin Control Register 3"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High"
|
|
tree.end
|
|
width 5.
|
|
tree "SPI Pin Control Registers 6-8"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PC6,Pin Control Register 1"
|
|
bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated"
|
|
bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated"
|
|
bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PC7,Pin Control Register 7"
|
|
bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PC8,Pin Control Register 8"
|
|
bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x01000000)==0x01000000)
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DAT0,Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active"
|
|
bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data"
|
|
endif
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x0 "BUF,Receive Buffer Register"
|
|
in
|
|
width 7.
|
|
if (((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "EMU,Emulation Register"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE"))
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error"
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "DELAY,Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "DELAY,Delay Register"
|
|
endif
|
|
width 7.
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEF,Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High"
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High"
|
|
width 6.
|
|
tree "SPI Data Format Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "FMT0,Data Format Register 0"
|
|
bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FMT1,Data Format Register 1"
|
|
bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "FMT2,Data Format Register 2"
|
|
bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMT3,Data Format Register 3"
|
|
bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait"
|
|
bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB"
|
|
bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive"
|
|
bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
tree.end
|
|
width 12.
|
|
tree "SPI Interrupt Vector Registers"
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0"
|
|
bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..."
|
|
bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished"
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..."
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT")))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SRSEL,Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow"
|
|
bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow"
|
|
bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow"
|
|
bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow"
|
|
bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow"
|
|
bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow"
|
|
bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow"
|
|
bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow"
|
|
bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow"
|
|
bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow"
|
|
bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow"
|
|
bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow"
|
|
bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow"
|
|
bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow"
|
|
bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow"
|
|
bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x00)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x01000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
elif (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x02000000)
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
else
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..."
|
|
sif (cpu()=="TMS570PSFC61")
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..."
|
|
else
|
|
bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data"
|
|
endif
|
|
endif
|
|
width 11.
|
|
tree "MibSPI Registers"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W"
|
|
bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled"
|
|
width 11.
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1"
|
|
width 11.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")
|
|
eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt"
|
|
width 11.
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..."
|
|
endif
|
|
hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer"
|
|
else
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "TICKCNT,Tick Count Register"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer"
|
|
endif
|
|
width 9.
|
|
tree "MibSPI Transfer Group Control Registers"
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
else
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB4++0x3
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..."
|
|
bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer"
|
|
endif
|
|
else
|
|
sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1)
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers"
|
|
bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers"
|
|
else
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DMA0COUNT,ICOUNT Register 0"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DMA1COUNT,ICOUNT Register 1"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DMA2COUNT,ICOUNT Register 2"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DMA3COUNT,ICOUNT Register 3"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x108++0x3
|
|
hide.long 0x00 "DMA4COUNT,ICOUNT Register 4"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x10C++0x3
|
|
hide.long 0x00 "DMA5COUNT,ICOUNT Register 5"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x00 "DMA6COUNT,ICOUNT Register 6"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x00 "DMA7COUNT,ICOUNT Register 7"
|
|
endif
|
|
if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01)
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
in
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register"
|
|
hgroup.long 0x120++0x3
|
|
hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
hgroup.long 0x128++0x3
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x12c++0x3
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
hgroup.long 0x130++0x3
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
if ((((d.l((ad:0xFFF7FC00+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7FC00+0x0134)))&0x02)==0x02))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive"
|
|
elif ((((data.long((ad:0xFFF7FC00+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7FC00+0x0134)))&0x02)==0x00))
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1"
|
|
bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog"
|
|
else
|
|
group.long 0x134++0x3
|
|
line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "SCI (Serial Communication Interface)"
|
|
tree "LIN1"
|
|
base ad:0xFFF7E400
|
|
width 8.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x44)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
endif
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x40)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif (((d.l((ad:0xFFF7E400+0x4)))&0x44)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
endif
|
|
width 11.
|
|
tree "SCI Interrupt Registers"
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled"
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received"
|
|
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready"
|
|
eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout"
|
|
eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
endif
|
|
width 9.
|
|
tree "SCI Interrupt Vector Offset Registers"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "INVECT0,Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "INVECT1,Interrupt Vector Offset 1"
|
|
in
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
elif (((d.l(ad:0xFFF7E400+0x4)&0x40)==0x0)&&(((d.l((ad:0xFFF7E400+0x04)))&0x0400)==0x0400))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRSR,Baud Rate Selection Register"
|
|
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection"
|
|
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
width 4.
|
|
tree "SCI Data Buffer Registers"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "ED,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "RD,SCI Data Buffer"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "TD,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree.end
|
|
tree "SCI Pin I/O Control Registers"
|
|
width 6.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..."
|
|
endif
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK"
|
|
endif
|
|
endif
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357")
|
|
if ((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x20))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x0))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input"
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "PIO2,Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High"
|
|
endif
|
|
width 6.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIO3,Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High"
|
|
endif
|
|
sif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PIO4,Pin I/O Control Register 4"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PIO5,Pin I/O Control Register 5"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
width 6.
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "PIO6,Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIO7,Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&cpu()!=("TMS570LS1114*")&&cpu()!=("TMS570LS1115*")&&cpu()!=("TMS570LS1224*")&&cpu()!=("TMS570LS1225*")&&cpu()!=("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes"
|
|
endif
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "PIO8,Pin I/O Control Register 8"
|
|
bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up"
|
|
endif
|
|
tree.end
|
|
tree "BLIN Registers"
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits"
|
|
bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
endif
|
|
sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "LINRD0,LINRD0 Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x0 "LINRD1,LINRD1 Register"
|
|
in
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "LINRD0,LINRD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD0 ,Receive Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD1 ,Receive Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD2 ,Receive Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD3 ,Receive Buffer 3"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "LINRD1,LINRD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD4 ,Receive Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD5 , Receive Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD6 ,Receive Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD7 ,Receive Buffer 7"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LINMASK,LINMASK Register"
|
|
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked"
|
|
else
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x0 "LINMASK,LINMASK Register"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "LINID,LINID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte"
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "LINID,LINID Register"
|
|
endif
|
|
width 9.
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "LINTD0,LINTD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "LINTD1,LINTD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7"
|
|
tree.end
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler"
|
|
else
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
endif
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&(cpu()!="TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PIO9,Pin I/O Control Register 9"
|
|
bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew"
|
|
bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew"
|
|
sif (cpu()!="TMS570PSFC61")
|
|
bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew"
|
|
endif
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "LIN2"
|
|
base ad:0xFFF7E500
|
|
width 8.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x44)==0x44)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
endif
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif ((d.l(ad:0xFFF7E500+0x4)&0x44)==0x40)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif (((d.l((ad:0xFFF7E500+0x4)))&0x44)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
endif
|
|
width 11.
|
|
tree "SCI Interrupt Registers"
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled"
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received"
|
|
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready"
|
|
eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout"
|
|
eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
endif
|
|
width 9.
|
|
tree "SCI Interrupt Vector Offset Registers"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "INVECT0,Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "INVECT1,Interrupt Vector Offset 1"
|
|
in
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
elif (((d.l(ad:0xFFF7E500+0x4)&0x40)==0x0)&&(((d.l((ad:0xFFF7E500+0x04)))&0x0400)==0x0400))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRSR,Baud Rate Selection Register"
|
|
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection"
|
|
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
width 4.
|
|
tree "SCI Data Buffer Registers"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "ED,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "RD,SCI Data Buffer"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "TD,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree.end
|
|
tree "SCI Pin I/O Control Registers"
|
|
width 6.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..."
|
|
endif
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK"
|
|
endif
|
|
endif
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357")
|
|
if ((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E500+0x4)&0x60)==0x20))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E500+0x4)&0x60)==0x0))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input"
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "PIO2,Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High"
|
|
endif
|
|
width 6.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIO3,Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High"
|
|
endif
|
|
sif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PIO4,Pin I/O Control Register 4"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PIO5,Pin I/O Control Register 5"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
width 6.
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "PIO6,Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIO7,Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&cpu()!=("TMS570LS1114*")&&cpu()!=("TMS570LS1115*")&&cpu()!=("TMS570LS1224*")&&cpu()!=("TMS570LS1225*")&&cpu()!=("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes"
|
|
endif
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "PIO8,Pin I/O Control Register 8"
|
|
bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up"
|
|
endif
|
|
tree.end
|
|
tree "BLIN Registers"
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits"
|
|
bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
endif
|
|
sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "LINRD0,LINRD0 Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x0 "LINRD1,LINRD1 Register"
|
|
in
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "LINRD0,LINRD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD0 ,Receive Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD1 ,Receive Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD2 ,Receive Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD3 ,Receive Buffer 3"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "LINRD1,LINRD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD4 ,Receive Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD5 , Receive Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD6 ,Receive Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD7 ,Receive Buffer 7"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LINMASK,LINMASK Register"
|
|
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked"
|
|
else
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x0 "LINMASK,LINMASK Register"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "LINID,LINID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte"
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "LINID,LINID Register"
|
|
endif
|
|
width 9.
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "LINTD0,LINTD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "LINTD1,LINTD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7"
|
|
tree.end
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler"
|
|
else
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
endif
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&(cpu()!="TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PIO9,Pin I/O Control Register 9"
|
|
bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew"
|
|
bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew"
|
|
sif (cpu()!="TMS570PSFC61")
|
|
bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew"
|
|
endif
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40)
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "CCMR4 (CPU Compare Module - CortexR4)"
|
|
base ad:0xFFFFF600
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CCMSR,CCM-R4F Status Register"
|
|
eventfld.long 0x00 16. " CMPE ,Compare error" "No error,Error"
|
|
bitfld.long 0x00 8. " STC ,Self-test complete" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " STET ,Self test error type" "Compare match,Compare mismatch"
|
|
bitfld.long 0x00 0. " STE ,Self-test error" "No error,Error"
|
|
line.long 0x04 "CCMKEYR,CCM-R4F Key Register"
|
|
bitfld.long 0x04 0.--3. " MKEY ,Mode key" "Lockstep,,,,,,Self-test,,,Error Forcing,,,,,,Self-test error forcing"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Controller)"
|
|
base ad:0xFE000000
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTRL0,CRC Global Control Register 0"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 24. " CH4_PSA_SWREST ,Channel 4 PSA software reset" "No reset,Reset"
|
|
bitfld.long 0x00 16. " CH3_PSA_SWREST ,Channel 3 psa software reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_CTRL1,CRC Global Control Register 1"
|
|
bitfld.long 0x00 0. " PWDN ,Power down" "Not powered down,Powered down"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRC_CTRL2,CRC Global Control Register 2"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 24.--25. " CH4_MODE ,Channel 4 mode" "Data capture,Auto,,Full-CPU"
|
|
bitfld.long 0x00 16.--17. " CH3_MODE ,Channel 3 mode" "Data capture,Auto,,Full-CPU"
|
|
newline
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,,Full-CPU"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,,Full-CPU"
|
|
else
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,Semi-CPU,Full-CPU"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,Semi-CPU,Full-CPU"
|
|
endif
|
|
sif (cpu()==("TMS570LS3137-EP"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRC_INT_SET/CLR,CRC Interrupt Enable Set/Reset Register"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " CH2_TIMEOUTEN ,Channel 2 timeout interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " CH2_UNDEREN ,Channel 2 underrun interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " CH2_OVEREN ,Channel 2 overrun interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " CH2_CRCFAILEN ,Channel 2 CRC fail interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " CH2_CCITEN ,Channel 2 compression complete interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " CH1_TIMEOUTEN ,Channel 1 timeout interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " CH1_UNDEREN ,Channel 1 underrun interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " CH1_OVEREN ,Channel 1 overrun interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " CH1_CRCFAILEN ,Channel 1 CRC fail interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " CH1_CCITEN ,Channel 1 compression complete interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRC_INTS,CRC Interrupt Enable Set Register"
|
|
sif (!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled"
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT")
|
|
newline
|
|
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC_INTR,CRC Interrupt Enable Reset Register"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 Timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes"
|
|
newline
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT")
|
|
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes"
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT")
|
|
newline
|
|
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes"
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x00 28. " CH4_TIMEOUT ,Channel 4 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " CH4_UNDER ,Channel 4 CRC underrun status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 26. " CH4_OVER ,Channel 4 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " CH4_CRCFAIL ,Channel 4 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 20. " CH3_TIMEOUT ,Channel 3 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " CH3_UNDER ,Channel 3 CRC underrun status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 18. " CH3_OVER ,Channel 3 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " CH3_CRCFAIL ,Channel 3 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
newline
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336"))
|
|
newline
|
|
eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt"
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CRC_BUSY,CRC Busy Register"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 24. " CH4_BUSY ,Channel 4 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " CH3_BUSY ,Channel 3 busy flag" "Not busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "MCRC_TRACE_BUS_SEL,Data Bus Selection Register"
|
|
bitfld.long 0x00 2. " MEN ,Enable/disables the tracing of VBUSM" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTCMEN ,Enable/disables the tracing of data TCM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ITCMEN ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRC_TRACE_BUS_SEL,Data Bus Selection Register"
|
|
bitfld.long 0x00 2. " MEn ,Enable/disables the tracing of VBUSM" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTCMEn ,Enable/disables the tracing of data TCM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ITCMEn ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled"
|
|
endif
|
|
tree "Channel 1 Registers"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Channel 1 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,Channel 1 sector counter preload"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1"
|
|
in
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1 ,Channel 1 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD1,CRC channel 1 block complete timeout preload register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD1 ,Channel 1 block complete timeout counter preload"
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register"
|
|
rgroup.long 0x70++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL1,Channel 1 PSA Sector Signature Low Register 1"
|
|
line.long 0x04 "PSA_SECSIGREGH1,Channel 1 PSA Sector Signature High Register 1"
|
|
line.long 0x08 "RAW_DATAREGL1,Channel 1 Raw Data Low Register 1"
|
|
line.long 0x0C "RAW_DATAREGH1,Channel 1 Raw Data High Register 1"
|
|
tree.end
|
|
tree "Channel 2 Registers"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Channel 2 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,Channel 2 sector counter preload"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2"
|
|
in
|
|
group.long 0x8C++0x07
|
|
line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2 ,Channel 2 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD2 ,Channel 2 block complete timeout counter preload"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register"
|
|
rgroup.long 0xB0++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL2,Channel 2 PSA Sector Signature Low Register 2"
|
|
line.long 0x04 "PSA_SECSIGREGH2,Channel 2 PSA Sector Signature High Register 2"
|
|
line.long 0x08 "RAW_DATAREGL2,Channel 2 Raw Data Low Register 2"
|
|
line.long 0x0C "RAW_DATAREGH2,Channel 2 Raw Data High Register 2"
|
|
tree.end
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP"))
|
|
tree "Channel 3 Registers"
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register 3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT3[19:0] ,Channel 3 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG3,CRC Sector Counter Preload Register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT3[15:0] ,Channel 3 sector counter preload"
|
|
hgroup.long 0xC8++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG3,CRC Current Sector Register 3"
|
|
in
|
|
group.long 0xCC++0x07
|
|
line.long 0x00 "CRC_WDTOPLD3,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD3[23:0] ,Channel 3 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD3,CRC Channel 3 Block Complete Timeout Preload Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD3[23:0] ,Channel 3 block complete timeout counter preload"
|
|
group.long 0xE0++0x0F
|
|
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL3,Channel 3 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH3,Channel 3 CRC Value High Register"
|
|
rgroup.long 0xF0++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL3,Channel 3 PSA Sector Signature Low Register 3"
|
|
line.long 0x04 "PSA_SECSIGREGH3,Channel 3 PSA Sector Signature High Register 3"
|
|
line.long 0x08 "RAW_DATAREGL3,Channel 3 Raw Data Low Register 3"
|
|
line.long 0x0C "RAW_DATAREGH3,Channel 3 Raw Data High Register 3"
|
|
tree.end
|
|
tree "Channel 4 Registers"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register 4"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT4 ,Channel 4 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG4,CRC Sector Counter Preload Register 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT4 ,Channel 4 sector counter preload"
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG4,CRC Current Sector Register 4"
|
|
in
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "CRC_WDTOPLD4,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD4[23:0] ,Channel 4 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD4,CRC Channel 4 Block Complete Timeout Preload Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD4[23:0] ,Channel 4 block complete timeout counter preload"
|
|
group.long 0x120++0x0F
|
|
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL4,Channel 4 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH4,Channel 4 CRC Value High Register"
|
|
rgroup.long 0x130++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL4,Channel 4 PSA Sector Signature Low Register 4"
|
|
line.long 0x04 "PSA_SECSIGREGH4,Channel 4 PSA Sector Signature High Register 4"
|
|
line.long 0x08 "RAW_DATAREGL4,Channel 4 Raw Data Low Register 4"
|
|
line.long 0x0C "RAW_DATAREGH4,Channel 4 Raw Data High Register 4"
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCC (Dual-Clock Comparator)"
|
|
tree "Dcc1"
|
|
base ad:0xFFFFEC00
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,CNT0_VALID0,CNT1,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "REV,Revision ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
|
|
newline
|
|
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "CNTSEED0,DCC Counter 0 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter 0"
|
|
line.long 0x04 "VALIDSEED0,Valid 0 Seed Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid 0"
|
|
line.long 0x08 "CNTSEED1,DCC Counter 1 Seed Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter 1"
|
|
line.long 0x0C "STAT,Status Register"
|
|
eventfld.long 0x0C 1. " DONE_FLG ,Single-shot sequence done flag" "Not done,Done"
|
|
eventfld.long 0x0C 0. " ERR_FLG ,Error flag" "No error,Error"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "CNT0,DCC Counter 0 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter 0"
|
|
line.long 0x04 "VALID0,Valid 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Current value for DCC valid 0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNT1,DCC Counter 1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter 1"
|
|
sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
elif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
if (((per.l.be(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,,LF LPO,HF LPO,,EXTCLKIN,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,Flash HD,EXTCLKIN1,,Ring oscillator,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "OSCIN,PLL1,,EXTCLKIN1,LFLPO,HFLPO,,EXTCLKIN2,?..."
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP"))
|
|
sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")||cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,VCLK"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Dcc2"
|
|
base ad:0xFFFFF400
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,CNT0_VALID0,CNT1,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "REV,Revision ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
|
|
newline
|
|
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "CNTSEED0,DCC Counter 0 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter 0"
|
|
line.long 0x04 "VALIDSEED0,Valid 0 Seed Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid 0"
|
|
line.long 0x08 "CNTSEED1,DCC Counter 1 Seed Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter 1"
|
|
line.long 0x0C "STAT,Status Register"
|
|
eventfld.long 0x0C 1. " DONE_FLG ,Single-shot sequence done flag" "Not done,Done"
|
|
eventfld.long 0x0C 0. " ERR_FLG ,Error flag" "No error,Error"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "CNT0,DCC Counter 0 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter 0"
|
|
line.long 0x04 "VALID0,Valid 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Current value for DCC valid 0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNT1,DCC Counter 1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter 1"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
if (((per.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l.be(ad:0xFFFFF400+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,Flash HD,EXTCLKIN1,,Ring oscillator,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP"))
|
|
sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
if (((per.l(ad:0xFFFFF400+0x24))&0xF00000)==0xA00000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")||cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,VCLK"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0xFFFFF000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 16. " DMA_EN ,DMA enable" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 8.--9. " DEBUG_MODE ,Debug mode" "Suspend ignored,Block finished,Frame finished,Immediate stop"
|
|
newline
|
|
bitfld.long 0x00 0. " DMA_RES ,DMA software reset" "No reset,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PEND,Channel Pending Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " PEND[31] ,Channel 31 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " PEND[15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 pending register" "Inactive,Pending"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1642")||cpuis("AWR1642-CORE1")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FBREG,Fall Back Register For EMC"
|
|
bitfld.long 0x00 8.--11. " FSMFB ,Switch off RTL clock gating for all FSM logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
bitfld.long 0x00 0.--3. " VBUSPFB ,Switch off RTL clock gating for all VBUSP logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMASTAT,DMA Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " STCH[31] ,Status of DMA channel 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " [30] ,Status of DMA channel 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " [29] ,Status of DMA channel 29" "Inactive,Active"
|
|
bitfld.long 0x00 28. " [28] ,Status of DMA channel 28" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Status of DMA channel 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " [26] ,Status of DMA channel 26" "Inactive,Active"
|
|
bitfld.long 0x00 25. " [25] ,Status of DMA channel 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " [24] ,Status of DMA channel 24" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Status of DMA channel 23" "Inactive,Active"
|
|
bitfld.long 0x00 22. " [22] ,Status of DMA channel 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " [21] ,Status of DMA channel 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " [20] ,Status of DMA channel 20" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Status of DMA channel 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " [18] ,Status of DMA channel 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " [17] ,Status of DMA channel 17" "Inactive,Active"
|
|
bitfld.long 0x00 16. " [16] ,Status of DMA channel 16" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " STCH[15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Status of DMA channel 11" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [10] ,Status of DMA channel 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [9] ,Status of DMA channel 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [8] ,Status of DMA channel 8" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status of DMA channel 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " [6] ,Status of DMA channel 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " [5] ,Status of DMA channel 5" "Inactive,Active"
|
|
bitfld.long 0x00 4. " [4] ,Status of DMA channel 4" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status of DMA channel 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " [2] ,Status of DMA channel 2" "Inactive,Active"
|
|
bitfld.long 0x00 1. " [1] ,Status of DMA channel 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " [0] ,Status of DMA channel 0" "Inactive,Active"
|
|
width 10.
|
|
tree "Channel Enable Status Registers"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HWCHENAS,HWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHENA[31] ,HW channel 31 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HWCHENA[15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HWCHENAR,HWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHDIS[31] ,HW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " HWCHDIS[15] ,HW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SWCHENAS,SWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHENA[31] ,SW channel 31 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SWCHENA[15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 enable status" "Not triggered,Triggered"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SWCHENAR,SWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHDIS[31] ,SW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " SWCHDIS[15] ,SW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CHPRIOS,Channel Priority Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPS[31] ,Channel priority 31 set" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30 set" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29 set" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27 set" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26 set" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25 set" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23 set" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22 set" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21 set" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19 set" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18 set" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17 set" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " CPS[15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11 set" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10 set" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9 set" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7 set" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6 set" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5 set" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3 set" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2 set" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1 set" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0 set" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CHPRIOR,Channel Priority Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPL[31] ,Channel priority 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " CPL[15] ,Channel priority 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GCHIENAS,Global Channel Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHIE[31] ,Global channel interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GCHIE[15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GCHIENAR,Global Channel Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHID[31] ,Global channel interrupt disable 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt disable 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt disable 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt disable 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt disable 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt disable 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt disable 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt disable 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt disable 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt disable 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt disable 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt disable 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt disable 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt disable 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt disable 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt disable 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " GCHID[15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
endif
|
|
tree "DMA Request Assignment Registers"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0 ASI ,Channel 0 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1 ASI ,Channel 1 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2 ASI ,Channel 2 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3 ASI ,Channel 3 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4 ASI ,Channel 4 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5 ASI ,Channel 5 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6 ASI ,Channel 6 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7 ASI ,Channel 7 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8 ASI ,Channel 8 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9 ASI ,Channel 9 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel 11 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DREQASI4,DMA Request Assignment Register 4"
|
|
bitfld.long 0x00 24.--29. " CH16ASI ,Channel 16 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH17ASI ,Channel 17 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH18ASI ,Channel 18 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH19ASI ,Channel 19 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DREQASI5,DMA Request Assignment Register 5"
|
|
bitfld.long 0x00 24.--29. " CH20ASI ,Channel 20 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH21ASI ,Channel 21 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH22ASI ,Channel 22 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH23ASI ,Channel 23 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DREQASI6,DMA Request Assignment Register 6"
|
|
bitfld.long 0x00 24.--29. " CH24ASI ,Channel 24 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH25ASI ,Channel 25 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH26ASI ,Channel 26 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH27ASI ,Channel 27 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DREQASI7,DMA Request Assignment Register 7"
|
|
bitfld.long 0x00 24.--29. " CH28ASI ,Channel 28 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH29ASI ,Channel 29 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH30ASI ,Channel 30 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH31ASI ,Channel 31 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0ASI ,Channel CH0ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1ASI ,Channel CH1ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2ASI ,Channel CH2ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3ASI ,Channel CH3ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4ASI ,Channel CH4ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5ASI ,Channel CH5ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6ASI ,Channel CH6ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7ASI ,Channel CH7ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8ASI ,Channel CH8ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9ASI ,Channel CH9ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel CH10ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel CH11ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel CH12ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel CH13ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel CH14ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel CH15ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
endif
|
|
tree.end
|
|
width 6.
|
|
tree "Port Assignment Registers"
|
|
sif cpuis("AWR*")
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x08 "PAR2,Port Assignment Register 2"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x0C "PAR3,Port Assignment Register 3"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
elif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
tree "Interrupt Mapping Registers"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FTCMAP,FTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCAB[31] ,Frame transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Frame transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Frame transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Frame transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Frame transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Frame transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Frame transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Frame transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Frame transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Frame transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Frame transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Frame transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Frame transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Frame transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Frame transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Frame transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCAB[15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "LFSMAP,LFS Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSAB[31] ,Last frame started interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Last frame started interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Last frame started interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Last frame started interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Last frame started interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Last frame started interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Last frame started interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Last frame started interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Last frame started interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Last frame started interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Last frame started interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Last frame started interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Last frame started interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Last frame started interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Last frame started interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Last frame started interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSAB[15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "HBCMAP,HBC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCAB[31] ,Half block complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Half block complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Half block complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Half block complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Half block complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Half block complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Half block complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Half block complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Half block complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Half block complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Half block complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Half block complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Half block complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Half block complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Half block complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Half block complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCAB[15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Half block complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Half block complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Half block complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Half block complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half block complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Half block complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Half block complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Half block complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half block complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Half block complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Half block complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Half block complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BTCMAP,BTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCAB[31] ,Block transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Block transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Block transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Block transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Block transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Block transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Block transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Block transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Block transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Block transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Block transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Block transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Block transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Block transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Block transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Block transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCAB[15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BERMAP,BER Interrupt Mapping Register"
|
|
bitfld.long 0x00 31. " BERAB[31] ,Bus error interrupt of channel 31 to group A/B" "A,B"
|
|
bitfld.long 0x00 30. " [30] ,Bus error interrupt of channel 30 to group A/B" "A,B"
|
|
bitfld.long 0x00 29. " [29] ,Bus error interrupt of channel 29 to group A/B" "A,B"
|
|
bitfld.long 0x00 28. " [28] ,Bus error interrupt of channel 28 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Bus error interrupt of channel 27 to group A/B" "A,B"
|
|
bitfld.long 0x00 26. " [26] ,Bus error interrupt of channel 26 to group A/B" "A,B"
|
|
bitfld.long 0x00 25. " [25] ,Bus error interrupt of channel 25 to group A/B" "A,B"
|
|
bitfld.long 0x00 24. " [24] ,Bus error interrupt of channel 24 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Bus error interrupt of channel 23 to group A/B" "A,B"
|
|
bitfld.long 0x00 22. " [22] ,Bus error interrupt of channel 22 to group A/B" "A,B"
|
|
bitfld.long 0x00 21. " [21] ,Bus error interrupt of channel 21 to group A/B" "A,B"
|
|
bitfld.long 0x00 20. " [20] ,Bus error interrupt of channel 20 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bus error interrupt of channel 19 to group A/B" "A,B"
|
|
bitfld.long 0x00 18. " [18] ,Bus error interrupt of channel 18 to group A/B" "A,B"
|
|
bitfld.long 0x00 17. " [17] ,Bus error interrupt of channel 17 to group A/B" "A,B"
|
|
bitfld.long 0x00 16. " [16] ,Bus error interrupt of channel 16 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Bus error interrupt of channel 15 to group A/B" "A,B"
|
|
bitfld.long 0x00 14. " [14] ,Bus error interrupt of channel 14 to group A/B" "A,B"
|
|
bitfld.long 0x00 13. " [13] ,Bus error interrupt of channel 13 to group A/B" "A,B"
|
|
bitfld.long 0x00 12. " [12] ,Bus error interrupt of channel 12 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Bus error interrupt of channel 11 to group A/B" "A,B"
|
|
bitfld.long 0x00 10. " [10] ,Bus error interrupt of channel 10 to group A/B" "A,B"
|
|
bitfld.long 0x00 9. " [9] ,Bus error interrupt of channel 9 to group A/B" "A,B"
|
|
bitfld.long 0x00 8. " [8] ,Bus error interrupt of channel 8 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bus error interrupt of channel 7 to group A/B" "A,B"
|
|
bitfld.long 0x00 6. " [6] ,Bus error interrupt of channel 6 to group A/B" "A,B"
|
|
bitfld.long 0x00 5. " [5] ,Bus error interrupt of channel 5 to group A/B" "A,B"
|
|
bitfld.long 0x00 4. " [4] ,Bus error interrupt of channel 4 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bus error interrupt of channel 3 to group A/B" "A,B"
|
|
bitfld.long 0x00 2. " [2] ,Bus error interrupt of channel 2 to group A/B" "A,B"
|
|
bitfld.long 0x00 1. " [1] ,Bus error interrupt of channel 1 to group A/B" "A,B"
|
|
bitfld.long 0x00 0. " [0] ,Bus error interrupt of channel 0 to group A/B" "A,B"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FTCINTENAS,FTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTENA[31] ,FTC (frame transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCINTENA[15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FTCINTENAR,FTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTDIS[31] ,FTC (frame transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " FTCINTDIS[15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "LFSINTENAS,LFS Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTENA[31] ,LFS (last frame started) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSINTENA[15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "LFSINTENAR,LFS Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTDIS[31] ,LFS (last frame started) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " LFSINTDIS[15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "HBCINTENAS,HBC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "HBCINTENAR,HBC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt disable 0" "No,Yes"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BTCINTENAS,BTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BTCINTENAR,BTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Flag Registers"
|
|
width 10.
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GINTFLAG,Global Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GINT[31] ,Global interrupt flag for channel 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Global interrupt flag for channel 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Global interrupt flag for channel 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Global interrupt flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global interrupt flag for channel 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Global interrupt flag for channel 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Global interrupt flag for channel 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Global interrupt flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global interrupt flag for channel 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Global interrupt flag for channel 22" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Global interrupt flag for channel 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Global interrupt flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global interrupt flag for channel 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Global interrupt flag for channel 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Global interrupt flag for channel 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Global interrupt flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GINT[15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global interrupt flag for channel 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Global interrupt flag for channel 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Global interrupt flag for channel 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Global interrupt flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global interrupt flag for channel 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Global interrupt flag for channel 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Global interrupt flag for channel 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Global interrupt flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global interrupt flag for channel 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Global interrupt flag for channel 2" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Global interrupt flag for channel 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Global interrupt flag for channel 0" "Not pending,Pending"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FTCFLAG,FTC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " FTCI[31] ,Frame transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Frame transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Frame transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Frame transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Frame transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Frame transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Frame transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Frame transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Frame transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Frame transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Frame transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Frame transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Frame transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Frame transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Frame transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Frame transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " FTCI[15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Frame transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Frame transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Frame transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Frame transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Frame transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Frame transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Frame transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Frame transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Frame transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Frame transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Frame transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Frame transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LFSFLAG,LFS Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " LFSI[31] ,Last frame transfer started flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Last frame transfer started flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Last frame transfer started flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Last frame transfer started flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Last frame transfer started flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Last frame transfer started flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Last frame transfer started flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Last frame transfer started flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Last frame transfer started flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Last frame transfer started flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Last frame transfer started flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Last frame transfer started flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Last frame transfer started flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Last frame transfer started flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Last frame transfer started flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Last frame transfer started flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " LFSI[15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Last frame transfer started flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Last frame transfer started flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Last frame transfer started flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Last frame transfer started flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Last frame transfer started flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Last frame transfer started flag for channel for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Last frame transfer started flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Last frame transfer started flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Last frame transfer started flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Last frame transfer started flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Last frame transfer started flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Last frame transfer started flag for channel 0" "Not pending,Pending"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "HBCFLAG,HBC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " HBCI[31] ,Half of block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Half of block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Half of block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Half of block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Half of block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Half of block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Half of block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Half of block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Half of block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Half of block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Half of block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Half of block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Half of block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Half of block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Half of block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Half of block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " HBCI[15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Half of block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Half of block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Half of block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Half of block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Half of block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Half of block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Half of block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Half of block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Half of block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Half of block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Half of block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Half of block transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BTCFLAG,BER Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " BTCI[31] ,Block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " BTCI[15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Block transfer complete flag for channel 0" "Not pending,Pending"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " BERI[31] ,Bus error flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Bus error flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Bus error flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Bus error flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Bus error flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Bus error flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Bus error flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Bus error flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Bus error flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Bus error flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Bus error flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Bus error flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Bus error flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Bus error flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Bus error flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Bus error flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Bus error flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Bus error flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Bus error flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Bus error flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Bus error flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Bus error flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Bus error flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Bus error flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Bus error flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Bus error flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Bus error flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Bus error flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Bus error flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Bus error flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Bus error flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Bus error flag for channel 0" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 12.
|
|
tree "Interrupt Channel Offset Registers"
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "FTCAOFFSET,FTCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "LFSAOFFSET,LFSA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "HBCAOFFSET,HBCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "BTCAOFFSET,BTCA Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x15C++0x03
|
|
hide.long 0x00 "BERAOFFSET,BERA Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "FTCBOFFSET,FTCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "LFSBOFFSET,LFSB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "HBCBOFFSET,HBCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "BTCBOFFSET,BTCB Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "BERBOFFSET,BERB Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x178++0x13
|
|
line.long 0x00 "PTCRL,Port Control Register"
|
|
rbitfld.long 0x00 24. " PENDB ,Port B transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 17. " PSFRHQPB ,Port B high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 16. " PSFRLQPB ,Port B low priority queue priority scheme" "Fixed,Rotated"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x00 8. " PENDA ,Port A transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " BYA ,Bypass FIFO A" "Not limited,Limited"
|
|
bitfld.long 0x00 1. " PSFRHQPA ,Port A high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 0. " PSFRLQPA ,Port A low priority queue priority scheme" "Fixed,Rotated"
|
|
endif
|
|
line.long 0x04 "RTCTRL,RAM Test Control Register"
|
|
bitfld.long 0x04 0. " RTC ,RAM test control" "Disabled,Enabled"
|
|
line.long 0x08 "DCTRL,Debug Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rbitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
eventfld.long 0x08 16. " DMADBGS ,DMA debug status" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
line.long 0x0C "WPR,Watch Point Register"
|
|
newline
|
|
line.long 0x10 "WMR,Watch Point Mask Register"
|
|
bitfld.long 0x10 31. " WM[31:0] ,Watch point bit 31 mask" "0,1"
|
|
bitfld.long 0x10 30. ",Watch point bit 30 mask" "0,1"
|
|
bitfld.long 0x10 29. ",Watch point bit 29 mask" "0,1"
|
|
bitfld.long 0x10 28. ",Watch point bit 28 mask" "0,1"
|
|
bitfld.long 0x10 27. ",Watch point bit 27 mask" "0,1"
|
|
bitfld.long 0x10 26. ",Watch point bit 26 mask" "0,1"
|
|
bitfld.long 0x10 25. ",Watch point bit 25 mask" "0,1"
|
|
bitfld.long 0x10 24. ",Watch point bit 24 mask" "0,1"
|
|
bitfld.long 0x10 23. ",Watch point bit 23 mask" "0,1"
|
|
bitfld.long 0x10 22. ",Watch point bit 22 mask" "0,1"
|
|
bitfld.long 0x10 21. ",Watch point bit 21 mask" "0,1"
|
|
bitfld.long 0x10 20. ",Watch point bit 20 mask" "0,1"
|
|
bitfld.long 0x10 19. ",Watch point bit 19 mask" "0,1"
|
|
bitfld.long 0x10 18. ",Watch point bit 18 mask" "0,1"
|
|
bitfld.long 0x10 17. ",Watch point bit 17 mask" "0,1"
|
|
bitfld.long 0x10 16. ",Watch point bit 16 mask" "0,1"
|
|
bitfld.long 0x10 15. ",Watch point bit 15 mask" "0,1"
|
|
bitfld.long 0x10 14. ",Watch point bit 14 mask" "0,1"
|
|
bitfld.long 0x10 13. ",Watch point bit 13 mask" "0,1"
|
|
bitfld.long 0x10 12. ",Watch point bit 12 mask" "0,1"
|
|
bitfld.long 0x10 11. ",Watch point bit 11 mask" "0,1"
|
|
bitfld.long 0x10 10. ",Watch point bit 10 mask" "0,1"
|
|
bitfld.long 0x10 9. ",Watch point bit 9 mask" "0,1"
|
|
bitfld.long 0x10 8. ",Watch point bit 8 mask" "0,1"
|
|
bitfld.long 0x10 7. ",Watch point bit 7 mask" "0,1"
|
|
bitfld.long 0x10 6. ",Watch point bit 6 mask" "0,1"
|
|
bitfld.long 0x10 5. ",Watch point bit 5 mask" "0,1"
|
|
bitfld.long 0x10 4. ",Watch point bit 4 mask" "0,1"
|
|
bitfld.long 0x10 3. ",Watch point bit 3 mask" "0,1"
|
|
bitfld.long 0x10 2. ",Watch point bit 2 mask" "0,1"
|
|
bitfld.long 0x10 1. ",Watch point bit 1 mask" "0,1"
|
|
bitfld.long 0x10 0. ",Watch point bit 0 mask" "0,1"
|
|
width 11.
|
|
tree "Active Channel Registers"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
group.long 0x18C++0x0B
|
|
line.long 0x00 "PAACSADDR,Port A Active Channel Source Address Register"
|
|
line.long 0x04 "PAACDADDR,Port A Active Channel Destination Address Register"
|
|
line.long 0x08 "PAACTC,Port A Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PAFTCOUNT ,Port A active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PAETCOUNT ,Port A active channel element count"
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
else
|
|
rgroup.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x1A8++0x07
|
|
line.long 0x00 "DMAPCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " ERRA ,Error action" "Unchanged,Disabled"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits memory mapping" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "DMAPAR,Parity Error Address Register"
|
|
eventfld.long 0x04 24. " EDFLG ,Parity error detection flag" "No error,Error"
|
|
hexmask.long.word 0x04 0.--11. 0x01 " ERROR_ADDRESS ,Error address"
|
|
tree "DMA Memory Protection Registers"
|
|
width 11.
|
|
group.long 0x1B0++0x27
|
|
line.long 0x00 "DMAMPCTRL,DMA Memory Protection Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " INT3ENA ,Interrupt enable of region 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " REG3AP ,Region 3 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 24. " REG3ENA ,Region 3 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " INT2ENA ,Interrupt enable of region 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " REG2AP ,Region 2 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 16. " REG2ENA ,Region 2 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " INT1ENA ,Interrupt enable of region 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " REG1AP ,Region 1 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 8. " REG1ENA ,Region 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " INT0AB ,Interrupt assignment of region 0 to group A/B" "VIM,DSP"
|
|
bitfld.long 0x00 3. " INT0ENA ,Interrupt enable of region 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " REG0AP ,Region 0 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 0. " REG0ENA ,Region 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAMPST,Memory Protection Status Register"
|
|
eventfld.long 0x04 24. " REG3FT ,Region 3 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 16. " REG2FT ,Region 2 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " REG1FT ,Region 1 fault" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 0. " REG0FT ,Region 0 fault" "Not detected,Detected"
|
|
line.long 0x08 "DMAMPR0S,DMA Protection Region Starting Address 0 Register"
|
|
line.long 0x0C "DMAMPR0E,DMA Protection Region End Address 0 Register"
|
|
line.long 0x10 "DMAMPR1S,DMA Protection Region Starting Address 1 Register"
|
|
line.long 0x14 "DMAMPR1E,DMA Protection Region End Address 1 Register"
|
|
line.long 0x18 "DMAMPR2S,DMA Protection Region Starting Address 2 Register"
|
|
line.long 0x1C "DMAMPR2E,DMA Protection Region End Address 2 Register"
|
|
line.long 0x20 "DMAMPR3S,DMA Protection Region Starting Address 3 Register"
|
|
line.long 0x24 "DMAMPR3E,DMA Protection Region End Address 3 Register"
|
|
tree.end
|
|
base ad:0xFFF80000
|
|
tree "Control Packet Registers"
|
|
width 9.
|
|
tree.open "Primary Control Packet Registers"
|
|
tree "Primary Control Packet 0"
|
|
group.long (0x0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 1"
|
|
group.long (0x20)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x20+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 2"
|
|
group.long (0x40)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x40+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 3"
|
|
group.long (0x60)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 4"
|
|
group.long (0x80)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 5"
|
|
group.long (0xA0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xA0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 6"
|
|
group.long (0xC0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xC0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 7"
|
|
group.long (0xE0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xE0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 8"
|
|
group.long (0x100)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x100+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 9"
|
|
group.long (0x120)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x120+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 10"
|
|
group.long (0x140)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x140+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 11"
|
|
group.long (0x160)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x160+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 12"
|
|
group.long (0x180)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x180+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 13"
|
|
group.long (0x1A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 14"
|
|
group.long (0x1C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 15"
|
|
group.long (0x1E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 16"
|
|
group.long (0x200)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x200+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 17"
|
|
group.long (0x220)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x220+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 18"
|
|
group.long (0x240)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x240+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 19"
|
|
group.long (0x260)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x260+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 20"
|
|
group.long (0x280)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x280+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 21"
|
|
group.long (0x2A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 22"
|
|
group.long (0x2C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 23"
|
|
group.long (0x2E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 24"
|
|
group.long (0x300)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x300+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 25"
|
|
group.long (0x320)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x320+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 26"
|
|
group.long (0x340)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x340+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 27"
|
|
group.long (0x360)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x360+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 28"
|
|
group.long (0x380)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x380+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 29"
|
|
group.long (0x3A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 30"
|
|
group.long (0x3C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 31"
|
|
group.long (0x3E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree.end
|
|
tree.open "Working Control Packet Registers"
|
|
tree "Working Control Packet 0"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 1"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x10+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 2"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x20+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 3"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x30+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 4"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x40+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 5"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x50+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 6"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x60+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 7"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x70+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 8"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x80+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 9"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x90+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 10"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xA0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 11"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xB0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 12"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xC0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 13"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xD0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 14"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xE0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 15"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xF0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 16"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x100+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 17"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x110+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 18"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x120+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 19"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x130+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 20"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x140+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 21"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x150+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 22"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x160+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 23"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x170+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 24"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x180+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 25"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x190+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 26"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1A0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 27"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1B0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 28"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1C0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 29"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1D0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 30"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1E0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 31"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1F0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMM (Data Modification Module)"
|
|
base ad:0xFFFFF700
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GLBCTRL,DMM Global Control Register"
|
|
bitfld.long 0x00 24. " BUSY ,Busy indicator" "Not received,Received"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 18. " CONTCLK ,Continuous RTPCLK output" "Suspended,Continue"
|
|
else
|
|
bitfld.long 0x00 18. " CONTCLK ,Continuous DMMCLK input" "Suspended,Continue"
|
|
endif
|
|
bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 16. " RESET ,This bit resets the state machine and the registers to its reset value" "No reset,Reset"
|
|
bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in Direct Data Mode" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace Mode,Direct Data Mode"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x04 "INTSET_SET/CLR,DMM Interrupt Set Register"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x08 17. " PROG_BUFF ,Programmable buffer interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x08 16. " EO_BUFF ,End of buffer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " DEST3REG2 ,Destination 3 Region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " DEST3REG1 ,Destination 3 Region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " DEST2REG2 ,Destination 2 Region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " DEST2REG1 ,Destination 2 Region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DEST1REG2 ,Destination 1 Region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " DEST1REG1 ,Destination 1 Region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " DEST0REG2 ,Destination 0 Region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " DEST0REG1 ,Destination 0 Region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " DEST3_ERRENA ,Destination 3 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " DEST2_ERRENA ,Destination 2 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " DEST1_ERRENA_ ,Destination 1 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " DEST0_ERRENA ,Destination 0 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "INTLVL,DMM Interrupt Level Register"
|
|
bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 Region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 Region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 Region 2 Interrupt Level" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 Region 1 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 Region 2 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 Region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 Region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 Region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " DEST3_ERRENA ,Destination 3 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " DEST2_ERRENA ,Destination 2 error interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 2. " DEST1_ERRENA ,Destination 1 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " DEST0_ERRENA ,Destination 0 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1"
|
|
line.long 0x04 "INTFLAG,DMM Interrupt Flag Register"
|
|
eventfld.long 0x04 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 15. " DEST3REG2 ,Destination 3 Region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " DEST3REG1 ,Destination 3 Region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " DEST2REG2 ,Destination 2 Region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " DEST2REG1 ,Destination 2 Region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 11. " DEST1REG2 ,Destination 1 Region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " DEST1REG1 ,Destination 1 Region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 9. " DEST0REG2 ,Destination 0 Region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " DEST0REG1 ,Destination 0 Region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " DEST3_ERRENA ,Destination 3 error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 3. " DEST2_ERRENA ,Destination 2 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " DEST1_ERRENA ,Destination 1 error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " DEST0_ERRENA ,Destination 0 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "OFF1,DMM Interrupt Offset 1 Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "OFF2,DMM Interrupt Offset 2 Register"
|
|
in
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "DDMDEST,DDM Direct Data Mode Destination Register"
|
|
line.long 0x04 "DDMBL,DMM Direct Data Mode Blocksize Register"
|
|
bitfld.long 0x04 0.--3. " BLOCKSIZE ,These bits define the size of the buffer region" "0 B,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,?..."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DDMPT,DMM Direct Data Mode Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 1. " POINTER ,Hold the pointer to the next entry to be written in the buffer"
|
|
group.long 0x28++0x4B
|
|
line.long 0x00 "INTPT,DDM Direct Data Mode Interrupt Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 1. " INTPT ,Interrupt Pointer"
|
|
line.long 0x04 "DEST0REG1,DDM Destination 0 Region 1"
|
|
hexmask.long.word 0x04 18.--31. 0x04 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x08 "DEST0BL1,DDM Destination 0 Blocksize 1"
|
|
bitfld.long 0x08 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x0C "DEST0REG2,DDM Destination 0 Region 2"
|
|
hexmask.long.word 0x0C 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x10 "DEST0BL2,DDM Destination 0 Blocksize 2"
|
|
bitfld.long 0x10 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x14 "DEST1REG1,DDM Destination 1 Region 1"
|
|
hexmask.long.word 0x14 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x18 "DEST1BL1,DDM Destination 1 Blocksize 1"
|
|
bitfld.long 0x18 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x1C "DEST1REG2,DDM Destination 1 Region 2"
|
|
hexmask.long.word 0x1C 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x1C 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x20 "DEST1BL2,DDM Destination 1 Blocksize 2"
|
|
bitfld.long 0x20 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x24 "DEST2REG1,DDM Destination 2 Region 1"
|
|
hexmask.long.word 0x24 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x24 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x28 "DEST2BL1,DDM Destination 2 Blocksize 1"
|
|
bitfld.long 0x28 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x2C "DEST2REG2,DDM Destination 2 Region 2"
|
|
hexmask.long.word 0x2C 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x2C 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x30 "DEST2BL2,DDM Destination 2 Blocksize 2"
|
|
bitfld.long 0x30 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x34 "DEST3REG1,DDM Destination 3 Region 1"
|
|
hexmask.long.word 0x34 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x34 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x38 "DEST3BL1,DDM Destination 3 Blocksize 1"
|
|
bitfld.long 0x38 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x3C "DEST3REG2,DDM Destination 3 Region 2"
|
|
hexmask.long.word 0x3C 18.--31. 0x4 " BASEADDR ,Base Address"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " BLOCKADDR ,Block Address"
|
|
line.long 0x40 "DEST3BL2,DDM Destination 3 Blocksize 2"
|
|
bitfld.long 0x40 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
line.long 0x44 "PC0,DDM Pin Control 0 (FUNC)"
|
|
bitfld.long 0x44 18. " ENAFUNC ,DMMENA functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 17. " DATA15FUNC ,DMMDATA[15] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 16. " DATA14FUNC ,DMMDATA[14] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 15. " DATA13FUNC ,DMMDATA[13] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 14. " DATA12FUNC ,DMMDATA[12] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 13. " DATA11FUNC ,DMMDATA[11] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 12. " DATA10FUNC ,DMMDATA[10] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 11. " DATA9FUNC ,DMMDATA[9] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 10. " DATA8FUNC ,DMMDATA[8] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 9. " DATA7FUNC ,DMMDATA[7] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 8. " DATA6FUNC ,DMMDATA[6] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 7. " DATA5FUNC ,DMMDATA[5] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 6. " DATA4FUNC ,DMMDATA[4] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 5. " DATA3FUNC ,DMMDATA[3] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 4. " DATA2FUNC ,DMMDATA[2] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 3. " DATA1FUNC ,DMMDATA[1] functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 2. " DATA0FUNC ,DMMDATA[0] functional mode pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x44 1. " CLKFUNC ,DMMCLK functional mode pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x44 0. " SYNCFUNC ,DMMSYNC functional mode pin" "GIO mode,Functional mode"
|
|
line.long 0x48 "PC1,DDM Pin Control 1 (DIR)"
|
|
bitfld.long 0x48 18. " ENADIR ,DMMENA direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 17. " DATA15DIR ,DMMDATA[15] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 16. " DATA14DIR ,DMMDATA[14] direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 15. " DATA13DIR ,DMMDATA[13] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 14. " DATA12DIR ,DMMDATA[12] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 13. " DATA11DIR ,DMMDATA[11] direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 12. " DATA10DIR ,DMMDATA[10] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 11. " DATA9DIR ,DMMDATA[9] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 10. " DATA8DIR ,DMMDATA[8] direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 9. " DATA7DIR ,DMMDATA[7] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 8. " DATA6DIR ,DMMDATA[6] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 7. " DATA5DIR ,DMMDATA[5] direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 6. " DATA4DIR ,DMMDATA[4] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 5. " DATA3DIR ,DMMDATA[3] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 4. " DATA2DIR ,DMMDATA[2] direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 3. " DATA1DIR ,DMMDATA[1] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 2. " DATA0DIR ,DMMDATA[0] direction pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x48 1. " CLKDIR ,DMMCLK direction pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x48 0. " SYNCDIR ,DMMSYNC direction pin (GIO mode)" "Input,Output"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "PC2,DDM Pin Control 2 (DIN)"
|
|
bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High"
|
|
bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High"
|
|
bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High"
|
|
bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High"
|
|
bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High"
|
|
bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High"
|
|
bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High"
|
|
bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High"
|
|
bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High"
|
|
bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High"
|
|
bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High"
|
|
bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High"
|
|
bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High"
|
|
bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High"
|
|
bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PC3,DMM Pin Control 3 (OUT)"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT_set/clr ,DMMENA output state" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT_set/clr ,DMMDATA[15] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT_set/clr ,DMMDATA[14] output state" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT_set/clr ,DMMDATA[13] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT_set/clr ,DMMDATA[12] output state" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT_set/clr ,DMMDATA[11] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT_set/clr ,DMMDATA[10] output state" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT_set/clr ,DMMDATA[9] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT_set/clr ,DMMDATA[8] output state" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT_set/clr ,DMMDATA[7] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT_set/clr ,DMMDATA[6] output state" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT_set/clr ,DMMDATA[5] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT_set/clr ,DMMDATA[4] output state" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT_set/clr ,DMMDATA[3] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT_set/clr ,DMMDATA[2] output state" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT_set/clr ,DMMDATA[1] output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT_set/clr ,DMMDATA[0] output state" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT_set/clr ,DMMCLK output state" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT_set/clr ,DMMSYNC output state" "Low,High"
|
|
sif cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DSet,Pin Control 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DClr,Pin Control 5"
|
|
endif
|
|
group.long 0x84++0x0B
|
|
line.long 0x00 "PC6,DDM Pin Control 6 (PDR)"
|
|
bitfld.long 0x00 18. " ENAPDR ,DMMENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DATA15PDR ,DMMDATA[15] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DATA14PDR ,DMMDATA[14] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " DATA13PDR ,DMMDATA[13] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DATA12PDR ,DMMDATA[12] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DATA11PDR ,DMMDATA[11] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " DATA10PDR ,DMMDATA[10] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DATA9PDR ,DMMDATA[9] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DATA8PDR ,DMMDATA[8] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " DATA7PDR ,DMMDATA[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DATA6PDR ,DMMDATA[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DATA5PDR ,DMMDATA[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4PDR ,DMMDATA[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DATA3PDR ,DMMDATA[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DATA2PDR ,DMMDATA[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " DATA1PDR ,DMMDATA[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DATA0PDR ,DMMDATA[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKPDR ,DMMCLK open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " SYNCPDR ,DMMSYNC open drain enable" "Disabled,Enabled"
|
|
line.long 0x04 "PC7,DMM Pin Control 7 (PDIS)"
|
|
bitfld.long 0x04 18. " ENAPDIS ,DMMENA pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 17. " DATA15PDIS ,DMMDATA[15] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " DATA14PDIS ,DMMDATA[14] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 15. " DATA13PDIS ,DMMDATA[13] pull disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 14. " DATA12PDIS ,DMMDATA[12] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 13. " DATA11PDIS ,DMMDATA[11] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 12. " DATA10PDIS ,DMMDATA[10] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 11. " DATA9PDIS ,DMMDATA[9] pull disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10. " DATA8PDIS ,DMMDATA[8] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 9. " DATA7PDIS ,DMMDATA[7] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 8. " DATA6PDIS ,DMMDATA[6] Pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 7. " DATA5PDIS ,DMMDATA[5] pull disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6. " DATA4PDIS ,DMMDATA[4] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 5. " DATA3PDIS ,DMMDATA[3] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 4. " DATA2PDIS ,DMMDATA[2] Pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 3. " DATA1PDIS ,DMMDATA[1] pull disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2. " DATA0PDIS ,DMMDATA[0] pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 1. " CLKPDIS ,DMMCLK pull disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 0. " SYNCPDIS ,DMMSYNC pull disable" "Enabled,Disabled"
|
|
line.long 0x08 "PC8,DMM Pin Control 8 (PSEL)"
|
|
bitfld.long 0x08 18. " ENAPSEL ,DMMENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " DATA15PSEL ,DMMDATA[15] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 16. " DATA14PSEL ,DMMDATA[14] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 15. " DATA13PSEL ,DMMDATA[13] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " DATA12PSEL ,DMMDATA[12] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 13. " DATA11PSEL ,DMMDATA[11] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 12. " DATA10PSEL ,DMMDATA[10] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " DATA9PSEL ,DMMDATA[9] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 10. " DATA8PSEL ,DMMDATA[8] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 9. " DATA7PSEL ,DMMDATA[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " DATA6PSEL ,DMMDATA[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 7. " DATA5PSEL ,DMMDATA[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 6. " DATA4PSEL ,DMMDATA[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " DATA3PSEL ,DMMDATA[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 4. " DATA2PSEL ,DMMDATA[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 3. " DATA1PSEL ,DMMDATA[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " DATA0PSEL ,DMMDATA[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " CLKPDSEL ,DMMCLK pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 0. " SYNCPSEL ,DMMSYNC pull select" "Pull down,Pull up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ESM (Error Signaling Module)"
|
|
base ad:0xFFFFF500
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEPAPR1_SET/CLR,Enable Error Pin Action/Response Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31 (CCM-R4 - selftest)" "No influence,influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30 (DCC1 - error)" "No influence,influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28 (RAM odd bank (B1TCM))" "No influence,influence"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27 (CPU - selftest)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26 (RAM even bank (B0TCM)) - correctable error)" "No influence,influence"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24 (MibSPIP5 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23 (DCAN2 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22 (DCAN3 - parity)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21 (DCAN1 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19 (MibADC1 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18 (MibSPI3 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17 (MibSPI1 - parity)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16 (Flexray TU - MPU)" "No influence,influence"
|
|
setclrfld.long 0x00 15. 0x00 25. 0x04 15. " [15] ,Set/Clear influence on error pin 15 (VIM RAM - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14 (Flexray TU - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13 (DMA - imprecise write error)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12 (Flexray - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11 (Clock Monitor - interrupt)" "No influence,influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10 (PLL - Slip)" "No influence,influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9 (HET TU1/HET TU2 - MPU)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8 (HET TU1/HET TU2 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7 (N2HET1/N2HET2 - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6 (FMC - correctable error) - correctable error)" "No influence,influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5 (DMA - imprecise read error)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3 (DMA - parity)" "No influence,influence"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2 (DMA - MPU)" "No influence,influence"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1 (MibADC2 - parity)" "No influence,influence"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IESR1_SET/CLR,Interrupt Enable Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31 (CCM-R4 - selftest)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30 (DCC1 - error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28 (RAM odd bank (B1TCM))" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27 (CPU - selftest)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26 (RAM even bank (B0TCM))" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24 (MibSPIP5 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23 (DCAN2 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22 (DCAN3 - parity)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21 (DCAN1 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19 (MibADC1 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18 (MibSPI3 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17 (MibSPI1 - parity)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16 (Flexray TU - MPU)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15 (VIM RAM - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14 (Flexray TU - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13 (DMA - imprecise write error)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12 (Flexray - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11 (Clock Monitor - interrupt)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10 (PLL - slip)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9 (HET TU1/HET TU2 - MPU)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8 (HET TU1/HET TU2 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7 (N2HET1/N2HET2 - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6 (FMC - correctable error) - correctable error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5 (DMA - imprecise read error)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3 (DMA - parity)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2 (DMA - MPU)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1 (MibADC2 - parity)" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILSR1_SET/CLR,Interrupt Level Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31 (CCM-R4 - selftest)" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30 (DCC1 - error)" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28 (RAM odd bank (B1TCM))" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27 (CPU - selftest)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26 (RAM even bank (B0TCM))" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24 (MibSPIP5 - parity)" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23 (DCAN2 - parity)" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22 (DCAN3 - parity)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21 (DCAN1 - parity)" "Low,High"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19 (MibADC1 - parity)" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18 (MibSPI3 - parity)" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17 (MibSPI1 - parity)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16 (Flexray TU - MPU)" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15 (VIM RAM - parity)" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14 (Flexray TU - parity)" "Low,High"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13 (DMA - imprecise write error)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12 (Flexray - parity)" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11 (Clock Monitor - interrupt)" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10 (PLL - slip)" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9 (HET TU1/HET TU2 - MPU)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8 (HET TU1/HET TU2 - parity)" "Low,High"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7 (N2HET1/N2HET2 - parity)" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6 (FMC - correctable error)" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5 (DMA - imprecise read error)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3 (DMA - parity)" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2 (DMA - MPU)" "Low,High"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1 (MibADC2 - parity)" "Low,High"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SR1,Status Register 1"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31 (CCM-R4 - selftest)" "No error,error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30 (DCC1 - error)" "No error,error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28 (RAM odd bank (B1TCM))" "No error,error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27 (CPU - selftest)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26 (RAM even bank (B0TCM))" "No error,error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24 (MibSPIP5 - parity)" "No error,error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23 (DCAN2 - parity)" "No error,error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22 (DCAN3 - parity)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21 (DCAN1 - parity)" "No error,error"
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19 (MibADC1 - parity)" "No error,error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18 (MibSPI3 - parity)" "No error,error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17 (MibSPI1 - parity)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16 (Flexray TU - MPU)" "No error,error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15 (VIM RAM - parity)" "No error,error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14 (Flexray TU - parity)" "No error,error"
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13 (DMA - imprecise write error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12 (Flexray - parity)" "No error,error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11 (Clock Monitor - interrupt)" "No error,error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10 (PLL - slip)" "No error,error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9 (HET TU1/HET TU2 - MPU)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8 (HET TU1/HET TU2 - parity)" "No error,error"
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7 (N2HET1/N2HET2 - parity)" "No error,error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6 (FMC - correctable error)" "No error,error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5 (DMA - imprecise read error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3 (DMA - parity)" "No error,error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2 (DMA - MPU)" "No error,error"
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1 (MibADC2 - parity)" "No error,error"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR2_SET/CLR,Status Register 2"
|
|
eventfld.long 0x00 24. " ESF[24] ,Error status flag 24 (RTI_WWD_NMI)" "No error,error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12 (B1TCM - address bus parity error)" "No error,error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10 (B0TCM - address bus parity error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8 (B1TCM - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6 (B0TCM - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4 (FMC - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2 (CCM-R4 - compare)" "No error,error"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SR3,Status Register 3"
|
|
eventfld.long 0x00 7. " ESF[7] ,Error status flag 7 (FMC - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5 (B1TCM - ECC uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3 (B0TCM - ECC uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1 (eFuse Controller - autoload error)" "No error,error"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "EPSR,Error Pin Status Register"
|
|
bitfld.long 0x00 0. " EPSF ,Error pin status flag" "Active,Not active"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IOFFHR,Interrupt Offset High Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INTOFFH ,Offset high level interrupt"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "IOFFLR,Interrupt Offset Low Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INTOFFL ,Offset low level interrupt"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "LTCR,Low-Time Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LTC ,error pin Low-Time counter"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "LTCPR,Low-Time Counter Preload Register"
|
|
bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-Time Counter pre-load value [15:14]" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " [13:0] ,Low-time counter pre-load value [13:0]"
|
|
group.long 0x38++0x03
|
|
line.long 0x0 "EKR,Error Key Register"
|
|
bitfld.long 0x00 0.--3. " EKEY ,Error key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SSR2,Status Shadow Register"
|
|
eventfld.long 0x00 24. " ESF[24] ,Error status flag 24 (RTI_WWD_NMI)" "No error,error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12 (B1TCM - address bus parity error)" "No error,error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10 (B0TCM - address bus parity error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8 (B1TCM - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6 (B0TCM - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4 (Flash (ATCM) - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2 (CCM-R4 - compare)" "No error,error"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IEPSR4_SET/CLR,Influence Error pin Set/Status Register 4"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " IEPSET[62] ,Set/Clear influence on error pin 62 (DCC2 - error)" "No influence,influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/Clear influence on error pin 43 (Ethernet Controller master interface)" "No influence,influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/Clear influence on error pin 42 (PLL2 - slip)" "No influence,influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear influence on error pin 41 (eFuse Controller - self test error)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear influence on error pin 40 (eFuse Controller error)" "No influence,influence"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear influence on error pin 39 (Power domain controller self-test error)" "No influence,influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear influence on error pin 38 (Power domain controller compare error)" "No influence,influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear influence on error pin 37 (IOMM - mux configuration error)" "No influence,influence"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear influence on error pin 36 (FMC - uncorrectable error)" "No influence,influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear influence on error pin 35 (FMC - correctable error)" "No influence,influence"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IESR4_SET/CLR,Interrupt Enable Set/Status Register 4"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTENSET[62] ,Set/Clear interrupt enable pin 62 (DCC2 - error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/Clear interrupt enable pin 43 (Ethernet Controller master interface)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/Clear interrupt enable pin 42 (PLL2 - slip)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt enable pin 41 (eFuse Controller - self test error)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt enable pin 40 (eFuse Controller error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt enable pin 39 (Power domain controller self-test error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt enable pin 38 (Power domain controller compare error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt enable pin 37 (IOMM - mux configuration error)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt enable pin 36 (FMC - uncorrectable error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt enable pin 35 (FMC - correctable error)" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ILSR4_SET/CLR,Interrupt Level Set/Status Register 4"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVLSET[62] ,Set/Clear interrupt level pin 62 (DCC2 - error)" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/Clear interrupt level pin 43 (Ethernet Controller master interface)" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/Clear interrupt level pin 42 (PLL2 - slip)" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt level pin 41 (eFuse Controller - self test error)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt level pin 40 (eFuse Controller error)" "Low,High"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt level pin 39 (Power domain controller self-test error)" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt level pin 38 (Power domain controller compare error)" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt level pin 37 (IOMM - mux configuration error)" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt level pin 36 (FMC - uncorrectable error)" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt level pin 35 (FMC - correctable error)" "Low,High"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SR4_SET/CLR,Status Register 4"
|
|
eventfld.long 0x00 30. " INTLVLSET[62] ,Error status flag 62 (DCC2 - error)" "No error,error"
|
|
eventfld.long 0x00 11. " [43] ,Error status flag 43 (Ethernet Controller master interface)" "No error,error"
|
|
eventfld.long 0x00 10. " [42] ,Error status flag 42 (PLL2 - slip)" "No error,error"
|
|
eventfld.long 0x00 9. " [41] ,Error status flag 41 (eFuse Controller - self test error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 8. " [40] ,Error status flag 40 (eFuse Controller error)" "No error,error"
|
|
eventfld.long 0x00 7. " [39] ,Error status flag 39 (Power domain controller self-test error)" "No error,error"
|
|
eventfld.long 0x00 6. " [38] ,Error status flag 38 (Power domain controller compare error)" "No error,error"
|
|
eventfld.long 0x00 5. " [37] ,Error status flag 37 (IOMM - mux configuration error)" "No error,error"
|
|
newline
|
|
eventfld.long 0x00 4. " [36] ,Error status flag 36 (FMC - uncorrectable error)" "No error,error"
|
|
eventfld.long 0x00 3. " [35] ,Error status flag 35 (FMC - correctable error)" "No error,error"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "FLASHWRAPPER"
|
|
base ad:0xFFF87000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FRDCNTL,Read Control Register"
|
|
bitfld.long 0x00 8.--11. " RWAIT ,Random read wait state" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 4. " ASWSTEN ,Address setup wait state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ENPIPE ,Pipeline mode enable" "Disabled,Enabled"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "FSPRD,Special Read Control Register"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "FEDACCTRL1,Error Correction Control Register1"
|
|
bitfld.long 0x00 24. " SUSP_IGNR ,Suspend ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16.--19. " EDACMODE ,Error correction mode" "Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Detection mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode"
|
|
newline
|
|
bitfld.long 0x00 10. " EOFEN ,Error on one fail enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EZFEN ,Error on zero fail enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " EPEN ,Error profiling enable" "Disabled,Enabled"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 5. " EOCV ,One condition valid" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " EZCV ,Zero condition valid" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0.--3. " EDACEN ,Error detection and correction enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "FEDACCTRL2,Error Correction Control Register2"
|
|
hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single error correction threshold"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FCORERRCNT,Error Correction Counter Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long.word 0x00 0.--15. 1. "FERRCNT ,Single Error Correction Count"
|
|
endif
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "FCORERRADDR,Correctable Error Address"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long 0x00 3.--31. 0x08 "COR_ERR_ADD ,Correctable error address"
|
|
bitfld.long 0x00 0.--2. "B_OFF ,Byte offset" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "FCORERRPOS,Correctable Error Position Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 9. "BUS2 ,Bus 2 error" "Main Flash,OTP read"
|
|
bitfld.long 0x04 8. "TYPE ,Error type" "64 data bits,8 check bits"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 "ERR_POS ,Single-bit error address"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FEDACSTAT,Error Status Register"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "FUNC_ERR_ADD,Un-correctable Error Address"
|
|
hexmask.long 0x00 3.--31. 0x08 " UNC_ERR_ADD ,Un-correctable error address"
|
|
bitfld.long 0x00 0.--2. " WORD_OFFSET ,Last 3 digit of the address" "000,001,010,011,100,101,110,111"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FEDACSDIS,Error Detection Sector Disable"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FPPRIMADDRTAG,Primary Address Tag Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FREDUADDRTAG,Redundant Address Tag Register"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "FBPROT,Bank Protection Register"
|
|
bitfld.long 0x00 0. " PROTL1DIS ,Level 1 protection disabled" "No,Yes"
|
|
line.long 0x04 "FBSE,Bank Sector Enable Register"
|
|
bitfld.long 0x04 15. " BSE[15] ,Bank sector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " BSE[14] ,Bank sector enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " BSE[13] ,Bank sector enable 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 12. " BSE[12] ,Bank sector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " BSE[11] ,Bank sector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " BSE[10] ,Bank sector enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " BSE[9] ,Bank sector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " BSE[8] ,Bank sector enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " BSE[7] ,Bank sector enable 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " BSE[6] ,Bank sector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " BSE[5] ,Bank sector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BSE[4] ,Bank sector enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " BSE[3] ,Bank sector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " BSE[2] ,Bank sector enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BSE[1] ,Bank sector enable 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " BSE[0] ,Bank sector enable 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FBUSY,Bank Busy Register"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FBAC,Bank Access Control Register"
|
|
bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector protection disable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " OTPPROTDIS[6] ,OTP sector protection disable 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " OTPPROTDIS[5] ,OTP sector protection disable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " OTPPROTDIS[4] ,OTP sector protection disable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " OTPPROTDIS[3] ,OTP sector protection disable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OTPPROTDIS[2] ,OTP sector protection disable 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " OTPPROTDIS[1] ,OTP sector protection disable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " OTPPROTDIS[0] ,OTP sector protection disable 0" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BAGP[7:0] ,Bank active grace period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VREADST[7:0] ,VREAD setup"
|
|
line.long 0x04 "FBFALLBACK,Bank Fallback Power Register"
|
|
bitfld.long 0x04 6.--7. " BANKPWR3[1:0] ,Bank 3 fallback power mode" "Sleep,Standby,Reserved,Active"
|
|
bitfld.long 0x04 4.--5. " BANKPWR2[1:0] ,Bank 2 fallback power mode" "Sleep,Standby,Reserved,Active"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " BANKPWR1[1:0] ,Bank 1 fallback power mode" "Sleep,Standby,Reserved,Active"
|
|
bitfld.long 0x04 0.--1. " BANKPWR0[1:0] ,Bank 0 fallback power mode" "Sleep,Standby,Reserved,Active"
|
|
group.long 0x44++0x03
|
|
line.long 0x0 "FBNKPMPRDY,Bank/Pump Ready Register"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "FPAC1,Pump Access Control Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " PSLEEP[10:0] ,Pump sleep"
|
|
bitfld.long 0x00 0. " PUMPPWR ,Flash charge pump fallback power mode" "Sleep,Active"
|
|
line.long 0x04 "FPAC2,Pump Access Control Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " PAGP[15:0] ,Pump active grace period"
|
|
line.long 0x08 "FMAC,Module Access Control Register"
|
|
bitfld.long 0x8 0.--2. " BANK[2:0] ,Bank enable" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x00 17. " RVSUSP ,Read verify suspend" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " RVDER ,Read verify command currently underway" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " RVF ,Read verify failure" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 14. " ILA ,Illegal address" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " DBT ,Disturbance test fail" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " PGV ,Program verify" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 11. " PCV ,Precondition verify" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " EV ,Erase verify" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " CV ,Compact verify" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 8. " BUSY ,Busy" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " ERS ,Erase active" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " PGM ,Program active" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 5. " INVDAT ,Invalid data" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " CSTAT ,Command status" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " VOLTSTAT ,Core voltage status" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 2. " ESUSP ,Erase suspended" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " PSUSP ,Program suspended" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SLOCK ,Sector lock status" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FEMUDATMSW,EEPROM Emulation Data MSW Register"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FEMUDATLSW,EEPROM Emulation Data LSW Register"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FEMUECC,EEPROM Emulation ECC Register"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FLOCK,Flash Lock Register"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FEMUADDR,EEPROM Emulation Address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FDIAGCTRL,Diagnostic Control Register"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FRAWDATAH,Uncorrected Raw Data High"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "FRAWDATAL,Uncorrected Raw Data Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FRAWECC,Uncorrected Raw ECC"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FPAROVR,Parity Override"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FEDACSDIS2,Error Detection Sector Disable Register 2"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "FSM_WR_ENA,FSM Register Write Enable"
|
|
bitfld.long 0x00 0.--2. " WR_ENA ,FSM write enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "EEPROM_CONFIG,EEPROM Emulation configuration Register"
|
|
bitfld.long 0x00 16.--19. " EWAIT ,EEPROM wait state counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " AUTOSUSP_EN ,Auto suspend enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOSTART_GRACE ,Auto-suspend startup grace period"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PBIST (Programmable Built-In Self-Test)"
|
|
base ad:0xFFFFE400
|
|
width 13.
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "VarAddr0,Variable Address Register 0"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "VarAddr1,Variable Address Register 1"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "VarAddr2,Variable Address Register 2"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "VarAddr3,Variable Address Register 3"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "VarLpCnt0,Variable Loop Count Register 0"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "VarLpCnt1,Variable Loop Count Register 1"
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "VarLpCnt0,Variable Loop Count Register 0"
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "VarLpCnt1,Variable Loop Count Register 1"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "DD0,DD0 Data Register"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "DE0,DE0 Data Register"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "ConstAddr0,Constant Address Register 0"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "ConstAddr1,Constant Address Register 1"
|
|
group.long 0x138++0x3
|
|
line.long 0x0 "ConstAddr2,Constant Address Register 2"
|
|
group.long 0x13C++0x3
|
|
line.long 0x0 "ConstAddr3,Constant Address Register 3"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "ConstLpCnt0,Constant Loop Count Register 0"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "ConstLpCnt1,Constant Loop Count Register 1"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "ConstLpCnt2,Constant Loop Count Register 2"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "ConstLpCnt3,Constant Loop Count Register 3"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "ConstInc0,Constant Increment Register 0"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "ConstInc1,Constant Increment Register 1"
|
|
group.long 0x158++0x3
|
|
line.long 0x0 "ConstInc2,Constant Increment Register 2"
|
|
group.long 0x15C++0x3
|
|
line.long 0x0 "ConstInc3,Constant Increment Register 3"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "RamT,Ram Configuration"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "Dlr,Datalogger"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "Cms,ConstLpCntock Mux Select"
|
|
group.long 0x16C++0x3
|
|
line.long 0x0 "Str,ProgRam Control"
|
|
group.long 0x178++0x3
|
|
line.long 0x0 "Csr,Chip Select"
|
|
group.long 0x17C++0x3
|
|
line.long 0x0 "FDly,Fail Delay"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "PAct,PBIST Activate ROM Clock Enable"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "IdR,PBIST ID"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "Over,PBIST Override"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "Fsfr0,Fail Status Fail - Port 0"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "Fsfr1,Fail Status Fail - Port 1"
|
|
group.long 0x198++0x3
|
|
line.long 0x0 "Fsrc0,Fail Status Count - Port 0"
|
|
group.long 0x19C++0x3
|
|
line.long 0x0 "Fsrc1,Fail Status Count - Port 1"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "Fsra0,Fail Status Address - Port 0"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x0 "Fsra1,Fail Status Address - Port 1"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "Fsrdl0,Fail Status Data - Port 0"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "Fsrdl1,Fail Status Data - Port 1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "Rom,ROM Mask"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x0 "Algo,ROM Algorithm Mask"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x0 "RInfoL,Ram Info Mask Lower"
|
|
group.long 0x1CC++0x3
|
|
line.long 0x0 "RInfoU,Ram Info Mask Upper"
|
|
width 11.
|
|
tree.end
|
|
tree "PMM (Power Management Module)"
|
|
base ad:0xFFFF0000
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.be
|
|
endif
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOGICPDPWRCTRL0,Logic Power Domain Control Register 0"
|
|
bitfld.long 0x00 24.--27. " LOGICPDON[0] ,Power domain PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 16.--19. " [1] ,Power domain PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Power domain PD4 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 0.--3. " [3] ,Power domain PD5 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "LOGICPDCTRL1,Logic Power Domain Control Register"
|
|
line.long 0x04 "LOGICPDCTRL2,Logic Power Domain Control Register"
|
|
line.long 0x08 "LOGICPDCTRL3,Logic Power Domain Control Register"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEMPDPWRCTRL0,Memory Power Domain Control Register 0"
|
|
bitfld.long 0x00 24.--27. " MEMPDON[0] ,Power domain RAM_PD1 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 16.--19. " [1] ,Power domain RAM_PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Power domain RAM_PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MEMPDCTRL1,Memory Power Domain Control Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDCLK_DIS_SET/CLR,Power Domain Clock Disable Set/Clear Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDCLK_DIS[3] ,Clocks to logic power domain PD5 disable" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Clocks to logic power domain PD4 disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Clocks to logic power domain PD3 disable" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Clocks to logic power domain PD2 disable" "No,Yes"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISOEXTEND,Isolation Extension Register"
|
|
line.long 0x04 "ISOEXTENDSET,Isolation Extension SET Register"
|
|
line.long 0x08 "ISOEXTENDCLR,Isolation Extension CLEAR Register"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT0 ,Logic Power Domain Status Register 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain PD2" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain PD2" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT0 ,Logic power domain PD2 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT1 ,Logic Power Domain Status Register 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain PD3" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain PD3" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT1 ,Logic power domain PD3 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT2 ,Logic Power Domain Status Register 2 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain PD4" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain PD4" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON2 ,Current state of power domain PD4" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT2 ,Logic power domain PD4 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT3 ,Logic Power Domain Status Register 3 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS3 ,Logic in transition status for power domain PD5" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS3 ,Memory in transition status for power domain PD5" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON3 ,Current state of power domain PD5" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT3 ,Logic power domain PD5 power state" "Off,Idle,,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x50++0x2F
|
|
line.long 0x00 "LOGICPDPWRSTAT4,Logic Power Domain Power Status Register"
|
|
line.long 0x04 "LOGICPDPWRSTAT5,Logic Power Domain Power Status Register"
|
|
line.long 0x08 "LOGICPDPWRSTAT6,Logic Power Domain Power Status Register"
|
|
line.long 0x0C "LOGICPDPWRSTAT7,Logic Power Domain Power Status Register"
|
|
line.long 0x10 "LOGICPDPWRSTAT8,Logic Power Domain Power Status Register"
|
|
line.long 0x14 "LOGICPDPWRSTAT9,Logic Power Domain Power Status Register"
|
|
line.long 0x18 "LOGICPDPWRSTAT10,Logic Power Domain Power Status Register"
|
|
line.long 0x1C "LOGICPDPWRSTAT11,Logic Power Domain Power Status Register"
|
|
line.long 0x20 "LOGICPDPWRSTAT12,Logic Power Domain Power Status Register"
|
|
line.long 0x24 "LOGICPDPWRSTAT13,Logic Power Domain Power Status Register"
|
|
line.long 0x28 "LOGICPDPWRSTAT14,Logic Power Domain Power Status Register"
|
|
line.long 0x2C "LOGICPDPWRSTAT15,Logic Power Domain Power Status Register"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT0 ,Memory Power Domain Status Register 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT1 ,Memory Power Domain Status Register 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,,Active"
|
|
else
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT0 ,Memory Power Domain Status 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,,Active"
|
|
endif
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT1 ,Memory Power Domain Status 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,,Active"
|
|
endif
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT2 ,Memory Power Domain Status 2 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain RAM_PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain RAM_PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON2 ,Current state of power domain RAM_PD3" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT2 ,Memory power domain RAM_PD3 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT2 ,Memory power domain RAM_PD3 power state" "Off,Idle,,Active"
|
|
endif
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x8C++0x13
|
|
line.long 0x00 "MEMPWRSTAT3,Memory Power Domain Power Status Register"
|
|
line.long 0x04 "MEMPWRSTAT4,Memory Power Domain Power Status Register"
|
|
line.long 0x08 "MEMPWRSTAT5,Memory Power Domain Power Status Register"
|
|
line.long 0x0C "MEMPWRSTAT6,Memory Power Domain Power Status Register"
|
|
line.long 0x10 "MEMPWRSTAT7,Memory Power Domain Power Status Register"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "GLOBALCTRL1,Global Control Register 1"
|
|
bitfld.long 0x00 8. " PMCTRL_PWRDN ,PMC/PSCON power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " AUTO_CLK_WAKE_ENA ,Automatic clock enable on wake up" "Disabled,Enabled"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "GLOBALCTRL2,Global Control Register 2"
|
|
endif
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "GLOBALSTAT,Global Status Register"
|
|
bitfld.long 0x00 0. " PMCTRL_IDLE ,State of PMC and all PSCONs" "Not idle,Idle"
|
|
group.long 0xAC++0x17
|
|
line.long 0x00 "PRCKEYREG,PSCON Diagnostic Compare Key Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON mode key" "Lock step,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
|
|
else
|
|
bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON mode key" "Lock step,Lock step,Lock step,Lock step,Lock step,Lock step,Self-test,Lock step,Lock step,Error Forcing,Lock step,Lock step,Lock step,Lock step,Lock step,Self-test Error Forcing"
|
|
endif
|
|
newline
|
|
line.long 0x04 "LPDDCSTAT1,Logic PD PSCON Diagnostic Compare Status Register 1"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x04 19. " LCMPE[3] ,Logic power domain compare error for PD5" "No error,Error"
|
|
eventfld.long 0x04 18. " [2] ,Logic power domain compare error for PD4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " [1] ,Logic power domain compare error for PD3" "No error,Error"
|
|
eventfld.long 0x04 16. " [0] ,Logic power domain compare error for PD2" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x04 3. " LSTC[3] ,Logic power domain self-test complete for PD5" "Not completed,Completed"
|
|
rbitfld.long 0x04 2. " [2] ,Logic power domain self-test complete for PD4" "Not completed,Completed"
|
|
newline
|
|
rbitfld.long 0x04 1. " [1] ,Logic power domain self-test complete for PD3" "Not completed,Completed"
|
|
rbitfld.long 0x04 0. " [0] ,Logic power domain self-test complete for PD2" "Not completed,Completed"
|
|
else
|
|
eventfld.long 0x04 19. " LCMPE[3] ,Logic power domain compare error for PD5" "No error,Error"
|
|
eventfld.long 0x04 18. " [2] ,Logic power domain compare error for PD4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " [1] ,Logic power domain compare error for PD3" "No error,Error"
|
|
eventfld.long 0x04 16. " [0] ,Logic power domain compare error for PD2" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " LSTC[3] ,Logic power domain self-test complete for PD5" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " [2] ,Logic power domain self-test complete for PD4" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Logic power domain self-test complete for PD3" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " [0] ,Logic power domain self-test complete for PD2" "Not completed,Completed"
|
|
endif
|
|
line.long 0x08 "LPDDCSTAT2,Logic PD PSCON Diagnostic Compare Status Register 2"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x08 19. " LSTET[3] ,Logic power domain self-test error type for PD5" "During match test,During mismatch test"
|
|
rbitfld.long 0x08 18. " [2] ,Logic power domain self-test error type for PD4" "During match test,During mismatch test"
|
|
newline
|
|
rbitfld.long 0x08 17. " [1] ,Logic power domain self-test error type for PD3" "During match test,During mismatch test"
|
|
rbitfld.long 0x08 16. " [0] ,Logic power domain self-test error type for PD2" "During match test,During mismatch test"
|
|
newline
|
|
rbitfld.long 0x08 3. " LSTE[3] ,Logic power domain self-test error for PD5" "No error,Error"
|
|
rbitfld.long 0x08 2. " [2] ,Logic power domain self-test error for PD4" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x08 1. " [1] ,Logic power domain self-test error for PD3" "No error,Error"
|
|
rbitfld.long 0x08 0. " [0] ,Logic power domain self-test error for PD2" "No error,Error"
|
|
else
|
|
bitfld.long 0x08 19. " LSTET[3] ,Logic power domain self-test error type for PD5" "During match test,During mismatch test"
|
|
bitfld.long 0x08 18. " LSTET[2] ,Logic power domain self-test error type for PD4" "During match test,During mismatch test"
|
|
newline
|
|
bitfld.long 0x08 17. " LSTET[1] ,Logic power domain self-test error type for PD3" "During match test,During mismatch test"
|
|
bitfld.long 0x08 16. " LSTET[0] ,Logic power domain self-test error type for PD2" "During match test,During mismatch test"
|
|
newline
|
|
bitfld.long 0x08 3. " LSTE[3] ,Logic power domain self-test error for PD5" "No error,Error"
|
|
bitfld.long 0x08 2. " LSTE[2] ,Logic power domain self-test error for PD4" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 1. " LSTE[1] ,Logic power domain self-test error for PD3" "No error,Error"
|
|
bitfld.long 0x08 0. " LSTE[0] ,Logic power domain self-test error for PD2" "No error,Error"
|
|
endif
|
|
line.long 0x0C "MPDDCSTAT1,Memory PD PSCON Diagnostic Compare Status Register 1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x0C 18. " MCMPE2 ,Memory power domain compare error for RAM_PD3" "No error,Error"
|
|
newline
|
|
elif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")
|
|
bitfld.long 0x0C 18. " MCMPE2 ,Memory power domain compare error for RAM_PD3" "No error,Error"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x0C 17. " [1] ,Memory power domain compare error for RAM_PD2" "No error,Error"
|
|
eventfld.long 0x0C 16. " [0] ,Memory power domain compare error for RAM_PD1" "No error,Error"
|
|
newline
|
|
else
|
|
bitfld.long 0x0C 17. " MCMPE1 ,Memory power domain compare error for RAM_PD2" "No error,Error"
|
|
bitfld.long 0x0C 16. " MCMPE0 ,Memory power domain compare error for RAM_PD1" "No error,Error"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x0C 2. " MSTC2 ,Memory power domain self-test complete for RAM_PD3" "Not completed,Completed"
|
|
newline
|
|
elif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
bitfld.long 0x0C 2. " MSTC2 ,Memory power domain self-test complete for RAM_PD3" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x0C 1. " [1] ,Memory power domain self-test complete for RAM_PD2" "Not completed,Completed"
|
|
rbitfld.long 0x0C 0. " [0] ,Memory power domain self-test complete for RAM_PD1" "Not completed,Completed"
|
|
else
|
|
bitfld.long 0x0C 1. " MSTC1 ,Memory power domain self-test complete for RAM_PD2" "Not completed,Completed"
|
|
bitfld.long 0x0C 0. " MSTC0 ,Memory power domain self-test complete for RAM_PD1" "Not completed,Completed"
|
|
endif
|
|
line.long 0x10 "MPDDCSTAT2,Memory PD PSCON Diagnostic Compare Status Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x10 18. " MSTET2 ,Memory power domain self-test error type for RAM_PD3" "During match test,During mismatch test"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x10 17. " [1] ,Memory power domain self-test error type for RAM_PD2" "During match test,During mismatch test"
|
|
rbitfld.long 0x10 16. " [0] ,Memory power domain self-test error type for RAM_PD1" "During match test,During mismatch test"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 18. " MSTET2 ,Memory power domain self-test error type for RAM_PD3" "During match test,During mismatch test"
|
|
bitfld.long 0x10 17. " MSTET1 ,Memory power domain self-test error type for RAM_PD2" "During match test,During mismatch test"
|
|
bitfld.long 0x10 16. " MSTET0 ,Memory power domain self-test error type for RAM_PD1" "During match test,During mismatch test"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x10 2. " MSTE2 ,Memory power domain self-test error for RAM_PD3" "No error,Error"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x10 1. " [1] ,Memory power domain self-test error for RAM_PD2" "No error,Error"
|
|
rbitfld.long 0x10 0. " [0] ,Memory power domain self-test error for RAM_PD1" "No error,Error"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 2. " MSTE2 ,Memory power domain self-test error for RAM_PD3" "No error,Error"
|
|
bitfld.long 0x10 1. " MSTE1 ,Memory power domain self-test error for RAM_PD2" "No error,Error"
|
|
bitfld.long 0x10 0. " MSTE0 ,Memory power domain self-test error for RAM_PD1" "No error,Error"
|
|
newline
|
|
endif
|
|
line.long 0x14 "ISODIAGSTAT,Isolation Diagnostic Status Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x14 3. " ISO_DIAG3 ,Isolation diagnostic for PD5 disable" "No,Yes"
|
|
rbitfld.long 0x14 2. " [2] ,Isolation diagnostic for PD4 disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x14 1. " [1] ,Isolation diagnostic for PD3 disable" "No,Yes"
|
|
rbitfld.long 0x14 0. " [0] ,Isolation diagnostic for PD2 disable" "No,Yes"
|
|
else
|
|
bitfld.long 0x14 3. " ISO_DIAG3 ,Isolation diagnostic for PD5 enable" "Enabled,Disabled"
|
|
bitfld.long 0x14 2. " ISO_DIAG2 ,Isolation diagnostic for PD4 enable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x14 1. " ISO_DIAG1 ,Isolation diagnostic for PD3 enable" "Enabled,Disabled"
|
|
bitfld.long 0x14 0. " ISO_DIAG0 ,Isolation diagnostic for PD2 enable" "Enabled,Disabled"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTP (RAM Trace Port)"
|
|
sif COMP.AVAILABLE("RTP")
|
|
base CONVert.ADDRESSTODUALPORT(COMPonent.BASE("RTP",-1))
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "RTPGLBCTRL,RTP Global Control Register"
|
|
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC61"||cpuis("TMS570LS20216*")||cpu()=="TMS570LS31XX"||cpu()=="TMS570LS21XX"||cpu()=="TMS570LS10XX"||cpu()=="M48L"||cpu()=="TMS570PSFC66")
|
|
bitfld.long 0x00 24. " TEST ,FIFO RAM test enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " PRESCALER ,Rtpclk=1/prescaler" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x00 12.--13. " DDM_WIDTH[1:0] ,Word size in DDM" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 11. " DDM_RW ,Direct data mode read/write" "Read,Write"
|
|
bitfld.long 0x00 10. " TM_DDM ,Trace mode or direct data mode" "Trace mode,Direct data mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PW[1:0] ,Port width" "2 pins,4 pins,8 pins,16 pins"
|
|
bitfld.long 0x00 7. " RESET ,Reset of RTP module" "No reset,Reset"
|
|
bitfld.long 0x00 6. " CONTCLK ,Continuous RTPCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HOVF ,Halt on overflow" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66")
|
|
bitfld.long 0x00 4. " INV_RGN ,Invers trace regions" "Inside,Outside"
|
|
else
|
|
bitfld.long 0x00 4. " INVERSE ,Invers trace regions" "Inside,Outside"
|
|
endif
|
|
bitfld.long 0x00 0.--3. " ON/OFF ,RTP on or off" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x04 "RTPTRENA,RTP Trace Enable Register"
|
|
bitfld.long 0x04 24. " ENA4 ,FIFO4 enable" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
|
|
bitfld.long 0x04 16. " ENA3 ,FIFO3 enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x04 8. " ENA2 ,FIFO2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ENA1 ,FIFO1 enable" "Disabled,Enabled"
|
|
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTPGSR,RTP Global Status Register"
|
|
rbitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty"
|
|
eventfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " OVF2 ,Overflow FIFO2" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " OVF1 ,Overflow FIFO1" "No overflow,Overflow"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RTPGSR,RTP Global Status Register"
|
|
bitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty"
|
|
sif (cpu()=="TMS570PSFC66")
|
|
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
|
|
bitfld.long 0x00 10. " EMPTY3 ,FIFO 3 Empty" "Not empty,Empty"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty"
|
|
endif
|
|
bitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow"
|
|
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
|
|
bitfld.long 0x00 2. " OVFPE3 ,Overflow FIFO3" "No overflow,Overflow"
|
|
endif
|
|
bitfld.long 0x00 1. " OVFPE2 ,Overflow FIFO2" "No overflow,Overflow"
|
|
bitfld.long 0x00 0. " OVFPE1 ,Overflow FIFO1" "No overflow,Overflow"
|
|
endif
|
|
group.long 0x0C++0x23
|
|
line.long 0x00 "RTPRAM1REG1,RTP RAM 1 Trace Region 1 Register"
|
|
bitfld.long 0x00 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x00 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " STARTADDR ,Start address"
|
|
line.long 0x04 "RTPRAM1REG2,RTP RAM 1 Trace Region 2 Register"
|
|
bitfld.long 0x04 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x04 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x04 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " STARTADDR ,Start address"
|
|
line.long 0x08 "RTPRAM2REG1,RTP RAM 2 Trace Region 1 Register"
|
|
bitfld.long 0x08 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x08 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x08 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " STARTADDR ,Start address"
|
|
line.long 0x0C "RTPRAM2REG2,RTP RAM 2 Trace Region 2 Register"
|
|
bitfld.long 0x0C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x0C 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x0C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " STARTADDR ,Start address"
|
|
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
|
|
line.long 0x10 "RTPRAM3REG1,RTP RAM 3 Trace Region 1 Register"
|
|
bitfld.long 0x10 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x10 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x10 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x10 0.--17. 1. " STARTADDR ,Start address"
|
|
line.long 0x14 "RTPRAM3REG2,RTP RAM 3 Trace Region 2 Register"
|
|
bitfld.long 0x14 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x14 28. " RW ,Read/write" "Read,Write"
|
|
bitfld.long 0x14 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
hexmask.long.tbyte 0x14 0.--17. 1. " STARTADDR ,Start address"
|
|
endif
|
|
line.long 0x18 "RTPPERREG1,RTP Peripheral Trace Region 1 Register"
|
|
bitfld.long 0x18 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x18 28. " RW ,Read/write" "Read,Write"
|
|
sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE")
|
|
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
else
|
|
bitfld.long 0x18 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
endif
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " STARTADDR ,Start address"
|
|
line.long 0x1C "RTPPERREG2,RTP Peripheral Trace Region 2 Register"
|
|
bitfld.long 0x1C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
|
|
bitfld.long 0x1C 28. " RW ,Read/write" "Read,Write"
|
|
sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE")
|
|
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
|
|
else
|
|
bitfld.long 0x1C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
|
|
endif
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " STARTADDR ,Start address"
|
|
line.long 0x20 "RTPDDMW,RTP Direct Data Mode Write Register"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "RTPPC0,RTP Pin Control 0"
|
|
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of RTPENA pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 17. " CLKFUNC ,Functional mode of RTPCLK pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 16. " SYNCFUNC ,Functional mode of RTPSYNC pin" "GIO mode,Functional mode"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAFUNC ,Output state of RTPDATA pin 15" "GIO,Functional"
|
|
bitfld.long 0x00 14. " DATAFUNC ,Output state of RTPDATA pin 14" "GIO,Functional"
|
|
bitfld.long 0x00 13. " DATAFUNC ,Output state of RTPDATA pin 13" "GIO,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DATAFUNC ,Output state of RTPDATA pin 12" "GIO,Functional"
|
|
bitfld.long 0x00 11. " DATAFUNC ,Output state of RTPDATA pin 11" "GIO,Functional"
|
|
bitfld.long 0x00 10. " DATAFUNC ,Output state of RTPDATA pin 10" "GIO,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DATAFUNC ,Output state of RTPDATA pin 9" "GIO,Functional"
|
|
bitfld.long 0x00 8. " DATAFUNC ,Output state of RTPDATA pin 8" "GIO,Functional"
|
|
bitfld.long 0x00 7. " DATAFUNC ,Output state of RTPDATA pin 7" "GIO,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DATAFUNC ,Output state of RTPDATA pin 6" "GIO,Functional"
|
|
bitfld.long 0x00 5. " DATAFUNC ,Output state of RTPDATA pin 5" "GIO,Functional"
|
|
bitfld.long 0x00 4. " DATAFUNC ,Output state of RTPDATA pin 4" "GIO,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAFUNC ,Output state of RTPDATA pin 3" "GIO,Functional"
|
|
bitfld.long 0x00 2. " DATAFUNC ,Output state of RTPDATA pin 2" "GIO,Functional"
|
|
bitfld.long 0x00 1. " DATAFUNC ,Output state of RTPDATA pin 1" "GIO,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATAFUNC ,Output state of RTPDATA pin 0" "GIO,Functional"
|
|
line.long 0x04 "RTPPC1,RTP Pin Control 1"
|
|
bitfld.long 0x04 18. " ENADIR ,Direction of RTPENA pin" "Input,Output"
|
|
bitfld.long 0x04 17. " CLKDIR ,Direction of RTPCLK pin" "Input,Output"
|
|
bitfld.long 0x04 16. " SYNCDIR ,Direction of RTPSYNC pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DATADIR ,Output state of RTPDATA pin 15" "Input,Output"
|
|
bitfld.long 0x04 14. " DATADIR ,Output state of RTPDATA pin 14" "Input,Output"
|
|
bitfld.long 0x04 13. " DATADIR ,Output state of RTPDATA pin 13" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DATADIR ,Output state of RTPDATA pin 12" "Input,Output"
|
|
bitfld.long 0x04 11. " DATADIR ,Output state of RTPDATA pin 11" "Input,Output"
|
|
bitfld.long 0x04 10. " DATADIR ,Output state of RTPDATA pin 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DATADIR ,Output state of RTPDATA pin 9" "Input,Output"
|
|
bitfld.long 0x04 8. " DATADIR ,Output state of RTPDATA pin 8" "Input,Output"
|
|
bitfld.long 0x04 7. " DATADIR ,Output state of RTPDATA pin 7" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATADIR ,Output state of RTPDATA pin 6" "Input,Output"
|
|
bitfld.long 0x04 5. " DATADIR ,Output state of RTPDATA pin 5" "Input,Output"
|
|
bitfld.long 0x04 4. " DATADIR ,Output state of RTPDATA pin 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATADIR ,Output state of RTPDATA pin 3" "Input,Output"
|
|
bitfld.long 0x04 2. " DATADIR ,Output state of RTPDATA pin 2" "Input,Output"
|
|
bitfld.long 0x04 1. " DATADIR ,Output state of RTPDATA pin 1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DATADIR ,Output state of RTPDATA pin 0" "Input,Output"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RTPPC2,RTP Pin Control 2"
|
|
bitfld.long 0x00 18. " ENAIN ,State of RTPENA pin" "Low,High"
|
|
bitfld.long 0x00 17. " CLKIN ,State of RTPCLK pin" "Low,High"
|
|
bitfld.long 0x00 16. " SYNCIN ,State of RTPSYNC pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAIN ,Output state of RTPDATA pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " DATAIN ,Output state of RTPDATA pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " DATAIN ,Output state of RTPDATA pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DATAIN ,Output state of RTPDATA pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " DATAIN ,Output state of RTPDATA pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " DATAIN ,Output state of RTPDATA pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DATAIN ,Output state of RTPDATA pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " DATAIN ,Output state of RTPDATA pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " DATAIN ,Output state of RTPDATA pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DATAIN ,Output state of RTPDATA pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " DATAIN ,Output state of RTPDATA pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " DATAIN ,Output state of RTPDATA pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAIN ,Output state of RTPDATA pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " DATAIN ,Output state of RTPDATA pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " DATAIN ,Output state of RTPDATA pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATAIN ,Output state of RTPDATA pin 0" "Low,High"
|
|
group.long 0x40++0x17
|
|
line.long 0x00 "RTPPC3,RTP Pin Control 3"
|
|
bitfld.long 0x00 18. " ENAOUT ,Output state of RTPENA pin" "Low,High"
|
|
bitfld.long 0x00 17. " CLKOUT ,Output state of RTPCLK pin" "Low,High"
|
|
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66")
|
|
bitfld.long 0x00 16. " SYNCOUT ,Output state of RTPSYNC pins" "Low,High"
|
|
else
|
|
bitfld.long 0x00 16. " DATAOUT ,Output state of RTPDATA pins" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " DATAOUT ,Output state of RTPDATA pin 15" "Push/pull,Open drain"
|
|
bitfld.long 0x00 14. " DATAOUT ,Output state of RTPDATA pin 14" "Push/pull,Open drain"
|
|
bitfld.long 0x00 13. " DATAOUT ,Output state of RTPDATA pin 13" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DATAOUT ,Output state of RTPDATA pin 12" "Push/pull,Open drain"
|
|
bitfld.long 0x00 11. " DATAOUT ,Output state of RTPDATA pin 11" "Push/pull,Open drain"
|
|
bitfld.long 0x00 10. " DATAOUT ,Output state of RTPDATA pin 10" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DATAOUT ,Output state of RTPDATA pin 9" "Push/pull,Open drain"
|
|
bitfld.long 0x00 8. " DATAOUT ,Output state of RTPDATA pin 8" "Push/pull,Open drain"
|
|
bitfld.long 0x00 7. " DATAOUT ,Output state of RTPDATA pin 7" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DATAOUT ,Output state of RTPDATA pin 6" "Push/pull,Open drain"
|
|
bitfld.long 0x00 5. " DATAOUT ,Output state of RTPDATA pin 5" "Push/pull,Open drain"
|
|
bitfld.long 0x00 4. " DATAOUT ,Output state of RTPDATA pin 4" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATAOUT ,Output state of RTPDATA pin 3" "Push/pull,Open drain"
|
|
bitfld.long 0x00 2. " DATAOUT ,Output state of RTPDATA pin 2" "Push/pull,Open drain"
|
|
bitfld.long 0x00 1. " DATAOUT ,Output state of RTPDATA pin 1" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATAOUT ,Output state of RTPDATA pin 0" "Push/pull,Open drain"
|
|
line.long 0x04 "RTPPC4,RTP Pin Control 4"
|
|
bitfld.long 0x04 18. " ENASET ,Set output state of RTPENA pin to logic high" "No change,Set high"
|
|
bitfld.long 0x04 17. " CLKSET ,Set output state of RTPCLK pin to logic high" "No change,Set high"
|
|
bitfld.long 0x04 16. " SYNCSET ,Set output state of RTPSYNC pin to logic high" "No change,Set high"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DATASET ,Output state of RTPDATA pin 15" "Low,High"
|
|
bitfld.long 0x04 14. " DATASET ,Output state of RTPDATA pin 14" "Low,High"
|
|
bitfld.long 0x04 13. " DATASET ,Output state of RTPDATA pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DATASET ,Output state of RTPDATA pin 12" "Low,High"
|
|
bitfld.long 0x04 11. " DATASET ,Output state of RTPDATA pin 11" "Low,High"
|
|
bitfld.long 0x04 10. " DATASET ,Output state of RTPDATA pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DATASET ,Output state of RTPDATA pin 9" "Low,High"
|
|
bitfld.long 0x04 8. " DATASET ,Output state of RTPDATA pin 8" "Low,High"
|
|
bitfld.long 0x04 7. " DATASET ,Output state of RTPDATA pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATASET ,Output state of RTPDATA pin 6" "Low,High"
|
|
bitfld.long 0x04 5. " DATASET ,Output state of RTPDATA pin 5" "Low,High"
|
|
bitfld.long 0x04 4. " DATASET ,Output state of RTPDATA pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATASET ,Output state of RTPDATA pin 3" "Low,High"
|
|
bitfld.long 0x04 2. " DATASET ,Output state of RTPDATA pin 2" "Low,High"
|
|
bitfld.long 0x04 1. " DATASET ,Output state of RTPDATA pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DATASET ,Output state of RTPDATA pin 0" "Low,High"
|
|
line.long 0x08 "RTPPC5,RTP Pin Control 5"
|
|
bitfld.long 0x08 18. " ENACLR ,Set output state of RTPENA pin to logic low" "No change,Set low"
|
|
bitfld.long 0x08 17. " CLKCLR ,Set output state of RTPCLK pin to logic low" "No change,Set low"
|
|
bitfld.long 0x08 16. " SYNCCLR ,Set output state of RTPSYNC pin to logic low" "No change,Set low"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DATACLR ,Output state of RTPDATA pin 15" "Low,High"
|
|
bitfld.long 0x08 14. " DATACLR ,Output state of RTPDATA pin 14" "Low,High"
|
|
bitfld.long 0x08 13. " DATACLR ,Output state of RTPDATA pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DATACLR ,Output state of RTPDATA pin 12" "Low,High"
|
|
bitfld.long 0x08 11. " DATACLR ,Output state of RTPDATA pin 11" "Low,High"
|
|
bitfld.long 0x08 10. " DATACLR ,Output state of RTPDATA pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DATACLR ,Output state of RTPDATA pin 9" "Low,High"
|
|
bitfld.long 0x08 8. " DATACLR ,Output state of RTPDATA pin 8" "Low,High"
|
|
bitfld.long 0x08 7. " DATACLR ,Output state of RTPDATA pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DATACLR ,Output state of RTPDATA pin 6" "Low,High"
|
|
bitfld.long 0x08 5. " DATACLR ,Output state of RTPDATA pin 5" "Low,High"
|
|
bitfld.long 0x08 4. " DATACLR ,Output state of RTPDATA pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATACLR ,Output state of RTPDATA pin 3" "Low,High"
|
|
bitfld.long 0x08 2. " DATACLR ,Output state of RTPDATA pin 2" "Low,High"
|
|
bitfld.long 0x08 1. " DATACLR ,Output state of RTPDATA pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DATACLR ,Output state of RTPDATA pin 0" "Low,High"
|
|
line.long 0x0C "RTPPC6,RTP Pin Control 6"
|
|
bitfld.long 0x0C 18. " ENAPDR ,Open drain enable of RTPENA pin" "Normal mode,Open drain"
|
|
bitfld.long 0x0C 17. " CLKPDR ,Open drain enable of RTPCLK pin" "Normal mode,Open drain"
|
|
bitfld.long 0x0C 16. " SYNCPDR ,Open drain enable of RTPSYNC pin" "Normal mode,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " DATAPDR ,Output state of RTPDATA pin 15" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 14. " DATAPDR ,Output state of RTPDATA pin 14" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 13. " DATAPDR ,Output state of RTPDATA pin 13" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " DATAPDR ,Output state of RTPDATA pin 12" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 11. " DATAPDR ,Output state of RTPDATA pin 11" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 10. " DATAPDR ,Output state of RTPDATA pin 10" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DATAPDR ,Output state of RTPDATA pin 9" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 8. " DATAPDR ,Output state of RTPDATA pin 8" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 7. " DATAPDR ,Output state of RTPDATA pin 7" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DATAPDR ,Output state of RTPDATA pin 6" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 5. " DATAPDR ,Output state of RTPDATA pin 5" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 4. " DATAPDR ,Output state of RTPDATA pin 4" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DATAPDR ,Output state of RTPDATA pin 3" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 2. " DATAPDR ,Output state of RTPDATA pin 2" "Push/pull,Open drain"
|
|
bitfld.long 0x0C 1. " DATAPDR ,Output state of RTPDATA pin 1" "Push/pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " DATAPDR ,Output state of RTPDATA pin 0" "Push/pull,Open drain"
|
|
line.long 0x10 "RTPPC7,RTP Pin Control 7"
|
|
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT")
|
|
bitfld.long 0x10 18. " ENADIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes"
|
|
bitfld.long 0x10 17. " CLKDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes"
|
|
bitfld.long 0x10 16. " SYNCDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes"
|
|
else
|
|
bitfld.long 0x10 18. " ENAPDIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes"
|
|
bitfld.long 0x10 17. " CLKPDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes"
|
|
bitfld.long 0x10 16. " SYNCPDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 15. " DATADIS ,Output state of RTPDATA pin 15" "Enabled,Disabled"
|
|
bitfld.long 0x10 14. " DATADIS ,Output state of RTPDATA pin 14" "Enabled,Disabled"
|
|
bitfld.long 0x10 13. " DATADIS ,Output state of RTPDATA pin 13" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " DATADIS ,Output state of RTPDATA pin 12" "Enabled,Disabled"
|
|
bitfld.long 0x10 11. " DATADIS ,Output state of RTPDATA pin 11" "Enabled,Disabled"
|
|
bitfld.long 0x10 10. " DATADIS ,Output state of RTPDATA pin 10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DATADIS ,Output state of RTPDATA pin 9" "Enabled,Disabled"
|
|
bitfld.long 0x10 8. " DATADIS ,Output state of RTPDATA pin 8" "Enabled,Disabled"
|
|
bitfld.long 0x10 7. " DATADIS ,Output state of RTPDATA pin 7" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DATADIS ,Output state of RTPDATA pin 6" "Enabled,Disabled"
|
|
bitfld.long 0x10 5. " DATADIS ,Output state of RTPDATA pin 5" "Enabled,Disabled"
|
|
bitfld.long 0x10 4. " DATADIS ,Output state of RTPDATA pin 4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DATADIS ,Output state of RTPDATA pin 3" "Enabled,Disabled"
|
|
bitfld.long 0x10 2. " DATADIS ,Output state of RTPDATA pin 2" "Enabled,Disabled"
|
|
bitfld.long 0x10 1. " DATADIS ,Output state of RTPDATA pin 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " DATADIS ,Output state of RTPDATA pin 0" "Enabled,Disabled"
|
|
line.long 0x14 "RTPPC8,RTP Pin Control 8"
|
|
bitfld.long 0x14 18. " ENAPSEL ,Pull select of RTPENA pin" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 17. " CLKPSEL ,Pull select of RTPCLK pin" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 16. " SYNCPSEL ,Pull select of RTPSYNC pin" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DATAPSEL ,Output state of RTPDATA pin 15" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 14. " DATAPSEL ,Output state of RTPDATA pin 14" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 13. " DATAPSEL ,Output state of RTPDATA pin 13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " DATAPSEL ,Output state of RTPDATA pin 12" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 11. " DATAPSEL ,Output state of RTPDATA pin 11" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 10. " DATAPSEL ,Output state of RTPDATA pin 10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DATAPSEL ,Output state of RTPDATA pin 9" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 8. " DATAPSEL ,Output state of RTPDATA pin 8" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 7. " DATAPSEL ,Output state of RTPDATA pin 7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DATAPSEL ,Output state of RTPDATA pin 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 5. " DATAPSEL ,Output state of RTPDATA pin 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 4. " DATAPSEL ,Output state of RTPDATA pin 4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DATAPSEL ,Output state of RTPDATA pin 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 2. " DATAPSEL ,Output state of RTPDATA pin 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x14 1. " DATAPSEL ,Output state of RTPDATA pin 1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DATAPSEL ,Output state of RTPDATA pin 0" "Pull-down,Pull-up"
|
|
sif (cpu()!="TMS570LC4357"&&cpu()!="RM57L843-ZWT")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RTPIODFTCTRL,RTP IODFT Control"
|
|
hexmask.long.byte 0x00 8.--11. 1. " IODFTENA ,IO DFT enable"
|
|
bitfld.long 0x00 1. " LBENA ,Loop back enable" "Analog,Digital"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTI (Real Time Interrupt)"
|
|
base ad:0xFFFFFC00
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.be
|
|
endif
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
sif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
else
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 16.--17. " NTUSEL ,Select NTU signal" "NTU0,NTU1,?..."
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Started"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Started"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TBCTRL,Timebase Control Register"
|
|
bitfld.long 0x00 1. " INC ,Increment free running counter" "Not incremented,Incremented"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 0. " TBEXT ,Time base external" "Clocks FRC0,Not clocks FRC0"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 0. " TBEXT ,Time base external" "UC0,NTU"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CAPCTRL,Capture Control Register"
|
|
bitfld.long 0x00 1. " CAPCNTR1 ,Capture counter 1" "CES 0,CES 1"
|
|
bitfld.long 0x00 0. " CAPCNTR0 ,Capture counter 0" "CES 0,CES 1"
|
|
line.long 0x04 "COMPCTRL,Compare Control Register"
|
|
bitfld.long 0x04 12. " COMPSEL3 ,Compare select 3" "FRC0,FRC1"
|
|
bitfld.long 0x04 8. " COMPSEL2 ,Compare select 2" "FRC0,FRC1"
|
|
bitfld.long 0x04 4. " COMPSEL1 ,Compare select 1" "FRC0,FRC1"
|
|
newline
|
|
bitfld.long 0x04 0. " COMPSEL0 ,Compare select 0" "FRC0,FRC1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "FRC0,Free Running Counter 0 Register"
|
|
in
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FRC0,Free Running Counter 0 Register"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "UC0,Up Counter 0 Register"
|
|
line.long 0x04 "CPUC0,Compare Up Counter 0 Register"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "CAFRC0,Capture Free Running Counter 0 Register"
|
|
line.long 0x04 "CAUC0,Capture Up Counter 0 Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "FRC1,Free Running Counter 1 Register"
|
|
in
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FRC1,Free Running Counter 1 Register"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "UC1,Up Counter 1 Register"
|
|
line.long 0x04 "CPUC1,Compare Up Counter 1 Register"
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "CAFRC1,Capture Free Running Counter 1 Register"
|
|
line.long 0x04 "CAUC1,Capture Up Counter 1 Register"
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "COMP0,Compare 0 Register"
|
|
line.long 0x04 "UDCP0,Update Compare 0 Register"
|
|
line.long 0x08 "COMP1,Compare 1 Register"
|
|
line.long 0x0C "UDCP1,Update Compare 1 Register"
|
|
line.long 0x10 "COMP2,Compare 2 Register"
|
|
line.long 0x14 "UDCP2,Update Compare 2 Register"
|
|
line.long 0x18 "COMP3,Compare 3 Register"
|
|
line.long 0x1C "UDCP3,Update Compare 3 Register"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "TBLCOMP,External Clock Timebase Low Compare Register"
|
|
line.long 0x04 "TBHCOMP,External Clock Timebase High Compare Register"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SETINT_SET/CLR,Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SETOVL1IN_SET/CLR ,Free running counter 1 overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SETOVL0INT_SET/CLR ,Free running counter 0 overflow interrupt" "Disabled,Enabled"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SETTBINT_SET/CLR ,Timebase interrupt" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SETDMA3_SET/CLR ,Compare DMA request 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SETDMA2_SET/CLR ,Compare DMA request 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SETDMA1_SET/CLR ,Compare DMA request 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SETDMA0_SET/CLR ,Compare DMA request 0" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SETINT2_SET/CLR ,Compare interrupt 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SETINT1_SET/CLR ,Compare interrupt 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SETINT0_SET/CLR ,Compare interrupt 0" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "INTFLAG,Interrupt Flag Register"
|
|
eventfld.long 0x00 18. " OVL1INT ,Free running counter 1 overflow interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " OVL0INT ,Free running counter 0 overflow interrupt flag" "No interrupt,Interrupt"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
newline
|
|
eventfld.long 0x00 16. " TBINT ,Timebase interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt flag 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt flag 1" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt flag 0" "No interrupt,Interrupt"
|
|
sif (cpu()!="TMS570PSFC61")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "DWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "DWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "WDSTATUS,Watchdog Status Register"
|
|
sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
eventfld.long 0x08 0. " AWDST ,Analog watchdog status" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
line.long 0x0C "WDKEY,Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "WDCNTR,Digital Watchdog Down Counter"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,Digital watchdog down counter"
|
|
endif
|
|
sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "WWDRXNCTRL,Digital Windowed Watchdog Reaction Control"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
else
|
|
bitfld.long 0x00 0.--3. " DWDST ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
endif
|
|
line.long 0x04 "WWDSIZECTRL,Digital Windowed Watchdog Window Size Control"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")
|
|
group.long 0xAC++0x13
|
|
line.long 0x00 "INTCLRENABLE,Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x00 24.--27. " INTCLRENABLE3 ,Auto-clear functionality on the compare 3 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " INTCLRENABLE2 ,Auto-clear functionality on the compare 2 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " INTCLRENABLE1 ,Auto-clear functionality on the compare 1 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " INTCLRENABLE0 ,Auto-clear functionality on the compare 0 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "CMP0CLR,Compare 0 Clear Register"
|
|
line.long 0x08 "CMP1CLR,Compare 1 Clear Register"
|
|
line.long 0x0C "CMP2CLR,Compare 2 Clear Register"
|
|
line.long 0x10 "CMP3CLR,Compare 3 Clear Register"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "STC (Self-Test Controller)"
|
|
base ad:0xFFFFE600
|
|
width 7.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,STC global control register0"
|
|
hexmask.long.word 0x00 16.--31. 1. " INTCOUNT ,Number of intervals of selftest run"
|
|
bitfld.long 0x00 0. " RS_CNT ,Restart or Continue" "Continue,Restart"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,STC Global Control Register1"
|
|
bitfld.long 0x00 0.--3. " STC_ENA ,Self test run enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "TPR,Self Test Run Timeout Counter Preload Register"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "CADDR,Current ROM Address Register"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CICR,Current Interval Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " N ,Interval Number"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GSTAT,SelfTest Global Status Register"
|
|
bitfld.long 0x00 1. " TEST_FAIL ,Test Fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TEST_DONE ,Test Done" "Not completed,Completed"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FSTAT,SelfTest Fail Status Register"
|
|
bitfld.long 0x00 2. " TO_ERR ,Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 1. " CPU2_FAIL ,CPU2 failure info" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " CPU1_FAIL ,CPU1 failure info" "Not failed,Failed"
|
|
width 15.
|
|
sif (cpu()=="RM42L432")
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "CPU2_CURMISR3,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "CPU2_CURMISR2,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CPU2_CURMISR1,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "CPU2_CURMISR0,Cpu 2 Current Misr Register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "STCSCSCR,Signature Compare Self Check Register"
|
|
bitfld.long 0x00 4. " FAULT_INS ,Fault Insertion" "No fault,Fault"
|
|
bitfld.long 0x00 0.--3. " SELF_CHECK_KEY ,Signature compare logic self-check key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "CPU1_CURMISR3,Cpu 1 Current Misr Register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "CPU1_CURMISR2,Cpu 1 Current Misr Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CPU1_CURMISR1,Cpu 1 Current Misr Register"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "CPU1_CURMISR0,Cpu 1 Current Misr Register"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "CPU2_CURMISR3,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "CPU2_CURMISR2,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "CPU2_CURMISR1,Cpu 2 Current Misr Register"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "CPU2_CURMISR0,Cpu 2 Current Misr Register"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "SYS (System Registers)"
|
|
tree "SYS1"
|
|
base ad:0xFFFFFF00
|
|
width 9.
|
|
tree "System Pin Control Registers"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "SYSPC1,SYS Pin Control Register 1"
|
|
bitfld.long 0x00 0. " ECPCLKFUN ,ECPCLK Function" "GIO,ECPCLK"
|
|
line.long 0x04 "SYSPC2,SYS Pin Control Register 2"
|
|
bitfld.long 0x04 0. " ECPCLKDIR ,ECPCLK Data Direction" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "SYSPC3,SYS Pin Control Register 3"
|
|
bitfld.long 0x00 0. " ECPCLKDIN ,ECPCLK Data In" "Low,High"
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
elif (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x3
|
|
hide.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
elif (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x3
|
|
hide.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000))
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x7
|
|
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
hide.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x7
|
|
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
hide.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive"
|
|
else
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive"
|
|
else
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01000000)==0x00))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up"
|
|
else
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01)==0x00))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up"
|
|
else
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
endif
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "SYSPC10,SYS Pin Control Register 10"
|
|
bitfld.long 0x00 0. " ECPCLK_SLEW ,ECPCLK Slew Control" "Fast,Slow"
|
|
endif
|
|
tree.end
|
|
tree "System SSW PLL BIST Control Registers"
|
|
sif !(cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336")||(cpu()=="RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432"||cpu()=="RM48L550-ZWT"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SSWPLL1,SSW PLL BIST Control Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Window capture index"
|
|
bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter Read Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS[3:1] ,TAP Counter Disable" "Bit 16,Bit 18,Bit 20,Bit 22,Bit 24,Bit 26,Bit 28,Bit 30"
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Modulation Depth/Frequency Measurement mode" "Modulation Dept,Frequency"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SSWPLL2,SSW PLL BIST Control Register 2"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "SSWPLL3,SSW PLL BIST Control Register 3"
|
|
endif
|
|
tree.end
|
|
width 7.
|
|
tree "System Clock Source/Domain Disable Registers"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CSDIS,Clock Source Disable Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF_set/clr ,Clock Source 7 (External Clock In 2) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF_set/clr ,Clock Source 6 (PLL2) Off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF_set/clr ,Clock Source 5 (LPO High Frequency Clock) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF_set/clr ,Clock Source 4 (LPO Low Frequency Clock) Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF_set/clr ,Clock Source 3 (External Clock In) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF_set/clr ,Clock Source 1 (PLL1) Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF_set/clr ,Clock Source 0 (Oscillator) Off" "Enabled,Disabled"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "CDDIS,Clock Domain Disable Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " VCLKA4OFF_set/clr ,VCLKA4 Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " VCLKA3OFF_set/clr ,VCLKA3 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " VCLK3OFF_set/clr ,VCLK3 Domain Off" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " VCLK_EQEP_OFF_set/clr ,VCLK_EQEP_OFF domain off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF_set/clr ,RTICLK1 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF_set/clr ,VCLKA2 Domain Off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF_set/clr ,VCLKA1 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF_set/clr ,VCLK2 Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF_set/clr ,VCLKP Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF_set/clr ,HCLK Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF_set/clr ,GCLK Domain Off" "Enabled,Disabled"
|
|
tree.end
|
|
width 13.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "VCLKASRC,Peripheral Asynchronous Clock Source Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,?..."
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "RCLKSRC,RTI Clock Source Register"
|
|
bitfld.long 0x00 8.--9. " RTI1DIV[1:0] ,RTI Clock 1 Divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
width 13.
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CSVSTAT,Clock Source Valid Status Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 7. " CLKSR7V ,Clock Source 7 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " CLKSR6V ,Clock Source 6 Valid" "Not valid,Valid"
|
|
endif
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock Source 5 Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock Source 4 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock Source 3 Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock Source 1 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock Source 0 Valid" "Not valid,Valid"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hexmask.long.byte 0x00 16.--23. 1. " MBIST_ALGSEL ,Selects Different Algorithm for MBIST"
|
|
bitfld.long 0x00 8.--9. " ROM_DIV[1:0] ,ROM Clock Source Prescaler Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8"
|
|
endif
|
|
bitfld.long 0x00 0.--3. " MSTGENA[3:0] ,Memory Self-Test Controller Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "MINITGCR,Memory Hardware Initialization Global Control Register"
|
|
bitfld.long 0x00 0.--3. " MINITGENA[3:0] ,Memory Hardware Initialization Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register"
|
|
bitfld.long 0x00 31. " MSIENA31 ,MBIST Controller/Memory Initialization Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MSIENA30 ,MBIST Controller/Memory Initialization Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MSIENA29 ,MBIST Controller/Memory Initialization Enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSIENA28 ,MBIST Controller/Memory Initialization Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MSIENA27 ,MBIST Controller/Memory Initialization Enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MSIENA26 ,MBIST Controller/Memory Initialization Enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MSIENA25 ,MBIST Controller/Memory Initialization Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MSIENA24 ,MBIST Controller/Memory Initialization Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MSIENA23 ,MBIST Controller/Memory Initialization Enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MSIENA22 ,MBIST Controller/Memory Initialization Enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MSIENA21 ,MBIST Controller/Memory Initialization Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MSIENA20 ,MBIST Controller/Memory Initialization Enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSIENA19 ,MBIST Controller/Memory Initialization Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MSIENA18 ,MBIST Controller/Memory Initialization Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MSIENA17 ,MBIST Controller/Memory Initialization Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSIENA16 ,MBIST Controller/Memory Initialization Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MSIENA15 ,MBIST Controller/Memory Initialization Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MSIENA14 ,MBIST Controller/Memory Initialization Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MSIENA13 ,MBIST Controller/Memory Initialization Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MSIENA12 ,MBIST Controller/Memory Initialization Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MSIENA11 ,MBIST Controller/Memory Initialization Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MSIENA10 ,MBIST Controller/Memory Initialization Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MSIENA9 ,MBIST Controller/Memory Initialization Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MSIENA8 ,MBIST Controller/Memory Initialization Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSIENA7 ,MBIST Controller/Memory Initialization Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MSIENA6 ,MBIST Controller/Memory Initialization Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MSIENA5 ,MBIST Controller/Memory Initialization Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MSIENA4 ,MBIST Controller/Memory Initialization Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MSIENA3 ,MBIST Controller/Memory Initialization Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSIENA2 ,MBIST Controller/Memory Initialization Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSIENA1 ,MBIST Controller/Memory Initialization Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSIENA0 ,MBIST Controller/Memory Initialization Enable 0" "Disabled,Enabled"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "MSTFAIL,Memory Self-Test Fail Status Register"
|
|
eventfld.long 0x00 31. " MSTF31 ,Memory Self-Test Fail Status 31" "Not failed,Failed"
|
|
eventfld.long 0x00 30. " MSTF30 ,Memory Self-Test Fail Status 30" "Not failed,Failed"
|
|
eventfld.long 0x00 29. " MSTF29 ,Memory Self-Test Fail Status 29" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 28. " MSTF28 ,Memory Self-Test Fail Status 28" "Not failed,Failed"
|
|
eventfld.long 0x00 27. " MSTF27 ,Memory Self-Test Fail Status 27" "Not failed,Failed"
|
|
eventfld.long 0x00 26. " MSTF26 ,Memory Self-Test Fail Status 26" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 25. " MSTF25 ,Memory Self-Test Fail Status 25" "Not failed,Failed"
|
|
eventfld.long 0x00 24. " MSTF24 ,Memory Self-Test Fail Status 24" "Not failed,Failed"
|
|
eventfld.long 0x00 23. " MSTF23 ,Memory Self-Test Fail Status 23" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 22. " MSTF22 ,Memory Self-Test Fail Status 22" "Not failed,Failed"
|
|
eventfld.long 0x00 21. " MSTF21 ,Memory Self-Test Fail Status 21" "Not failed,Failed"
|
|
eventfld.long 0x00 20. " MSTF20 ,Memory Self-Test Fail Status 20" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " MSTF19 ,Memory Self-Test Fail Status 19" "Not failed,Failed"
|
|
eventfld.long 0x00 18. " MSTF18 ,Memory Self-Test Fail Status 18" "Not failed,Failed"
|
|
eventfld.long 0x00 17. " MSTF17 ,Memory Self-Test Fail Status 17" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " MSTF16 ,Memory Self-Test Fail Status 16" "Not failed,Failed"
|
|
eventfld.long 0x00 15. " MSTF15 ,Memory Self-Test Fail Status 15" "Not failed,Failed"
|
|
eventfld.long 0x00 14. " MSTF14 ,Memory Self-Test Fail Status 14" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 13. " MSTF13 ,Memory Self-Test Fail Status 13" "Not failed,Failed"
|
|
eventfld.long 0x00 12. " MSTF12 ,Memory Self-Test Fail Status 12" "Not failed,Failed"
|
|
eventfld.long 0x00 11. " MSTF11 ,Memory Self-Test Fail Status 11" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 10. " MSTF10 ,Memory Self-Test Fail Status 10" "Not failed,Failed"
|
|
eventfld.long 0x00 9. " MSTF9 ,Memory Self-Test Fail Status 9" "Not failed,Failed"
|
|
eventfld.long 0x00 8. " MSTF8 ,Memory Self-Test Fail Status 8" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MSTF7 ,Memory Self-Test Fail Status 7" "Not failed,Failed"
|
|
eventfld.long 0x00 6. " MSTF6 ,Memory Self-Test Fail Status 6" "Not failed,Failed"
|
|
eventfld.long 0x00 5. " MSTF5 ,Memory Self-Test Fail Status 5" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " MSTF4 ,Memory Self-Test Fail Status 4" "Not failed,Failed"
|
|
eventfld.long 0x00 3. " MSTF3 ,Memory Self-Test Fail Status 3" "Not failed,Failed"
|
|
eventfld.long 0x00 2. " MSTF2 ,Memory Self-Test Fail Status 2" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MSTF1 ,Memory Self-Test Fail Status 1" "Not failed,Failed"
|
|
eventfld.long 0x00 0. " MSTF0 ,Memory Self-Test Fail Status 0" "Not failed,Failed"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "MSTCGSTAT,MSTC Global Status Register"
|
|
eventfld.long 0x00 8. " MINIDONE ,Memory Hardware Initililization Test Run Complete Status" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " MSTDONE ,Memory Self-Test Run Complete Status" "Not completed,Completed"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "MINISTAT,Memory Hardware Initialization Status Register"
|
|
eventfld.long 0x00 31. " MIDONE31 ,Memory Hardware Initialization Status 31" "Not completed,Completed"
|
|
eventfld.long 0x00 30. " MIDONE30 ,Memory Hardware Initialization Status 30" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 29. " MIDONE29 ,Memory Hardware Initialization Status 29" "Not completed,Completed"
|
|
eventfld.long 0x00 28. " MIDONE28 ,Memory Hardware Initialization Status 28" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 27. " MIDONE27 ,Memory Hardware Initialization Status 27" "Not completed,Completed"
|
|
eventfld.long 0x00 26. " MIDONE26 ,Memory Hardware Initialization Status 26" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 25. " MIDONE25 ,Memory Hardware Initialization Status 25" "Not completed,Completed"
|
|
eventfld.long 0x00 24. " MIDONE24 ,Memory Hardware Initialization Status 24" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 23. " MIDONE23 ,Memory Hardware Initialization Status 23" "Not completed,Completed"
|
|
eventfld.long 0x00 22. " MIDONE22 ,Memory Hardware Initialization Status 22" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 21. " MIDONE21 ,Memory Hardware Initialization Status 21" "Not completed,Completed"
|
|
eventfld.long 0x00 20. " MIDONE20 ,Memory Hardware Initialization Status 20" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " MIDONE19 ,Memory Hardware Initialization Status 19" "Not completed,Completed"
|
|
eventfld.long 0x00 18. " MIDONE18 ,Memory Hardware Initialization Status 18" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " MIDONE17 ,Memory Hardware Initialization Status 17" "Not completed,Completed"
|
|
eventfld.long 0x00 16. " MIDONE16 ,Memory Hardware Initialization Status 16" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 15. " MIDONE15 ,Memory Hardware Initialization Status 15" "Not completed,Completed"
|
|
eventfld.long 0x00 14. " MIDONE14 ,Memory Hardware Initialization Status 14" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 13. " MIDONE13 ,Memory Hardware Initialization Status 13" "Not completed,Completed"
|
|
eventfld.long 0x00 12. " MIDONE12 ,Memory Hardware Initialization Status 12" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MIDONE11 ,Memory Hardware Initialization Status 11" "Not completed,Completed"
|
|
eventfld.long 0x00 10. " MIDONE10 ,Memory Hardware Initialization Status 10" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 9. " MIDONE9 ,Memory Hardware Initialization Status 9" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " MIDONE8 ,Memory Hardware Initialization Status 8" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MIDONE7 ,Memory Hardware Initialization Status 7" "Not completed,Completed"
|
|
eventfld.long 0x00 6. " MIDONE6 ,Memory Hardware Initialization Status 6" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " MIDONE5 ,Memory Hardware Initialization Status 5" "Not completed,Completed"
|
|
eventfld.long 0x00 4. " MIDONE4 ,Memory Hardware Initialization Status 4" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MIDONE3 ,Memory Hardware Initialization Status 3" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " MIDONE2 ,Memory Hardware Initialization Status 2" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MIDONE1 ,Memory Hardware Initialization Status 1" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " MIDONE0 ,Memory Hardware Initialization Status 0" "Not completed,Completed"
|
|
width 13.
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PLLCTL1,PLL Control Register 1"
|
|
bitfld.long 0x00 31. " ROS ,Reset on PLL Cycle Slip" "No reset,Reset"
|
|
bitfld.long 0x00 29.--30. " MASK_SLIP ,Mask detection of PLL slip" "Enabled,Enabled,Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset"
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PLLCTL2,PLL Control Register 2"
|
|
bitfld.long 0x00 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 22.--30. 1. " SPREADINGRATE ,Spreadingrate"
|
|
hexmask.long.word 0x00 12.--20. 1. " MULMOD ,Multiplier Correction when Frequency Modulation is enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
hexmask.long.word 0x00 0.--8. 1. " SPR_AMOUNT ,Spreading Amount"
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x0 "DIEIDL,Die Identification Register Lower Word"
|
|
hexmask.long.word 0x00 22.--31. 1. " LOT ,Lower 10 bits of the device lot number"
|
|
bitfld.long 0x00 16.--21. " WAFER ,Wafer number of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " Y_WAFER ,Y wafer coordinate of the device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " X_WAFER ,X wafer coordinate of the device"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DIEIDH,Die Identification Register Upper Word"
|
|
hexmask.long.word 0x00 0.--13. 1. " LOT ,Upper 14 bits of the device lot number"
|
|
width 13.
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register"
|
|
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "<= 20MHz,> 20MHz & <= 80MHz"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--12. " HFTRIM[4-0] ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100.00%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
|
|
bitfld.long 0x00 0.--4. " LFTRIM[4-0] ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100.00%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
|
|
else
|
|
bitfld.long 0x00 8.--11. " HFTRIM[3-0] ,High frequency oscillator trim value" "29.52%,38.85%,47.99%,57.02%,65.92%,74.55%,83.17%,91.75%,100.00%,108.17%,116.41%,124.42%,132.24%,140.15%,148.02%,155.50%"
|
|
bitfld.long 0x00 0.--3. " LFTRIM[3-0] ,Low frequency oscillator trim value" "20.67%,30.84%,40.93%,50.97%,60.86%,70.75%,80.61%,90.23%,100.00%,109.51%,119.01%,128.62%,138.03%,147.32%,156.63%,165.90%"
|
|
endif
|
|
width 13.
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "CLKTEST,Clock Test Register"
|
|
bitfld.long 0x00 26. " ALTLIMPCLOCKENABLE ,Alternate Limp Clock Enable" "10-MHz LPO,ALTLIMPCLOCK"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RANGEDETCTRL ,Range Detection Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RANGEDETENSSEL ,Range Detection Enable Select" "Hardware,CLKTEST[RANGEDETCTRL]"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CLK_TEST_EN[3:0] ,Clock Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT"||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
elif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
elif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Reserved,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
else
|
|
bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 4/pin,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SEL_ECP_PIN[3:0] ,Clock at ECP Pin Select" "Oscillator,PLL,Reserved,EXTCLKIN1,LPO low,LPO high,Secondary PLL,EXCLKIN2,GCLK,RTI Base,Reserved,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HD Pump Oscillator"
|
|
width 13.
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "DFTCTRLREG,DFT Control Register"
|
|
bitfld.long 0x00 12.--13. " DFTWRITE ,DFT Logic Access Mode" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast"
|
|
bitfld.long 0x00 8.--9. " DFTREAD ,DFT Logic Access" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "DFTCTRLREG2,DFT Control Register"
|
|
bitfld.long 0x00 31. " IMPDF[27] ,DFT Implementation Defined Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IMPDF[26] ,DFT Implementation Defined Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IMPDF[25] ,DFT Implementation Defined Bit[25]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IMPDF[24] ,DFT Implementation Defined Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IMPDF[23] ,DFT Implementation Defined Bit[23]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " IMPDF[22] ,DFT Implementation Defined Bit[22]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IMPDF[21] ,DFT Implementation Defined Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IMPDF[20] ,DFT Implementation Defined Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IMPDF[19] ,DFT Implementation Defined Bit[19]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IMPDF[18] ,DFT Implementation Defined Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " IMPDF[17] ,DFT Implementation Defined Bit[17]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IMPDF[16] ,DFT Implementation Defined Bit[16]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IMPDF[15] ,DFT Implementation Defined Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IMPDF[14] ,DFT Implementation Defined Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IMPDF[13] ,DFT Implementation Defined Bit[13]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IMPDF[12] ,DFT Implementation Defined Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IMPDF[11] ,DFT Implementation Defined Bit[11]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IMPDF[10] ,DFT Implementation Defined Bit[10]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IMPDF[9] ,DFT Implementation Defined Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IMPDF[8] ,DFT Implementation Defined Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IMPDF[7] ,DFT Implementation Defined Bit[7]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IMPDF[6] ,DFT Implementation Defined Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IMPDF[5] ,DFT Implementation Defined Bit[5]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IMPDF[4] ,DFT Implementation Defined Bit[4]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IMPDF[3] ,DFT Implementation Defined Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IMPDF[2] ,DFT Implementation Defined Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IMPDF[1] ,DFT Implementation Defined Bit[1]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IMPDF[0] ,DFT Implementation Defined Bit[0]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key (Internal TI Use Only)" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
width 13.
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "GPREG1,General Purpose Register 1"
|
|
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PLL1_RFSLIP_FILTER_KEY ,Configures the system response when a FBSLIP is indicated by the PLL macro" "Reserved,Reserved,Reserved,Reserved,Reserved,Bypassed,Reserved,Reserved,Reserved,Reserved,One-stage synchronization,Reserved,Reserved,Reserved,Reserved,Two-stage synchronization"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[15] ,EMI mode for RTP enable" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " OUTPUT_BUFFER_LOW_EMI_MODE[14] ,EMI mode for ADEVT enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[13] ,EMI mode for nERROR enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUTPUT_BUFFER_LOW_EMI_MODE[12] ,EMI mode for TEST enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OUTPUT_BUFFER_LOW_EMI_MODE[11] ,EMI mode for RTCK enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUTPUT_BUFFER_LOW_EMI_MODE[10] ,EMI mode for TD0 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OUTPUT_BUFFER_LOW_EMI_MODE[9] ,EMI mode for TDI enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUTPUT_BUFFER_LOW_EMI_MODE[8] ,EMI mode for TMS enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUTPUT_BUFFER_LOW_EMI_MODE[7] ,EMI mode for ETM enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OUTPUT_BUFFER_LOW_EMI_MODE[6] ,EMI mode for EMIF enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OUTPUT_BUFFER_LOW_EMI_MODE[5] ,EMI mode for FlexRay enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUTPUT_BUFFER_LOW_EMI_MODE[4] ,EMI mode for MiBSPI5 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OUTPUT_BUFFER_LOW_EMI_MODE[3] ,EMI mode for SPI4 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OUTPUT_BUFFER_LOW_EMI_MODE[2] ,EMI mode for MiBSPI3 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUTPUT_BUFFER_LOW_EMI_MODE[1] ,EMI mode for SPI2 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OUTPUT_BUFFER_LOW_EMI_MODE[0] ,EMI mode for MiBSPI1 enable" "Enabled,Disabled"
|
|
endif
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x0 "IMPFASTS,Imprecise Fault Status Register"
|
|
in
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "IMPFTADD,Imprecise Fault Write Address Register"
|
|
width 14.
|
|
tree "System Software Interrupt Request Registers"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "SSIR1,System Software Interrupt Request 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY1[7:0] ,System Software Interrupt Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA1[7:0] ,System Software Interrupt Data"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "SSIR2,System Software Interrupt Request 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY2[7:0] ,System Software Interrupt 2 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA2[7:0] ,System Software Interrupt 2 Data"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "SSIR3,System Software Interrupt Request 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY3[7:0] ,System Software Interrupt 3 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA3[7:0] ,System Software Interrupt 3 Data"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "SSIR4,System Software Interrupt Request 4 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY4[7:0] ,System Software Interrupt 3 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA4[7:0] ,System Software Interrupt 4 Data"
|
|
tree.end
|
|
width 10.
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "RAMGCR,RAM Control Register"
|
|
bitfld.long 0x00 16.--19. " RAM_DFT_EN[3:0] ,Functional Mode RAM DFT Port Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WST_AENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WST_DENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMMCR1,Bus Matrix Module Control Register1"
|
|
bitfld.long 0x00 0.--3. " MEMSW[3:0] ,Memory Swap Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Swapped,Reserved,Reserved,Reserved,Reserved,Default,?..."
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM42L432"&&cpu()!="RM48L550-ZWT"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "BMMCR2,Bus Matrix Module Control Register2"
|
|
endif
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "CPURSTCR,CPU Reset Control Register"
|
|
bitfld.long 0x00 0. " CPU_RESET ,Cpu reset" "No reset,Reset"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "CLKCNTL,Clock Control Register"
|
|
bitfld.long 0x00 24.--27. " VCLKR2[3:0] ,VBUS Clock 2 Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
bitfld.long 0x00 16.--19. " VCLKR[3:0] ,VBUS Clock Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
bitfld.long 0x00 8. " PENA ,Peripheral Enable" "Reset,No reset"
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "ECPCNTRL,ECP Control Register"
|
|
bitfld.long 0x00 24. " ECPSSEL ,ECP Source Clock Select for ECP Module" "Oscillator,VCLK"
|
|
bitfld.long 0x00 23. " ECPCOS ,ECP Continue on Suspend" "Suspended,Continue"
|
|
bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP Input Clock Source" "Tied Low,HCLK,External,Tied Low"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ECPDIV[15:0] ,ECP Divider Value"
|
|
group.long 0xDC++0x3
|
|
line.long 0x0 "DEVCR1,DEV Parity Control Register1"
|
|
bitfld.long 0x00 0.--3. " DEVPARSEL ,Device Parity Select Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Even,Reserved,Reserved,Reserved,Reserved,Odd,?..."
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "SYSECR,System Exception Control Register"
|
|
bitfld.long 0x00 14.--15. " RESET[1:0] ,Software Reset" "Reset,No reset,Reset,Reset"
|
|
width 10.
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "SYSESR,System Exception Status Register"
|
|
eventfld.long 0x00 15. " PORST ,Power-Up Reset" "No reset,Reset"
|
|
eventfld.long 0x00 14. " OSCRST ,Oscillator Failure/PLL Cycle Slip Reset" "No reset,Reset"
|
|
eventfld.long 0x00 13. " WDRST ,Watchdog Reset Flag" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CPURST ,CPU Reset Flag" "No reset,Reset"
|
|
eventfld.long 0x00 4. " SWRST ,Software Reset Flag" "No reset,Reset"
|
|
eventfld.long 0x00 3. " EXTRST ,External Reset Flag" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MPMODE ,This indicates the current memory protection unit (MPU) mode" "Disabled,Enabled"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "SYSTASR,System Test Abort Status Register"
|
|
bitfld.long 0x00 0.--4. " EFUSE_ABORT[4:0] ,Test Abort Status Flag" "Read: Last operation,Read: Controller times out,Read: Autoload/Not find FuseROM,Read: Autoload/Scan chain,Read: Autoload/Not completed operation,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Write: Cleared"
|
|
width 10.
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "GLBSTAT,Global Status Register"
|
|
eventfld.long 0x00 9. " FBSLIP ,Over Cycle Slip Detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RFSLIP ,Under Cycle Slip Detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " OSCFAIL ,Oscillator Fail Flag" "Not failed,Failed"
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "DEVID,Device Identification Register"
|
|
bitfld.long 0x00 31. " CP15 ,CP15 CPU" "CP15,No CP15"
|
|
hexmask.long.word 0x00 17.--30. 1. " UNIQUE_ID ,Device ID"
|
|
bitfld.long 0x00 13.--16. " TECH ,Device Manufacture Process Technology" "C05,F05,C035,F035,C021,F021,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " I/O_VOLTAGE ,Input/Output Voltage" "3.3 V,5 V"
|
|
bitfld.long 0x00 11. " PERIPHERAL_PARITY ,Peripheral Parity" "No parity,Parity"
|
|
bitfld.long 0x00 9.--10. " FLASH_ECC ,Program Memory Parity Present" "Not protected,Single bit,ECC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " RAM_RECC ,RAM ECC" "No ECC,ECC"
|
|
hexmask.long.byte 0x00 3.--7. 1. " VERSION ,Version"
|
|
hexmask.long.byte 0x00 0.--2. 1. " PLATFORM_ID ,The TMS570Px Platform ID"
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x0 "SSIVEC,Software Interrupt Vector Register"
|
|
in
|
|
width 10.
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "SSIF,System Software Interrupt Flag Register"
|
|
eventfld.long 0x00 3. " SSI_FLAG4 ,System Software Interrupt Flag 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SSI_FLAG43 ,System Software Interrupt Flag 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SSI_FLAG42 ,System Software Interrupt Flag 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SSI_FLAG41 ,System Software Interrupt Flag 1" "No interrupt,Interrupt"
|
|
width 11.
|
|
tree.end
|
|
tree "SYS2"
|
|
base ad:0xFFFFE100
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PLLCTL3,PLL Control Register 3"
|
|
bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL#2 output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLL_MUL2 ,PLL multiplication"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STCLKDIV,CPU Logic BIST Clock Divider"
|
|
bitfld.long 0x00 24.--26. " CLKDIV ,Clock divider/prescaler for CPU clock during logic BIST" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
sif !cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L950-PGE")&&!cpuis("RM48L950-ZWT")&&!cpuis("RM48L940-ZWT")&&!cpuis("RM48L940-PGE")&&!cpuis("RM48L930-ZWT")&&!cpuis("RM48L930-PGE")&&!cpuis("RM48L750-ZWT")&&!cpuis("RM48L750-PGE")&&!cpuis("RM48L740-ZWT")&&!cpuis("RM48L740-PGE")&&!cpuis("RM48L730-ZWT")&&!cpuis("RM48L730-PGE")&&!cpuis("RM48L550-PGE")&&!cpuis("RM48L540-ZWT")&&!cpuis("RM48L540-PGE")&&!cpuis("RM48L530-ZWT")&&!cpuis("RM48L530-PGE")&&!cpuis("RM48L550-ZWT")&&!cpuis("RM42L432")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP")
|
|
sif cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECPCNTL,ECP Control Register 1"
|
|
bitfld.long 0x00 24. " ECPSSEL ,Allows the selection between VCLK and OSCIN as the clock source for ECLK2" "VCLK,OSCIN"
|
|
bitfld.long 0x00 23. " ECPCOS ,ECP continue on suspend" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP input clock source" "Tied Low,HCLK,External clock,Tied Low"
|
|
hexmask.long.word 0x00 0.--15. 1. " ECPDIV ,ECP divider value"
|
|
else
|
|
group.long 0x0C++0xB
|
|
line.long 0x00 "CLKHB_GLBREG,Clock Hibernate Mode Global Enable Register"
|
|
line.long 0x04 "CLKHB_RTIDREG,Clocked Hibernate RTI Domain Control Register"
|
|
line.long 0x08 "HBCD_STAT,Hibernate Clock Domain Status Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKTRMI1,Clock Trim 1 Register"
|
|
endif
|
|
endif
|
|
sif !cpuis("TMS570LS0232")
|
|
sif (cpu()!="RM42L432"||cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLK2CNTRL,Clock 2 Control Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x00 8.--11. " VCLK4R ,VBUS clock4 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
else
|
|
bitfld.long 0x00 0.--3. " VCLK3R ,VBUS clock3 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "VCLKACON1,Peripheral Asynchronous Clock Configuration 1 Register"
|
|
bitfld.long 0x00 24.--26. " VCLKA4R ,Clock divider for the VCLKA4 source" "VCLKA4,VCLKA4/2,VCLKA4/3,VCLKA4/4,VCLKA4/5,VCLKA4/6,VCLKA4/7,VCLKA4/8"
|
|
bitfld.long 0x00 20. " VCLKA4_DIV_CDDIS ,Disable the VCLKA4 divider output" "No,Yes"
|
|
newline
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
newline
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--10. " VCLKA3R ,Clock divider for the VCLKA3 source" "VCLKA3,VCLKA3/2,VCLKA3/3,VCLKA3/4,VCLKA3/5,VCLKA3/6,VCLKA3/7,VCLKA3/8"
|
|
bitfld.long 0x00 4. " VCLKA3_DIV_CDDIS ,Disable the VCLKA3 divider output" "No,Yes"
|
|
newline
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLKSLIP,Clock Slip Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "Disabled,Every slip recognized,At least 2 HF LPO cycles,At least 3 HF LPO cycles,At least 4 HF LPO cycles,At least 5 HF LPO cycles,At least 6 HF LPO cycles,At least 7 HF LPO cycles,At least 8 HF LPO cycles,At least 9 HF LPO cycles,At least 10 HF LPO cycles,At least 11 HF LPO cycles,At least 12 HF LPO cycles,At least 13 HF LPO cycles,At least 14 HF LPO cycles,At least 15 HF LPO cycles,At least 16 HF LPO cycles,At least 17 HF LPO cycles,At least 18 HF LPO cycles,At least 19 HF LPO cycles,At least 20 HF LPO cycles,At least 21 HF LPO cycles,At least 22 HF LPO cycles,At least 23 HF LPO cycles,At least 24 HF LPO cycles,At least 25 HF LPO cycles,At least 26 HF LPO cycles,At least 27 HF LPO cycles,At least 28 HF LPO cycles,At least 29 HF LPO cycles,At least 30 HF LPO cycles,At least 31 HF LPO cycles,At least 32 HF LPO cycles,At least 33 HF LPO cycles,At least 34 HF LPO cycles,At least 35 HF LPO cycles,At least 36 HF LPO cycles,At least 37 HF LPO cycles,At least 38 HF LPO cycles,At least 39 HF LPO cycles,At least 40 HF LPO cycles,At least 41 HF LPO cycles,At least 42 HF LPO cycles,At least 43 HF LPO cycles,At least 44 HF LPO cycles,At least 45 HF LPO cycles,At least 46 HF LPO cycles,At least 47 HF LPO cycles,At least 48 HF LPO cycles,At least 49 HF LPO cycles,At least 50 HF LPO cycles,At least 51 HF LPO cycles,At least 52 HF LPO cycles,At least 53 HF LPO cycles,At least 54 HF LPO cycles,At least 55 HF LPO cycles,At least 56 HF LPO cycles,At least 57 HF LPO cycles,At least 58 HF LPO cycles,At least 59 HF LPO cycles,At least 60 HF LPO cycles,At least 61 HF LPO cycles,At least 62 HF LPO cycles,At least 63 HF LPO cycles"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,Enable the PLL filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "EFC_CTLREG,EFUSE Controller Control Register"
|
|
bitfld.long 0x00 0.--3. " EFC_INSTR_WEN ,Enable user write of 4 EFUSE controller instructions" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
rgroup.long 0xF0++0x0F
|
|
line.long 0x00 "DIEIDL_REG0,Die Identification Register Lower Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " WAFER# ,Wafer number of the device"
|
|
hexmask.long.word 0x00 12.--23. 1. " Y_WAFER_COORDINATE ,Y wafer coordinate of the device"
|
|
hexmask.long.word 0x00 0.--11. 1. " X_WAFER_COORDINATE ,X wafer coordinate of the device"
|
|
endif
|
|
line.long 0x04 "DIEIDH_REG1,Die Identification Register Upper Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " LOT# ,Device lot number"
|
|
endif
|
|
line.long 0x08 "DIEIDH_REG2,Die Identification Register Lower Word"
|
|
line.long 0x0C "DIEIDH_REG3,Die Identification Register Upper Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "VIM (Vectored Interrupt Manager)"
|
|
tree "VIM"
|
|
base ad:0xFFFFFE00
|
|
width 10.
|
|
tree "VIM Offset Vector Registers"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IRQINDEX,IRQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
|
|
line.long 0x04 "FIQINDEX,FIQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FIQINDEX ,FIQ index offset vector"
|
|
tree.end
|
|
newline
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "FIRQPR0,Program Control 0 Register"
|
|
bitfld.long 0x00 31. " FIRQPR_31 ,FIQ/IRQ program control for channel 31" "IRQ,FIQ"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 30. " FIRQPR_30 ,FIQ/IRQ program control for channel 30" "IRQ,FIQ"
|
|
endif
|
|
bitfld.long 0x00 29. " FIRQPR_29 ,FIQ/IRQ program control for channel 29" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " FIRQPR_28 ,FIQ/IRQ program control for channel 28" "IRQ,FIQ"
|
|
bitfld.long 0x00 27. " FIRQPR_27 ,FIQ/IRQ program control for channel 27" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 26. " FIRQPR_26 ,FIQ/IRQ program control for channel 26" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " FIRQPR_25 ,FIQ/IRQ program control for channel 25" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " FIRQPR_24 ,FIQ/IRQ program control for channel 24" "IRQ,FIQ"
|
|
bitfld.long 0x00 23. " FIRQPR_23 ,FIQ/IRQ program control for channel 23" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 22. " FIRQPR_22 ,FIQ/IRQ program control for channel 22" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " FIRQPR_21 ,FIQ/IRQ program control for channel 21" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " FIRQPR_20 ,FIQ/IRQ program control for channel 20" "IRQ,FIQ"
|
|
bitfld.long 0x00 19. " FIRQPR_19 ,FIQ/IRQ program control for channel 19" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 18. " FIRQPR_18 ,FIQ/IRQ program control for channel 18" "IRQ,FIQ"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 17. " FIRQPR_17 ,FIQ/IRQ program control for channel 17" "IRQ,FIQ"
|
|
endif
|
|
bitfld.long 0x00 16. " FIRQPR_16 ,FIQ/IRQ program control for channel 16" "IRQ,FIQ"
|
|
bitfld.long 0x00 15. " FIRQPR_15 ,FIQ/IRQ program control for channel 15" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " FIRQPR_14 ,FIQ/IRQ program control for channel 14" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 13. " FIRQPR_13 ,FIQ/IRQ program control for channel 13" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " FIRQPR_12 ,FIQ/IRQ program control for channel 12" "IRQ,FIQ"
|
|
bitfld.long 0x00 11. " FIRQPR_11 ,FIQ/IRQ program control for channel 11" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " FIRQPR_10 ,FIQ/IRQ program control for channel 10" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 9. " FIRQPR_9 ,FIQ/IRQ program control for channel 9" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " FIRQPR_8 ,FIQ/IRQ program control for channel 8" "IRQ,FIQ"
|
|
bitfld.long 0x00 7. " FIRQPR_7 ,FIQ/IRQ program control for channel 7" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " FIRQPR_6 ,FIQ/IRQ program control for channel 6" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 5. " FIRQPR_5 ,FIQ/IRQ program control for channel 5" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " FIRQPR_4 ,FIQ/IRQ program control for channel 4" "IRQ,FIQ"
|
|
bitfld.long 0x00 3. " FIRQPR_3 ,FIQ/IRQ program control for channel 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " FIRQPR_2 ,FIQ/IRQ program control for channel 2" "IRQ,FIQ"
|
|
line.long 0x04 "FIRQPR1,Program Control 1 Register"
|
|
bitfld.long 0x04 31. " FIRQPR_63 ,FIQ/IRQ program control for channel 63" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 30. " FIRQPR_62 ,FIQ/IRQ program control for channel 62" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " FIRQPR_61 ,FIQ/IRQ program control for channel 61" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " FIRQPR_60 ,FIQ/IRQ program control for channel 60" "IRQ,FIQ"
|
|
bitfld.long 0x04 27. " FIRQPR_59 ,FIQ/IRQ program control for channel 59" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 26. " FIRQPR_58 ,FIQ/IRQ program control for channel 58" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " FIRQPR_57 ,FIQ/IRQ program control for channel 57" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " FIRQPR_56 ,FIQ/IRQ program control for channel 56" "IRQ,FIQ"
|
|
bitfld.long 0x04 23. " FIRQPR_55 ,FIQ/IRQ program control for channel 55" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 22. " FIRQPR_54 ,FIQ/IRQ program control for channel 54" "IRQ,FIQ"
|
|
bitfld.long 0x04 21. " FIRQPR_53 ,FIQ/IRQ program control for channel 53" "IRQ,FIQ"
|
|
bitfld.long 0x04 20. " FIRQPR_52 ,FIQ/IRQ program control for channel 52" "IRQ,FIQ"
|
|
bitfld.long 0x04 19. " FIRQPR_51 ,FIQ/IRQ program control for channel 51" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 18. " FIRQPR_50 ,FIQ/IRQ program control for channel 50" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " FIRQPR_49 ,FIQ/IRQ program control for channel 49" "IRQ,FIQ"
|
|
bitfld.long 0x04 16. " FIRQPR_48 ,FIQ/IRQ program control for channel 48" "IRQ,FIQ"
|
|
bitfld.long 0x04 15. " FIRQPR_47 ,FIQ/IRQ program control for channel 47" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 14. " FIRQPR_46 ,FIQ/IRQ program control for channel 46" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " FIRQPR_45 ,FIQ/IRQ program control for channel 45" "IRQ,FIQ"
|
|
bitfld.long 0x04 12. " FIRQPR_44 ,FIQ/IRQ program control for channel 44" "IRQ,FIQ"
|
|
bitfld.long 0x04 10. " FIRQPR_42 ,FIQ/IRQ program control for channel 42" "IRQ,FIQ"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 9. " FIRQPR_41 ,FIQ/IRQ program control for channel 41" "IRQ,FIQ"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " FIRQPR_40 ,FIQ/IRQ program control for channel 40" "IRQ,FIQ"
|
|
bitfld.long 0x04 7. " FIRQPR_39 ,FIQ/IRQ program control for channel 39" "IRQ,FIQ"
|
|
bitfld.long 0x04 6. " FIRQPR_38 ,FIQ/IRQ program control for channel 38" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " FIRQPR_37 ,FIQ/IRQ program control for channel 37" "IRQ,FIQ"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 4. " FIRQPR_36 ,FIQ/IRQ program control for channel 36" "IRQ,FIQ"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " FIRQPR_35 ,FIQ/IRQ program control for channel 35" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " FIRQPR_34 ,FIQ/IRQ program control for channel 34" "IRQ,FIQ"
|
|
bitfld.long 0x04 1. " FIRQPR_33 ,FIQ/IRQ program control for channel 33" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 0. " FIRQPR_32 ,FIQ/IRQ program control for channel 32" "IRQ,FIQ"
|
|
line.long 0x08 "FIRQPR2,Program Control 2 Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 31. " FIRQPR_95 ,FIQ/IRQ program control for channel 95" "IRQ,FIQ"
|
|
bitfld.long 0x08 30. " FIRQPR_94 ,FIQ/IRQ program control for channel 94" "IRQ,FIQ"
|
|
bitfld.long 0x08 29. " FIRQPR_93 ,FIQ/IRQ program control for channel 93" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 28. " FIRQPR_92 ,FIQ/IRQ program control for channel 92" "IRQ,FIQ"
|
|
bitfld.long 0x08 27. " FIRQPR_91 ,FIQ/IRQ program control for channel 91" "IRQ,FIQ"
|
|
bitfld.long 0x08 26. " FIRQPR_90 ,FIQ/IRQ program control for channel 90" "IRQ,FIQ"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 25. " FIRQPR_89 ,FIQ/IRQ program control for channel 89" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " FIRQPR_88 ,FIQ/IRQ program control for channel 88" "IRQ,FIQ"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 23. " FIRQPR_87 ,FIQ/IRQ program control for channel 87" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " FIRQPR_86 ,FIQ/IRQ program control for channel 86" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 21. " FIRQPR_85 ,FIQ/IRQ program control for channel 85" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " FIRQPR_84 ,FIQ/IRQ program control for channel 84" "IRQ,FIQ"
|
|
endif
|
|
bitfld.long 0x08 19. " FIRQPR_83 ,FIQ/IRQ program control for channel 83" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " FIRQPR_82 ,FIQ/IRQ program control for channel 82" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 17. " FIRQPR_81 ,FIQ/IRQ program control for channel 81" "IRQ,FIQ"
|
|
bitfld.long 0x08 16. " FIRQPR_80 ,FIQ/IRQ program control for channel 80" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " FIRQPR_79 ,FIQ/IRQ program control for channel 79" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " FIRQPR_78 ,FIQ/IRQ program control for channel 78" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 13. " FIRQPR_77 ,FIQ/IRQ program control for channel 77" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " FIRQPR_76 ,FIQ/IRQ program control for channel 76" "IRQ,FIQ"
|
|
bitfld.long 0x08 11. " FIRQPR_75 ,FIQ/IRQ program control for channel 75" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " FIRQPR_74 ,FIQ/IRQ program control for channel 74" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 9. " FIRQPR_73 ,FIQ/IRQ program control for channel 73" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " FIRQPR_72 ,FIQ/IRQ program control for channel 72" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " FIRQPR_71 ,FIQ/IRQ program control for channel 71" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " FIRQPR_70 ,FIQ/IRQ program control for channel 70" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 5. " FIRQPR_69 ,FIQ/IRQ program control for channel 69" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " FIRQPR_68 ,FIQ/IRQ program control for channel 68" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " FIRQPR_67 ,FIQ/IRQ program control for channel 67" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " FIRQPR_66 ,FIQ/IRQ program control for channel 66" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 1. " FIRQPR_65 ,FIQ/IRQ program control for channel 65" "IRQ,FIQ"
|
|
bitfld.long 0x08 0. " FIRQPR_64 ,FIQ/IRQ program control for channel 64" "IRQ,FIQ"
|
|
tree "VIM Pending Interrupt Read Location Registers"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTREQ0,Pending Interrupt Read Location 0"
|
|
eventfld.long 0x00 31. " INTREQ_31 ,Interrupt pending 31" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 30. " INTREQ_30 ,Interrupt pending 30" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " INTREQ_29 ,Interrupt pending 29" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " INTREQ_28 ,Interrupt pending 28" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " INTREQ_27 ,Interrupt pending 27" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 26. " INTREQ_26 ,Interrupt pending 26" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " INTREQ_25 ,Interrupt pending 25" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " INTREQ_24 ,Interrupt pending 24" "Not occurred,Occurred"
|
|
eventfld.long 0x00 23. " INTREQ_23 ,Interrupt pending 23" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 22. " INTREQ_22 ,Interrupt pending 22" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " INTREQ_21 ,Interrupt pending 21" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " INTREQ_20 ,Interrupt pending 20" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " INTREQ_19 ,Interrupt pending 19" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 18. " INTREQ_18 ,Interrupt pending 18" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 17. " INTREQ_17 ,Interrupt pending 17" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " INTREQ_16 ,Interrupt pending 16" "Not occurred,Occurred"
|
|
eventfld.long 0x00 15. " INTREQ_15 ,Interrupt pending 15" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " INTREQ_14 ,Interrupt pending 14" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 13. " INTREQ_13 ,Interrupt pending 13" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " INTREQ_12 ,Interrupt pending 12" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " INTREQ_11 ,Interrupt pending 11" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " INTREQ_10 ,Interrupt pending 10" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 9. " INTREQ_9 ,Interrupt pending 9" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " INTREQ_8 ,Interrupt pending 8" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " INTREQ_7 ,Interrupt pending 7" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " INTREQ_6 ,Interrupt pending 6" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 5. " INTREQ_5 ,Interrupt pending 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " INTREQ_4 ,Interrupt pending 4" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " INTREQ_3 ,Interrupt pending 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " INTREQ_2 ,Interrupt pending 2" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 1. " INTREQ_1 ,Interrupt pending 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " INTREQ_0 ,Interrupt pending 0" "Not occurred,Occurred"
|
|
line.long 0x04 "INTREQ1,Pending Interrupt Read Location 1"
|
|
eventfld.long 0x04 31. " INTREQ_63 ,Interrupt pending 63" "Not occurred,Occurred"
|
|
eventfld.long 0x04 30. " INTREQ_62 ,Interrupt pending 62" "Not occurred,Occurred"
|
|
eventfld.long 0x04 29. " INTREQ_61 ,Interrupt pending 61" "Not occurred,Occurred"
|
|
eventfld.long 0x04 28. " INTREQ_60 ,Interrupt pending 60" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 27. " INTREQ_59 ,Interrupt pending 59" "Not occurred,Occurred"
|
|
eventfld.long 0x04 26. " INTREQ_58 ,Interrupt pending 58" "Not occurred,Occurred"
|
|
eventfld.long 0x04 25. " INTREQ_57 ,Interrupt pending 57" "Not occurred,Occurred"
|
|
eventfld.long 0x04 24. " INTREQ_56 ,Interrupt pending 56" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 23. " INTREQ_55 ,Interrupt pending 55" "Not occurred,Occurred"
|
|
eventfld.long 0x04 22. " INTREQ_54 ,Interrupt pending 54" "Not occurred,Occurred"
|
|
eventfld.long 0x04 21. " INTREQ_53 ,Interrupt pending 53" "Not occurred,Occurred"
|
|
eventfld.long 0x04 20. " INTREQ_52 ,Interrupt pending 52" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 19. " INTREQ_51 ,Interrupt pending 51" "Not occurred,Occurred"
|
|
eventfld.long 0x04 18. " INTREQ_50 ,Interrupt pending 50" "Not occurred,Occurred"
|
|
eventfld.long 0x04 17. " INTREQ_49 ,Interrupt pending 49" "Not occurred,Occurred"
|
|
eventfld.long 0x04 16. " INTREQ_48 ,Interrupt pending 48" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 15. " INTREQ_47 ,Interrupt pending 47" "Not occurred,Occurred"
|
|
eventfld.long 0x04 14. " INTREQ_46 ,Interrupt pending 46" "Not occurred,Occurred"
|
|
eventfld.long 0x04 13. " INTREQ_45 ,Interrupt pending 45" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " INTREQ_44 ,Interrupt pending 44" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 11. " INTREQ_43 ,Interrupt pending 43" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 10. " INTREQ_42 ,Interrupt pending 42" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 9. " INTREQ_41 ,Interrupt pending 41" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " INTREQ_40 ,Interrupt pending 40" "Not occurred,Occurred"
|
|
eventfld.long 0x04 7. " INTREQ_39 ,Interrupt pending 39" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " INTREQ_38 ,Interrupt pending 38" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 5. " INTREQ_37 ,Interrupt pending 37" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 4. " INTREQ_36 ,Interrupt pending 36" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " INTREQ_35 ,Interrupt pending 35" "Not occurred,Occurred"
|
|
eventfld.long 0x04 2. " INTREQ_34 ,Interrupt pending 34" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " INTREQ_33 ,Interrupt pending 33" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 0. " INTREQ_32 ,Interrupt pending 32" "Not occurred,Occurred"
|
|
line.long 0x08 "INTREQ2,Pending Interrupt Read Location 2"
|
|
eventfld.long 0x08 31. " INTREQ_95 ,Interrupt pending 95" "Not occurred,Occurred"
|
|
eventfld.long 0x08 30. " INTREQ_94 ,Interrupt pending 94" "Not occurred,Occurred"
|
|
eventfld.long 0x08 29. " INTREQ_93 ,Interrupt pending 93" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 28. " INTREQ_92 ,Interrupt pending 92" "Not occurred,Occurred"
|
|
eventfld.long 0x08 27. " INTREQ_91 ,Interrupt pending 91" "Not occurred,Occurred"
|
|
eventfld.long 0x08 26. " INTREQ_90 ,Interrupt pending 90" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 25. " INTREQ_89 ,Interrupt pending 89" "Not occurred,Occurred"
|
|
eventfld.long 0x08 24. " INTREQ_88 ,Interrupt pending 88" "Not occurred,Occurred"
|
|
eventfld.long 0x08 23. " INTREQ_87 ,Interrupt pending 87" "Not occurred,Occurred"
|
|
eventfld.long 0x08 22. " INTREQ_86 ,Interrupt pending 86" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 21. " INTREQ_85 ,Interrupt pending 85" "Not occurred,Occurred"
|
|
eventfld.long 0x08 20. " INTREQ_84 ,Interrupt pending 84" "Not occurred,Occurred"
|
|
eventfld.long 0x08 19. " INTREQ_83 ,Interrupt pending 83" "Not occurred,Occurred"
|
|
eventfld.long 0x08 18. " INTREQ_82 ,Interrupt pending 82" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 17. " INTREQ_81 ,Interrupt pending 81" "Not occurred,Occurred"
|
|
eventfld.long 0x08 16. " INTREQ_80 ,Interrupt pending 80" "Not occurred,Occurred"
|
|
eventfld.long 0x08 15. " INTREQ_79 ,Interrupt pending 79" "Not occurred,Occurred"
|
|
eventfld.long 0x08 14. " INTREQ_78 ,Interrupt pending 78" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 13. " INTREQ_77 ,Interrupt pending 77" "Not occurred,Occurred"
|
|
eventfld.long 0x08 12. " INTREQ_76 ,Interrupt pending 76" "Not occurred,Occurred"
|
|
eventfld.long 0x08 11. " INTREQ_75 ,Interrupt pending 75" "Not occurred,Occurred"
|
|
eventfld.long 0x08 10. " INTREQ_74 ,Interrupt pending 74" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 9. " INTREQ_73 ,Interrupt pending 73" "Not occurred,Occurred"
|
|
eventfld.long 0x08 8. " INTREQ_72 ,Interrupt pending 72" "Not occurred,Occurred"
|
|
eventfld.long 0x08 7. " INTREQ_71 ,Interrupt pending 71" "Not occurred,Occurred"
|
|
eventfld.long 0x08 6. " INTREQ_70 ,Interrupt pending 70" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 5. " INTREQ_69 ,Interrupt pending 69" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " INTREQ_68 ,Interrupt pending 68" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " INTREQ_67 ,Interrupt pending 67" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " INTREQ_66 ,Interrupt pending 66" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 1. " INTREQ_65 ,Interrupt pending 65" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " INTREQ_64 ,Interrupt pending 64" "Not occurred,Occurred"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INTREQ0,Pending Interrupt Read Location 0"
|
|
bitfld.long 0x00 31. " INTREQ_31 ,Interrupt pending 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTREQ_29 ,Interrupt pending 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTREQ_28 ,Interrupt pending 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " INTREQ_27 ,Interrupt pending 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. " INTREQ_26 ,Interrupt pending 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTREQ_25 ,Interrupt pending 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTREQ_24 ,Interrupt pending 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " INTREQ_23 ,Interrupt pending 23" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 22. " INTREQ_22 ,Interrupt pending 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTREQ_21 ,Interrupt pending 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTREQ_20 ,Interrupt pending 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " INTREQ_19 ,Interrupt pending 19" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 18. " INTREQ_18 ,Interrupt pending 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTREQ_16 ,Interrupt pending 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " INTREQ_15 ,Interrupt pending 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTREQ_14 ,Interrupt pending 14" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " INTREQ_13 ,Interrupt pending 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTREQ_12 ,Interrupt pending 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " INTREQ_11 ,Interrupt pending 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTREQ_10 ,Interrupt pending 10" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " INTREQ_9 ,Interrupt pending 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTREQ_8 ,Interrupt pending 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " INTREQ_7 ,Interrupt pending 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTREQ_6 ,Interrupt pending 6" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " INTREQ_5 ,Interrupt pending 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTREQ_4 ,Interrupt pending 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INTREQ_3 ,Interrupt pending 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTREQ_2 ,Interrupt pending 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " INTREQ_0 ,Interrupt pending 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTREQ1,Pending Interrupt Read Location 1"
|
|
bitfld.long 0x00 31. " INTREQ_63 ,Interrupt pending 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INTREQ_62 ,Interrupt pending 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INTREQ_61 ,Interrupt pending 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " INTREQ_60 ,Interrupt pending 60" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " INTREQ_59 ,Interrupt pending 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " INTREQ_58 ,Interrupt pending 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INTREQ_57 ,Interrupt pending 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTREQ_56 ,Interrupt pending 56" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " INTREQ_55 ,Interrupt pending 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " INTREQ_54 ,Interrupt pending 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " INTREQ_53 ,Interrupt pending 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " INTREQ_52 ,Interrupt pending 52" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " INTREQ_51 ,Interrupt pending 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTREQ_50 ,Interrupt pending 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " INTREQ_49 ,Interrupt pending 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTREQ_48 ,Interrupt pending 48" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " INTREQ_47 ,Interrupt pending 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTREQ_46 ,Interrupt pending 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTREQ_45 ,Interrupt pending 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTREQ_44 ,Interrupt pending 44" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " INTREQ_42 ,Interrupt pending 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTREQ_40 ,Interrupt pending 40" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " INTREQ_39 ,Interrupt pending 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTREQ_38 ,Interrupt pending 38" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " INTREQ_37 ,Interrupt pending 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INTREQ_35 ,Interrupt pending 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTREQ_34 ,Interrupt pending 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTREQ_33 ,Interrupt pending 33" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " INTREQ_32 ,Interrupt pending 32" "No interrupt,Interrupt"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "INTREQ2,Pending Interrupt Read Location 2"
|
|
bitfld.long 0x00 25. " INTREQ_89 ,Interrupt pending 89" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " INTREQ_88 ,Interrupt pending 88" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " INTREQ_83 ,Interrupt pending 83" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " INTREQ_82 ,Interrupt pending 82" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " INTREQ_81 ,Interrupt pending 81" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTREQ_80 ,Interrupt pending 80" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " INTREQ_79 ,Interrupt pending 79" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTREQ_78 ,Interrupt pending 78" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " INTREQ_77 ,Interrupt pending 77" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTREQ_76 ,Interrupt pending 76" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " INTREQ_75 ,Interrupt pending 75" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTREQ_74 ,Interrupt pending 74" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " INTREQ_73 ,Interrupt pending 73" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTREQ_72 ,Interrupt pending 72" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " INTREQ_71 ,Interrupt pending 71" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTREQ_70 ,Interrupt pending 70" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " INTREQ_69 ,Interrupt pending 69" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTREQ_68 ,Interrupt pending 68" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INTREQ_67 ,Interrupt pending 67" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTREQ_66 ,Interrupt pending 66" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " INTREQ_65 ,Interrupt pending 65" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTREQ_64 ,Interrupt pending 64" "No interrupt,Interrupt"
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "VIM Interrupt Mask Registers"
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "REQENASET0_SET/CLR,Interrupt Enable Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_31 ,Request enable set bit 31" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQENA_30 ,Request enable set bit 30" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_29 ,Request enable set bit 29" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_28 ,Request enable set bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_27 ,Request enable set bit 27" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQENA_26 ,Request enable set bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_25 ,Request enable set bit 25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_24 ,Request enable set bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_23 ,Request enable set bit 23" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_22 ,Request enable set bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_21 ,Request enable set bit 21" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQENA_20 ,Request enable set bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_19 ,Request enable set bit 19" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_18 ,Request enable set bit 18" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_17 ,Request enable set bit 17" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_16 ,Request enable set bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_15 ,Request enable set bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_14 ,Request enable set bit 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_13 ,Request enable set bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_12 ,Request enable set bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_11 ,Request enable set bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_10 ,Request enable set bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_9 ,Request enable set bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_8 ,Request enable set bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_7 ,Request enable set bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_6 ,Request enable set bit 6" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_5 ,Request enable set bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_4 ,Request enable set bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_3 ,Request enable set bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_2 ,Request enable set bit 2" "Disabled,Enabled"
|
|
line.long 0x04 "REQENASET1_SET/CLR,Interrupt Enable Set/Clr Register 1"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x14 31. " REQENA_63 ,Request enable set bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x14 30. " REQENA_62 ,Request enable set bit 62" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 29. 0x04 29. 0x14 29. " REQENA_61 ,Request enable set bit 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x14 28. " REQENA_60 ,Request enable set bit 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 27. 0x04 27. 0x14 27. " REQENA_59 ,Request enable set bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x14 26. " REQENA_58 ,Request enable set bit 58" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 25. 0x04 25. 0x14 25. " REQENA_57 ,Request enable set bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x14 24. " REQENA_56 ,Request enable set bit 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 23. 0x04 23. 0x14 23. " REQENA_55 ,Request enable set bit 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x14 22. " REQENA_54 ,Request enable set bit 54" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 21. 0x04 21. 0x14 21. " REQENA_53 ,Request enable set bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x14 20. " REQENA_52 ,Request enable set bit 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 19. 0x04 19. 0x14 19. " REQENA_51 ,Request enable set bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x14 18. " REQENA_50 ,Request enable set bit 50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x04 17. 0x14 17. " REQENA_49 ,Request enable set bit 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x14 16. " REQENA_48 ,Request enable set bit 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 15. 0x04 15. 0x14 15. " REQENA_47 ,Request enable set bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x14 14. " REQENA_46 ,Request enable set bit 46" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 13. 0x04 13. 0x14 13. " REQENA_45 ,Request enable set bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x14 12. " REQENA_44 ,Request enable set bit 44" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x04 11. 0x00 11. 0x14 11. " REQENA_43 ,Request enable set bit 43" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x04 10. 0x04 10. 0x14 10. " REQENA_42 ,Request enable set bit 42" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x04 9. 0x04 9. 0x14 9. " REQENA_41 ,Request enable set bit 41" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x04 8. 0x04 8. 0x14 8. " REQENA_40 ,Request enable set bit 40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x14 7. " REQENA_39 ,Request enable set bit 39" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x14 6. " REQENA_38 ,Request enable set bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x14 5. " REQENA_37 ,Request enable set bit 37" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x14 3. " REQENA_35 ,Request enable set bit 35" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x04 2. 0x14 2. " REQENA_34 ,Request enable set bit 34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x14 1. " REQENA_33 ,Request enable set bit 33" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x14 0. " REQENA_32 ,Request enable set bit 32" "Disabled,Enabled"
|
|
line.long 0x08 "REQENASET2_SET/CLR,Interrupt Enable Set/Clr Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x08 31. 0x08 31. 0x18 31. " REQENA_95 ,Request enable set bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x18 30. " REQENA_94 ,Request enable set bit 94" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 29. 0x08 29. 0x18 29. " REQENA_93 ,Request enable set bit 93" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x18 28. " REQENA_92 ,Request enable set bit 92" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 27. 0x08 27. 0x18 27. " REQENA_91 ,Request enable set bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x18 26. " REQENA_90 ,Request enable set bit 90" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x08 25. 0x08 25. 0x18 25. " REQENA_89 ,Request enable set bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x18 24. " REQENA_88 ,Request enable set bit 88" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x08 23. 0x08 23. 0x18 23. " REQENA_87 ,Request enable set bit 87" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x18 22. " REQENA_86 ,Request enable set bit 86" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 21. 0x08 21. 0x18 21. " REQENA_85 ,Request enable set bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x18 20. " REQENA_84 ,Request enable set bit 84" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x08 19. 0x08 19. 0x18 19. " REQENA_83 ,Request enable set bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x18 18. " REQENA_82 ,Request enable set bit 82" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 17. 0x08 17. 0x18 17. " REQENA_81 ,Request enable set bit 81" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x18 16. " REQENA_80 ,Request enable set bit 80" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 15. 0x08 15. 0x18 15. " REQENA_79 ,Request enable set bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x18 14. " REQENA_78 ,Request enable set bit 78" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 13. 0x08 13. 0x18 13. " REQENA_77 ,Request enable set bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x18 12. " REQENA_76 ,Request enable set bit 76" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 11. 0x08 11. 0x18 11. " REQENA_75 ,Request enable set bit 75" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x18 10. " REQENA_74 ,Request enable set bit 74" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 9. 0x08 9. 0x18 9. " REQENA_73 ,Request enable set bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x18 8. " REQENA_72 ,Request enable set bit 72" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 7. 0x08 7. 0x18 7. " REQENA_71 ,Request enable set bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x18 6. " REQENA_70 ,Request enable set bit 70" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 5. 0x08 5. 0x18 5. " REQENA_69 ,Request enable set bit 69" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x18 4. " REQENA_68 ,Request enable set bit 68" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x08 3. 0x18 3. " REQENA_67 ,Request enable set bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x18 2. " REQENA_66 ,Request enable set bit 66" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 1. 0x08 1. 0x18 1. " REQENA_65 ,Request enable set bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x18 0. " REQENA_64 ,Request enable set bit 64" "Disabled,Enabled"
|
|
tree.end
|
|
width 18.
|
|
tree "VIM Wake Up Mask Registers"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "WAKEENA_SET/CLR0,Wake-up Enable Set/Clr Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_31 ,Wake-up enable set bit 31" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEENA_30 ,Wake-up enable set bit 30" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_29 ,Wake-up enable set bit 29" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_28 ,Wake-up enable set bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_27 ,Wake-up enable set bit 27" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEENA_26 ,Wake-up enable set bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_25 ,Wake-up enable set bit 25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_24 ,Wake-up enable set bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_23 ,Wake-up enable set bit 23" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_22 ,Wake-up enable set bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_21 ,Wake-up enable set bit 21" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEENA_20 ,Wake-up enable set bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_19 ,Wake-up enable set bit 19" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_18 ,Wake-up enable set bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_16 ,Wake-up enable set bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_15 ,Wake-up enable set bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_14 ,Wake-up enable set bit 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_13 ,Wake-up enable set bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_12 ,Wake-up enable set bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_11 ,Wake-up enable set bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_10 ,Wake-up enable set bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_9 ,Wake-up enable set bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_8 ,Wake-up enable set bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_7 ,Wake-up enable set bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_6 ,Wake-up enable set bit 6" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_5 ,Wake-up enable set bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_4 ,Wake-up enable set bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_3 ,Wake-up enable set bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_2 ,Wake-up enable set bit 2" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEENA_1 ,Wake-up enable set bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_0 ,Wake-up enable set bit 0" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_0 ,Wake-up enable set bit 0" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "WAKEENA_SET/CLR1,Wake-up Enable Set/Clr Register 1"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x14 31. " WAKEENA_63 ,Wake-up enable set bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x14 30. " WAKEENA_62 ,Wake-up enable set bit 62" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 29. 0x04 29. 0x14 29. " WAKEENA_61 ,Wake-up enable set bit 61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x14 28. " WAKEENA_60 ,Wake-up enable set bit 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 27. 0x04 27. 0x14 27. " WAKEENA_59 ,Wake-up enable set bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x14 26. " WAKEENA_58 ,Wake-up enable set bit 58" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 25. 0x04 25. 0x14 25. " WAKEENA_57 ,Wake-up enable set bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x14 24. " WAKEENA_56 ,Wake-up enable set bit 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 23. 0x04 23. 0x14 23. " WAKEENA_55 ,Wake-up enable set bit 55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x14 22. " WAKEENA_54 ,Wake-up enable set bit 54" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 21. 0x04 21. 0x14 21. " WAKEENA_53 ,Wake-up enable set bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x14 20. " WAKEENA_52 ,Wake-up enable set bit 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 19. 0x04 19. 0x14 19. " WAKEENA_51 ,Wake-up enable set bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x14 18. " WAKEENA_50 ,Wake-up enable set bit 50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x04 17. 0x14 17. " WAKEENA_49 ,Wake-up enable set bit 49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x14 16. " WAKEENA_48 ,Wake-up enable set bit 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 15. 0x04 15. 0x14 15. " WAKEENA_47 ,Wake-up enable set bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x14 14. " WAKEENA_46 ,Wake-up enable set bit 46" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 13. 0x04 13. 0x14 13. " WAKEENA_45 ,Wake-up enable set bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x14 12. " WAKEENA_44 ,Wake-up enable set bit 44" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x04 11. 0x04 11. 0x14 11. " WAKEENA_43 ,Wake-up enable set bit 43" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x14 10. " WAKEENA_42 ,Wake-up enable set bit 42" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x04 10. 0x04 10. 0x14 10. " WAKEENA_42 ,Wake-up enable set bit 42" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x14 9. " WAKEENA_41 ,Wake-up enable set bit 41" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x04 8. 0x04 8. 0x14 8. " WAKEENA_40 ,Wake-up enable set bit 40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x14 7. " WAKEENA_39 ,Wake-up enable set bit 39" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x14 6. " WAKEENA_38 ,Wake-up enable set bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x14 5. " WAKEENA_37 ,Wake-up enable set bit 37" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
setclrfld.long 0x04 4. 0x04 4. 0x14 4. " WAKEENA_36 ,Wake-up enable set bit 36" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x14 3. " WAKEENA_35 ,Wake-up enable set bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x14 2. " WAKEENA_34 ,Wake-up enable set bit 34" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 1. 0x04 1. 0x14 1. " WAKEENA_33 ,Wake-up enable set bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x14 0. " WAKEENA_32 ,Wake-up enable set bit 32" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENA_SET/CLR2,Wake-up Enable Set/Clr Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x08 31. 0x08 31. 0x18 31. " WAKEENA_95 ,Wake-up enable set bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x18 30. " WAKEENA_94 ,Wake-up enable set bit 94" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 29. 0x08 29. 0x18 29. " WAKEENA_93 ,Wake-up enable set bit 93" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x18 28. " WAKEENA_92 ,Wake-up enable set bit 92" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 27. 0x08 27. 0x18 27. " WAKEENA_91 ,Wake-up enable set bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x18 26. " WAKEENA_90 ,Wake-up enable set bit 90" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x08 25. 0x08 25. 0x18 25. " WAKEENA_89 ,Wake-up enable set bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x18 24. " WAKEENA_88 ,Wake-up enable set bit 88" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x08 23. 0x08 23. 0x18 23. " WAKEENA_87 ,Wake-up enable set bit 87" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x18 22. " WAKEENA_86 ,Wake-up enable set bit 86" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 21. 0x08 21. 0x18 21. " WAKEENA_85 ,Wake-up enable set bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x18 20. " WAKEENA_84 ,Wake-up enable set bit 84" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x08 19. 0x08 19. 0x18 19. " WAKEENA_83 ,Wake-up enable set bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x18 18. " WAKEENA_82 ,Wake-up enable set bit 82" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 17. 0x08 17. 0x18 17. " WAKEENA_81 ,Wake-up enable set bit 81" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x18 16. " WAKEENA_80 ,Wake-up enable set bit 80" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 15. 0x08 15. 0x18 15. " WAKEENA_79 ,Wake-up enable set bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x18 14. " WAKEENA_78 ,Wake-up enable set bit 78" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 13. 0x08 13. 0x18 13. " WAKEENA_77 ,Wake-up enable set bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x18 12. " WAKEENA_76 ,Wake-up enable set bit 76" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 11. 0x08 11. 0x18 11. " WAKEENA_75 ,Wake-up enable set bit 75" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x18 10. " WAKEENA_74 ,Wake-up enable set bit 74" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 9. 0x08 9. 0x18 9. " WAKEENA_73 ,Wake-up enable set bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x18 8. " WAKEENA_72 ,Wake-up enable set bit 72" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 7. 0x08 7. 0x18 7. " WAKEENA_71 ,Wake-up enable set bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x18 6. " WAKEENA_70 ,Wake-up enable set bit 70" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 5. 0x08 5. 0x18 5. " WAKEENA_69 ,Wake-up enable set bit 69" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x18 4. " WAKEENA_68 ,Wake-up enable set bit 68" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x08 3. 0x18 3. " WAKEENA_67 ,Wake-up enable set bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x18 2. " WAKEENA_66 ,Wake-up enable set bit 66" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 1. 0x08 1. 0x18 1. " WAKEENA_65 ,Wake-up enable set bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x18 0. " WAKEENA_64 ,Wake-up enable set bit 64" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree "VIM Interrupt Vector Registers"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "IRQVECREG,IRQ Interrupt Vector Register"
|
|
line.long 0x04 "FIQVECREG,FIQ Interrupt Vector Register"
|
|
tree.end
|
|
newline
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CAPEVTSRC,Capture Event Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1 ,Capture Event Source 1 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0 ,Capture Event Source 0 mapping control"
|
|
width 12.
|
|
tree "VIM Interrupt Control Registers"
|
|
group.long 0x80++0x53
|
|
line.long 0x00 "CHANCTRL0,VIM Interrupt Control Register 0"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0 ,Interrupt CHAN0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1 ,Interrupt CHAN1 mapping control"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2 ,Interrupt CHAN2 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3 ,Interrupt CHAN3 mapping control"
|
|
line.long 0x04 "CHANCTRL1,VIM Interrupt Control Register 1"
|
|
hexmask.long.byte 0x04 24.--30. 1. " CHANMAP4 ,Interrupt CHAN4 mapping control"
|
|
hexmask.long.byte 0x04 16.--22. 1. " CHANMAP5 ,Interrupt CHAN5 mapping control"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CHANMAP6 ,Interrupt CHAN6 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--6. 1. " CHANMAP7 ,Interrupt CHAN7 mapping control"
|
|
line.long 0x08 "CHANCTRL2,VIM Interrupt Control Register 2"
|
|
hexmask.long.byte 0x08 24.--30. 1. " CHANMAP8 ,Interrupt CHAN8 mapping control"
|
|
hexmask.long.byte 0x08 16.--22. 1. " CHANMAP9 ,Interrupt CHAN9 mapping control"
|
|
hexmask.long.byte 0x08 8.--14. 1. " CHANMAP10 ,Interrupt CHAN10 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--6. 1. " CHANMAP11 ,Interrupt CHAN11 mapping control"
|
|
line.long 0x0C "CHANCTRL3,VIM Interrupt Control Register 3"
|
|
hexmask.long.byte 0x0C 24.--30. 1. " CHANMAP12 ,Interrupt CHAN12 mapping control"
|
|
hexmask.long.byte 0x0C 16.--22. 1. " CHANMAP13 ,Interrupt CHAN13 mapping control"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " CHANMAP14 ,Interrupt CHAN14 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--6. 1. " CHANMAP15 ,Interrupt CHAN15 mapping control"
|
|
line.long 0x10 "CHANCTRL4,VIM Interrupt Control Register 4"
|
|
hexmask.long.byte 0x10 24.--30. 1. " CHANMAP16 ,Interrupt CHAN16 mapping control"
|
|
hexmask.long.byte 0x10 8.--14. 1. " CHANMAP18 ,Interrupt CHAN18 mapping control"
|
|
hexmask.long.byte 0x10 0.--6. 1. " CHANMAP19 ,Interrupt CHAN19 mapping control"
|
|
line.long 0x14 "CHANCTRL5,VIM Interrupt Control Register 5"
|
|
hexmask.long.byte 0x14 24.--30. 1. " CHANMAP20 ,Interrupt CHAN20 mapping control"
|
|
hexmask.long.byte 0x14 16.--22. 1. " CHANMAP21 ,Interrupt CHAN21 mapping control"
|
|
hexmask.long.byte 0x14 8.--14. 1. " CHANMAP22 ,Interrupt CHAN22 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. " CHANMAP23 ,Interrupt CHAN23 mapping control"
|
|
line.long 0x18 "CHANCTRL6,VIM Interrupt Control Register 6"
|
|
hexmask.long.byte 0x18 24.--30. 1. " CHANMAP24 ,Interrupt CHAN24 mapping control"
|
|
hexmask.long.byte 0x18 16.--22. 1. " CHANMAP25 ,Interrupt CHAN25 mapping control"
|
|
hexmask.long.byte 0x18 8.--14. 1. " CHANMAP26 ,Interrupt CHAN26 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--6. 1. " CHANMAP27 ,Interrupt CHAN27 mapping control"
|
|
line.long 0x1C "CHANCTRL7,VIM Interrupt Control Register 7"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " CHANMAP28 ,Interrupt CHAN28 mapping control"
|
|
hexmask.long.byte 0x1C 16.--22. 1. " CHANMAP29 ,Interrupt CHAN29 mapping control"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " CHANMAP31 ,Interrupt CHAN31 mapping control"
|
|
line.long 0x20 "CHANCTRL8,VIM Interrupt Control Register 8"
|
|
hexmask.long.byte 0x20 24.--30. 1. " CHANMAP32 ,Interrupt CHAN32 mapping control"
|
|
hexmask.long.byte 0x20 16.--22. 1. " CHANMAP33 ,Interrupt CHAN33 mapping control"
|
|
hexmask.long.byte 0x20 8.--14. 1. " CHANMAP34 ,Interrupt CHAN34 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--6. 1. " CHANMAP35 ,Interrupt CHAN35 mapping control"
|
|
line.long 0x24 "CHANCTRL9,VIM Interrupt Control Register 9"
|
|
hexmask.long.byte 0x24 16.--22. 1. " CHANMAP37 ,Interrupt CHAN37 mapping control"
|
|
hexmask.long.byte 0x24 8.--14. 1. " CHANMAP38 ,Interrupt CHAN38 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--6. 1. " CHANMAP39 ,Interrupt CHAN39 mapping control"
|
|
line.long 0x28 "CHANCTRL10,VIM Interrupt Control Register 10"
|
|
hexmask.long.byte 0x28 24.--30. 1. " CHANMAP40 ,Interrupt CHAN40 mapping control"
|
|
hexmask.long.byte 0x28 8.--14. 1. " CHANMAP42 ,Interrupt CHAN42 mapping control"
|
|
line.long 0x2C "CHANCTRL11,VIM Interrupt Control Register 11"
|
|
hexmask.long.byte 0x2C 24.--30. 1. " CHANMAP44 ,Interrupt CHAN44 mapping control"
|
|
hexmask.long.byte 0x2C 16.--22. 1. " CHANMAP45 ,Interrupt CHAN45 mapping control"
|
|
hexmask.long.byte 0x2C 8.--14. 1. " CHANMAP46 ,Interrupt CHAN46 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--6. 1. " CHANMAP47 ,Interrupt CHAN47 mapping control"
|
|
line.long 0x30 "CHANCTRL12,VIM Interrupt Control Register 12"
|
|
hexmask.long.byte 0x30 24.--30. 1. " CHANMAP48 ,Interrupt CHAN48 mapping control"
|
|
hexmask.long.byte 0x30 16.--22. 1. " CHANMAP49 ,Interrupt CHAN49 mapping control"
|
|
hexmask.long.byte 0x30 8.--14. 1. " CHANMAP50 ,Interrupt CHAN50 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--6. 1. " CHANMAP51 ,Interrupt CHAN51 mapping control"
|
|
line.long 0x34 "CHANCTRL13,VIM Interrupt Control Register 13"
|
|
hexmask.long.byte 0x34 24.--30. 1. " CHANMAP52 ,Interrupt CHAN52 mapping control"
|
|
hexmask.long.byte 0x34 16.--22. 1. " CHANMAP53 ,Interrupt CHAN53 mapping control"
|
|
hexmask.long.byte 0x34 8.--14. 1. " CHANMAP54 ,Interrupt CHAN54 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--6. 1. " CHANMAP55 ,Interrupt CHAN55 mapping control"
|
|
line.long 0x38 "CHANCTRL14,VIM Interrupt Control Register 14"
|
|
hexmask.long.byte 0x38 24.--30. 1. " CHANMAP56 ,Interrupt CHAN56 mapping control"
|
|
hexmask.long.byte 0x38 16.--22. 1. " CHANMAP57 ,Interrupt CHAN57 mapping control"
|
|
hexmask.long.byte 0x38 8.--14. 1. " CHANMAP58 ,Interrupt CHAN58 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--6. 1. " CHANMAP59 ,Interrupt CHAN59 mapping control"
|
|
line.long 0x3C "CHANCTRL15,VIM Interrupt Control Register 15"
|
|
hexmask.long.byte 0x3C 24.--30. 1. " CHANMAP60 ,Interrupt CHAN60 mapping control"
|
|
hexmask.long.byte 0x3C 16.--22. 1. " CHANMAP61 ,Interrupt CHAN61 mapping control"
|
|
hexmask.long.byte 0x3C 8.--14. 1. " CHANMAP62 ,Interrupt CHAN62 mapping control"
|
|
hexmask.long.byte 0x3C 0.--6. 1. " CHANMAP63 ,Interrupt CHAN63 mapping control"
|
|
line.long 0x40 "CHANCTRL16,VIM Interrupt Control Register 16"
|
|
hexmask.long.byte 0x40 24.--30. 1. " CHANMAP64 ,Interrupt CHAN64 mapping control"
|
|
hexmask.long.byte 0x40 16.--22. 1. " CHANMAP65 ,Interrupt CHAN65 mapping control"
|
|
hexmask.long.byte 0x40 8.--14. 1. " CHANMAP66 ,Interrupt CHAN66 mapping control"
|
|
hexmask.long.byte 0x40 0.--6. 1. " CHANMAP67 ,Interrupt CHAN63 mapping control"
|
|
line.long 0x44 "CHANCTRL17,Channel Mapping Register"
|
|
hexmask.long.byte 0x44 24.--30. 1. " CHANMAP68 ,Interrupt CHAN60 mapping control"
|
|
hexmask.long.byte 0x44 16.--22. 1. " CHANMAP69 ,Interrupt CHAN61 mapping control"
|
|
hexmask.long.byte 0x44 8.--14. 1. " CHANMAP70 ,Interrupt CHAN62 mapping control"
|
|
hexmask.long.byte 0x44 0.--6. 1. " CHANMAP71 ,Interrupt CHAN63 mapping control"
|
|
line.long 0x48 "CHANCTRL18,VIM Interrupt Control Register 18"
|
|
hexmask.long.byte 0x48 24.--30. 1. " CHANMAP72 ,Interrupt CHAN60 mapping control"
|
|
hexmask.long.byte 0x48 16.--22. 1. " CHANMAP73 ,Interrupt CHAN73 mapping control"
|
|
hexmask.long.byte 0x48 8.--14. 1. " CHANMAP74 ,Interrupt CHAN74 mapping control"
|
|
hexmask.long.byte 0x48 0.--6. 1. " CHANMAP75 ,Interrupt CHAN75 mapping control"
|
|
line.long 0x4C "CHANCTRL19,VIM Interrupt Control Register 19"
|
|
hexmask.long.byte 0x4C 24.--30. 1. " CHANMAP76 ,Interrupt CHAN76 mapping control"
|
|
hexmask.long.byte 0x4C 16.--22. 1. " CHANMAP77 ,Interrupt CHAN77 mapping control"
|
|
hexmask.long.byte 0x4C 8.--14. 1. " CHANMAP78 ,Interrupt CHAN78 mapping control"
|
|
hexmask.long.byte 0x4C 0.--6. 1. " CHANMAP79 ,Interrupt CHAN79 mapping control"
|
|
line.long 0x50 "CHANCTRL20,VIM Interrupt Control Register 20"
|
|
hexmask.long.byte 0x50 24.--30. 1. " CHANMAP80 ,Interrupt CHAN80 mapping control"
|
|
hexmask.long.byte 0x50 16.--22. 1. " CHANMAP81 ,Interrupt CHAN81 mapping control"
|
|
hexmask.long.byte 0x50 8.--14. 1. " CHANMAP82 ,Interrupt CHAN82 mapping control"
|
|
hexmask.long.byte 0x50 0.--6. 1. " CHANMAP83 ,Interrupt CHAN83 mapping control"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "CHANCTRL21,VIM Interrupt Control Register 21"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP84 ,Interrupt CHAN84 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMA85 ,Interrupt CHAN85 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMA86 ,Interrupt CHAN86 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMA87 ,Interrupt CHAN87 mapping control"
|
|
else
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "CHANCTRL21,Channel Mapping Register"
|
|
endif
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CHANCTRL22,VIM Interrupt Control Register 22"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMA88 ,Interrupt CHAN88 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMA89 ,Interrupt CHAN89 mapping control"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMA90 ,Interrupt CHAN90 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMA91 ,Interrupt CHAN91 mapping control"
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CHANCTRL23,VIM Interrupt Control Register 23"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMA92 ,Interrupt CHAN92 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMA93 ,Interrupt CHAN93 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMA94 ,Interrupt CHAN94 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMA95 ,Interrupt CHAN95 mapping control"
|
|
else
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "CHANCTRL23,Channel Mapping Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "VIMPAR"
|
|
base ad:0xFFFFFD00
|
|
width 10.
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PARFLG,Interrupt Vector Table Parity Flag Register"
|
|
eventfld.long 0x00 0. " PARFLG ,Parity error flag" "No error,Error"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PARCTL,Interrupt Vector Table Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits mapping" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARENA ,VIM parity enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(ad:0xFFFFFD00+0xEC))&0x01)==0x01)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "ADDERR,Address Parity Error Register"
|
|
hexmask.long.word 0x00 2.--8. 0x04 " ADDERR ,Address parity error"
|
|
hexmask.long.byte 0x00 0.--1. 0x01 " WO ,Word offset"
|
|
else
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "ADDERR,Address Parity Error Register"
|
|
hexmask.long.byte 0x00 0.--1. 0x01 " WO ,Word Offset"
|
|
endif
|
|
else
|
|
if (((per.long(ad:0xFFFFFD00+0xEC))&0x01)==0x01)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "ADDERR,Address Parity Error Register"
|
|
sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS20216-ZWT")||cpu()==("TMS570PSFC61")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336"))
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM offset"
|
|
endif
|
|
hexmask.long.word 0x00 2.--8. 0x04 " ADDERR ,Address parity error"
|
|
hexmask.long.byte 0x00 0.--1. 1. " WO ,Word offset"
|
|
else
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "ADDERR,Address Parity Error Register"
|
|
sif (cpu()==("TMS570PSFC61")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336"))
|
|
hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM offset"
|
|
endif
|
|
hexmask.long.byte 0x00 0.--1. 1. " WO ,Word offset"
|
|
endif
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "FBPARERR,Fall Back Address Parity Error Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "POM (Parameter Overlay Module)"
|
|
base ad:0xFFA04000
|
|
width 15.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GlbCtrl,Global Control Register"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "Rev,Revision Id"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "ClkCtrl,Clock Gate Control Register"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "Flg,POM Flag Register"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "ProgStart0,Program Region Start Address Register 0"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "OvlStart0,Overlay Region Start Address Register 0"
|
|
group.long 0x208++0x3
|
|
line.long 0x0 "RegSize0,Region Size Register 0"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "ProgStart1,Program Region Start Address Register 1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "OvlStart1,Overlay Region Start Address Register 1"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "RegSize1,Region Size Register 1"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "ProgStart2,Program Region Start Address Register 2"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "OvlStart2,Overlay Region Start Address Register 2"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "RegSize2,Region Size Register 2"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "ProgStart3,Program Region Start Address Register 3"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "OvlStart3,Overlay Region Start Address Register 3"
|
|
group.long 0x238++0x3
|
|
line.long 0x0 "RegSize3,Region Size Register 3"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "ProgStart4,Program Region Start Address Register 4"
|
|
group.long 0x244++0x3
|
|
line.long 0x0 "OvlStart4,Overlay Region Start Address Register 4"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "RegSize4,Region Size Register 4"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "ProgStart5,Program Region Start Address Register 5"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "OvlStart5,Overlay Region Start Address Register 5"
|
|
group.long 0x258++0x3
|
|
line.long 0x0 "RegSize5,Region Size Register 5"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "ProgStart6,Program Region Start Address Register 6"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "OvlStart6,Overlay Region Start Address Register 6"
|
|
group.long 0x268++0x3
|
|
line.long 0x0 "RegSize6,Region Size Register 6"
|
|
group.long 0x270++0x3
|
|
line.long 0x0 "ProgStart7,Program Region Start Address Register 7"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "OvlStart7,Overlay Region Start Address Register 7"
|
|
group.long 0x278++0x3
|
|
line.long 0x0 "RegSize7,Region Size Register 7"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "ProgStart8,Program Region Start Address Register 8"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "OvlStart8,Overlay Region Start Address Register 8"
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "RegSize8,Region Size Register 8"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "ProgStart9,Program Region Start Address Register 9"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "OvlStart9,Overlay Region Start Address Register 9"
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "RegSize9,Region Size Register 9"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ProgStart10,Program Region Start Address Register 10"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x0 "OvlStart10,Overlay Region Start Address Register 10"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x0 "RegSize10,Region Size Register 10"
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "ProgStart11,Program Region Start Address Register 11"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "OvlStart11,Overlay Region Start Address Register 11"
|
|
group.long 0x2B8++0x3
|
|
line.long 0x0 "RegSize11,Region Size Register 11"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "ProgStart12,Program Region Start Address Register 12"
|
|
group.long 0x2C4++0x3
|
|
line.long 0x0 "OvlStart12,Overlay Region Start Address Register 12"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "RegSize12,Region Size Register 12"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "ProgStart13,Program Region Start Address Register 13"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x0 "OvlStart13,Overlay Region Start Address Register 13"
|
|
group.long 0x2D8++0x3
|
|
line.long 0x0 "RegSize13,Region Size Register 13"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "ProgStart14,Program Region Start Address Register 14"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "OvlStart14,Overlay Region Start Address Register 14"
|
|
group.long 0x2E8++0x3
|
|
line.long 0x0 "RegSize14,Region Size Register 14"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x0 "ProgStart15,Program Region Start Address Register 15"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x0 "OvlStart15,Overlay Region Start Address Register 15"
|
|
group.long 0x2F8++0x3
|
|
line.long 0x0 "RegSize15,Region Size Register 15"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "ProgStart16,Program Region Start Address Register 16"
|
|
group.long 0x304++0x3
|
|
line.long 0x0 "OvlStart16,Overlay Region Start Address Register 16"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "RegSize16,Region Size Register 16"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "ProgStart17,Program Region Start Address Register 17"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "OvlStart17,Overlay Region Start Address Register 17"
|
|
group.long 0x318++0x3
|
|
line.long 0x0 "RegSize17,Region Size Register 17"
|
|
group.long 0x320++0x3
|
|
line.long 0x0 "ProgStart18,Program Region Start Address Register 18"
|
|
group.long 0x324++0x3
|
|
line.long 0x0 "OvlStart18,Overlay Region Start Address Register 18"
|
|
group.long 0x328++0x3
|
|
line.long 0x0 "RegSize18,Region Size Register 18"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "ProgStart19,Program Region Start Address Register 19"
|
|
group.long 0x334++0x3
|
|
line.long 0x0 "OvlStart19,Overlay Region Start Address Register 19"
|
|
group.long 0x338++0x3
|
|
line.long 0x0 "RegSize19,Region Size Register 19"
|
|
group.long 0x340++0x3
|
|
line.long 0x0 "ProgStart20,Program Region Start Address Register 20"
|
|
group.long 0x344++0x3
|
|
line.long 0x0 "OvlStart20,Overlay Region Start Address Register 20"
|
|
group.long 0x348++0x3
|
|
line.long 0x0 "RegSize20,Region Size Register 20"
|
|
group.long 0x350++0x3
|
|
line.long 0x0 "ProgStart21,Program Region Start Address Register 21"
|
|
group.long 0x354++0x3
|
|
line.long 0x0 "OvlStart21,Overlay Region Start Address Register 21"
|
|
group.long 0x358++0x3
|
|
line.long 0x0 "RegSize21,Region Size Register 21"
|
|
group.long 0x360++0x3
|
|
line.long 0x0 "ProgStart22,Program Region Start Address Register 22"
|
|
group.long 0x364++0x3
|
|
line.long 0x0 "OvlStart22,Overlay Region Start Address Register 22"
|
|
group.long 0x368++0x3
|
|
line.long 0x0 "RegSize22,Region Size Register 22"
|
|
group.long 0x370++0x3
|
|
line.long 0x0 "ProgStart23,Program Region Start Address Register 23"
|
|
group.long 0x374++0x3
|
|
line.long 0x0 "OvlStart23,Overlay Region Start Address Register 23"
|
|
group.long 0x378++0x3
|
|
line.long 0x0 "RegSize23,Region Size Register 23"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "ProgStart24,Program Region Start Address Register 24"
|
|
group.long 0x384++0x3
|
|
line.long 0x0 "OvlStart24,Overlay Region Start Address Register 24"
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "RegSize24,Region Size Register 24"
|
|
group.long 0x390++0x3
|
|
line.long 0x0 "ProgStart25,Program Region Start Address Register 25"
|
|
group.long 0x394++0x3
|
|
line.long 0x0 "OvlStart25,Overlay Region Start Address Register 25"
|
|
group.long 0x398++0x3
|
|
line.long 0x0 "RegSize25,Region Size Register 25"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x0 "ProgStart26,Program Region Start Address Register 26"
|
|
group.long 0x3A4++0x3
|
|
line.long 0x0 "OvlStart26,Overlay Region Start Address Register 26"
|
|
group.long 0x3A8++0x3
|
|
line.long 0x0 "RegSize26,Region Size Register 26"
|
|
group.long 0x3B0++0x3
|
|
line.long 0x0 "ProgStart27,Program Region Start Address Register 27"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x0 "OvlStart27,Overlay Region Start Address Register 27"
|
|
group.long 0x3B8++0x3
|
|
line.long 0x0 "RegSize27,Region Size Register 27"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x0 "ProgStart28,Program Region Start Address Register 28"
|
|
group.long 0x3C4++0x3
|
|
line.long 0x0 "OvlStart28,Overlay Region Start Address Register 28"
|
|
group.long 0x3C8++0x3
|
|
line.long 0x0 "RegSize28,Region Size Register 28"
|
|
group.long 0x3D0++0x3
|
|
line.long 0x0 "ProgStart29,Program Region Start Address Register 29"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x0 "OvlStart29,Overlay Region Start Address Register 29"
|
|
group.long 0x3D8++0x3
|
|
line.long 0x0 "RegSize29,Region Size Register 29"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x0 "ProgStart30,Program Region Start Address Register 30"
|
|
group.long 0x3E4++0x3
|
|
line.long 0x0 "OvlStart30,Overlay Region Start Address Register 30"
|
|
group.long 0x3E8++0x3
|
|
line.long 0x0 "RegSize30,Region Size Register 30"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "ProgStart31,Program Region Start Address Register 31"
|
|
group.long 0x3F4++0x3
|
|
line.long 0x0 "OvlStart31,Overlay Region Start Address Register 31"
|
|
group.long 0x3F8++0x3
|
|
line.long 0x0 "RegSize31,Region Size Register 31"
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "ItCtrl,Integration Control Register"
|
|
group.long 0xFA0++0x3
|
|
line.long 0x0 "ClaimSet,Claim Set Register"
|
|
group.long 0xFA4++0x3
|
|
line.long 0x0 "ClaimClr,Claim Clear Register"
|
|
group.long 0xFB0++0x3
|
|
line.long 0x0 "LockAccess,Lock Access Register"
|
|
group.long 0xFB4++0x3
|
|
line.long 0x0 "LockStatus,Lock Status Register"
|
|
group.long 0xFB8++0x3
|
|
line.long 0x0 "AuthStatus,Authentication Status Register"
|
|
group.long 0xFC8++0x3
|
|
line.long 0x0 "DevId,Device Id Register"
|
|
group.long 0xFCC++0x3
|
|
line.long 0x0 "DevType,Device Type Register"
|
|
group.long 0xFD0++0x3
|
|
line.long 0x0 "PeripheralId4,Peripheral Id 4 Register"
|
|
group.long 0xFD4++0x3
|
|
line.long 0x0 "PeripheralId5,Peripheral Id 5 Register"
|
|
group.long 0xFD8++0x3
|
|
line.long 0x0 "PeripheralId6,Peripheral Id 6 Register"
|
|
group.long 0xFDC++0x3
|
|
line.long 0x0 "PeripheralId7,Peripheral Id 7 Register"
|
|
group.long 0xFE0++0x3
|
|
line.long 0x0 "PeripheralId0,Peripheral Id 0 Register"
|
|
group.long 0xFE4++0x3
|
|
line.long 0x0 "PeripheralId1,Peripheral Id 1 Register"
|
|
group.long 0xFE8++0x3
|
|
line.long 0x0 "PeripheralId2,Peripheral Id 2 Register"
|
|
group.long 0xFEC++0x3
|
|
line.long 0x0 "PeripheralId3,Peripheral Id 3 Register"
|
|
group.long 0xFF0++0x3
|
|
line.long 0x0 "ComponentId0,Component Id 0 Register"
|
|
group.long 0xFF4++0x3
|
|
line.long 0x0 "ComponentId1,Component Id 1 Register"
|
|
group.long 0xFF8++0x3
|
|
line.long 0x0 "ComponentId2,Component Id 2 Register"
|
|
group.long 0xFFC++0x3
|
|
line.long 0x0 "ComponentId3,Component Id 3 Register"
|
|
width 11.
|
|
tree.end
|
|
tree "EMIF (Asynchronous External Memory Interface)"
|
|
base ad:0xFCFFE800
|
|
width 21.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "RevCdStat,Revision Code and Status Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "Async1Cfg,Asynchronous 1 Configuration Register (CS0 space)"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "Async2Cfg,Asynchronous 2 Configuration Register (CS1 space)"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "Async3Cfg,Asynchronous 3 Configuration Register (CS2 space)"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "Async4Cfg,Asynchronous 4 Configuration Register (CS3 space)"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SdramTiming,SDRAM Timing Register"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SdramStat,SDRAM Status Register"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DdrPhyCtrl,DDR PHY Control Register"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DdrPhyStat,DDR PHY Status Register"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "SdramAccess,Total SDRAM Accesses Register"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "SdramActivat,Total SDRAM Activate Register"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DdrPhyIdRev,DDR PHY ID and Revision Register"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SdramSrExTiming,SDRAM SR/PD Exit Timing Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "IntRaw,Interrupt Raw Register"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "IntMask,Interrupt Masked Register"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "IntMaskSet,Interrupt Mask Set Register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "IntMaskClr,Interrupt Mask Clear Register"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "IoCtrl,IO Control Register"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "IoStat,IO Status Register"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "SdramConfig2,SDRAM Config 2 Register"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "OneNandFlashCtrl,NAND Flash Control Register"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "NandFlashCtrl,NAND Flash Control Register"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "NandFlashStat,NAND Flash Status Register"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PageModCtrl,Page Mode Control Register"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "NandFlashCs2Ecc,NAND Flash CS2 1-Bit ECC Register"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "NandFlashCs3Ecc,NAND Flash CS3 1-Bit ECC Register"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "NandFlashCs4Ecc,NAND Flash CS4 1-Bit ECC Register"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "NandFlashCs5Ecc,NAND Flash CS2 1-Bit ECC Register"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "IoDftExecCount,IODFT Test Logic Execution Counter Register"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "IoDftGlobCtrl,IODFT Test Logic Global Control Register"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IoDftAddrMisrResult,IODFT Test Logic Address MISR Result Register"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "IoDftDataMisrResult,IODFT Test Logic Data MISR Result Register"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "IoDftCtrlResult,IODFT Test Logic Data and Control MISR Result"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "ModuleRev,Module Release Number Register"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "NandFlashEccLoad,NAND Flash 4-Bit ECC Load Register"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "NandFlashEcc1,NAND Flash 4-Bit ECC 1 Register"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "NandFlashEcc2,NAND Flash 4-Bit ECC 2 Register"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "NandFlashEcc3,NAND Flash 4-Bit ECC 3 Register"
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "NandFlashEcc4,NAND Flash 4-Bit ECC 4 Register"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "NandFlashErrAddr1,NAND Flash Error Address 1 Register"
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "NandFlashErrAddr2,NAND Flash Error Address 2 Register"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "NandFlashErrAddr3,NAND Flash Error Address 3 Register"
|
|
group.long 0xDC++0x3
|
|
line.long 0x0 "NandFlashErrAddr4,NAND Flash Error Address 4 Register"
|
|
width 11.
|
|
tree.end
|
|
tree "PCR (Peripheral Central Resource)"
|
|
base ad:0xFFFFE000
|
|
width 12.
|
|
tree "PCR Protection Registers"
|
|
tree "PCR Memory Protection Registers"
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "PMPROTSET0,Set-only Register to Protect PCS Frames 0 to 31"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PROT_set/clr ,Peripheral Memory Frame Protection 31" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PROT_set/clr ,Peripheral Memory Frame Protection 30" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PROT_set/clr ,Peripheral Memory Frame Protection 29" "Not protected,Protected"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PROT_set/clr ,Peripheral Memory Frame Protection 28" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PROT_set/clr ,Peripheral Memory Frame Protection 27" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PROT_set/clr ,Peripheral Memory Frame Protection 26" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PROT_set/clr ,Peripheral Memory Frame Protection 25" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PROT_set/clr ,Peripheral Memory Frame Protection 24" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PROT_set/clr ,Peripheral Memory Frame Protection 23" "Not protected,Protected"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PROT_set/clr ,Peripheral Memory Frame Protection 22" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PROT_set/clr ,Peripheral Memory Frame Protection 21" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PROT_set/clr ,Peripheral Memory Frame Protection 20" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PROT_set/clr ,Peripheral Memory Frame Protection 19" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PROT_set/clr ,Peripheral Memory Frame Protection 18" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PROT_set/clr ,Peripheral Memory Frame Protection 17" "Not protected,Protected"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PROT_set/clr ,Peripheral Memory Frame Protection 16" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PROT_set/clr ,Peripheral Memory Frame Protection 15" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PROT_set/clr ,Peripheral Memory Frame Protection 14" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PROT_set/clr ,Peripheral Memory Frame Protection 13" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PROT_set/clr ,Peripheral Memory Frame Protection 12" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PROT_set/clr ,Peripheral Memory Frame Protection 11" "Not protected,Protected"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PROT_set/clr ,Peripheral Memory Frame Protection 10" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PROT_set/clr ,Peripheral Memory Frame Protection 9" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PROT_set/clr ,Peripheral Memory Frame Protection 8" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PROT_set/clr ,Peripheral Memory Frame Protection 7" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PROT_set/clr ,Peripheral Memory Frame Protection 6" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PROT_set/clr ,Peripheral Memory Frame Protection 5" "Not protected,Protected"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PROT_set/clr ,Peripheral Memory Frame Protection 4" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PROT_set/clr ,Peripheral Memory Frame Protection 3" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PROT_set/clr ,Peripheral Memory Frame Protection 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PROT_set/clr ,Peripheral Memory Frame Protection 1" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PROT_set/clr ,Peripheral Memory Frame Protection 0" "Not protected,Protected"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "PMPROTSET1,Set-only Register to Protect PCS Frames 32 to 63"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PROT_set/clr ,Peripheral Memory Frame Protection 63" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PROT_set/clr ,Peripheral Memory Frame Protection 62" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PROT_set/clr ,Peripheral Memory Frame Protection 61" "Not protected,Protected"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PROT_set/clr ,Peripheral Memory Frame Protection 60" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PROT_set/clr ,Peripheral Memory Frame Protection 59" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PROT_set/clr ,Peripheral Memory Frame Protection 58" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PROT_set/clr ,Peripheral Memory Frame Protection 57" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PROT_set/clr ,Peripheral Memory Frame Protection 56" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PROT_set/clr ,Peripheral Memory Frame Protection 55" "Not protected,Protected"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PROT_set/clr ,Peripheral Memory Frame Protection 54" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS53PROT_set/clr ,Peripheral Memory Frame Protection 53" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PROT_set/clr ,Peripheral Memory Frame Protection 52" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PROT_set/clr ,Peripheral Memory Frame Protection 51" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PROT_set/clr ,Peripheral Memory Frame Protection 50" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PROT_set/clr ,Peripheral Memory Frame Protection 49" "Not protected,Protected"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PROT_set/clr ,Peripheral Memory Frame Protection 48" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PROT_set/clr ,Peripheral Memory Frame Protection 47" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PROT_set/clr ,Peripheral Memory Frame Protection 46" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PROT_set/clr ,Peripheral Memory Frame Protection 45" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PROT_set/clr ,Peripheral Memory Frame Protection 44" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PROT_set/clr ,Peripheral Memory Frame Protection 43" "Not protected,Protected"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PROT_set/clr ,Peripheral Memory Frame Protection 42" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PROT_set/clr ,Peripheral Memory Frame Protection 41" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PROT_set/clr ,Peripheral Memory Frame Protection 40" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PROT_set/clr ,Peripheral Memory Frame Protection 39" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PROT_set/clr ,Peripheral Memory Frame Protection 38" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PROT_set/clr ,Peripheral Memory Frame Protection 37" "Not protected,Protected"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PROT_set/clr ,Peripheral Memory Frame Protection 36" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PROT_set/clr ,Peripheral Memory Frame Protection 35" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PROT_set/clr ,Peripheral Memory Frame Protection 34" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PROT_set/clr ,Peripheral Memory Frame Protection 33" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PROT_set/clr ,Peripheral Memory Frame Protection 32" "Not protected,Protected"
|
|
tree.end
|
|
width 12.
|
|
textline " "
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PPROTSET0,Set-only Register to Protect the 32 Quadrants of PS0 to PS7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS7QUAD3PROT_set/clr ,Peripheral Protection 7 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS7QUAD2PROT_set/clr ,Peripheral Protection 7 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS7QUAD1PROT_set/clr ,Peripheral Protection 7 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS7QUAD0PROT_set/clr ,Peripheral Protection 7 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS6QUAD3PROT_set/clr ,Peripheral Protection 6 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS6QUAD2PROT_set/clr ,Peripheral Protection 6 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS6QUAD1PROT_set/clr ,Peripheral Protection 6 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS6QUAD0PROT_set/clr ,Peripheral Protection 6 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS5QUAD3PROT_set/clr ,Peripheral Protection 5 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS5QUAD2PROT_set/clr ,Peripheral Protection 5 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS5QUAD1PROT_set/clr ,Peripheral Protection 5 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS5QUAD0PROT_set/clr ,Peripheral Protection 5 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS4QUAD3PROT_set/clr ,Peripheral Protection 4 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS4QUAD2PROT_set/clr ,Peripheral Protection 4 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS4QUAD1PROT_set/clr ,Peripheral Protection 4 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS4QUAD0PROT_set/clr ,Peripheral Protection 4 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS3QUAD3PROT_set/clr ,Peripheral Protection 3 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS3QUAD2PROT_set/clr ,Peripheral Protection 3 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS3QUAD1PROT_set/clr ,Peripheral Protection 3 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS3QUAD0PROT_set/clr ,Peripheral Protection 3 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS2QUAD3PROT_set/clr ,Peripheral Protection 2 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS2QUAD2PROT_set/clr ,Peripheral Protection 2 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS2QUAD1PROT_set/clr ,Peripheral Protection 2 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS2QUAD0PROT_set/clr ,Peripheral Protection 2 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS1QUAD3PROT_set/clr ,Peripheral Protection 1 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS1QUAD2PROT_set/clr ,Peripheral Protection 1 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS1QUAD1PROT_set/clr ,Peripheral Protection 1 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS1QUAD0PROT_set/clr ,Peripheral Protection 1 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS0QUAD3PROT_set/clr ,Peripheral Protection 0 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS0QUAD2PROT_set/clr ,Peripheral Protection 0 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS0QUAD1PROT_set/clr ,Peripheral Protection 0 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS0QUAD0PROT_set/clr ,Peripheral Protection 0 0" "Not protected,Protected"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "PPROTSET1,Set-only Register to Protect the 32 Quadrants of PS8 to PS15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS15QUAD3PROT_set/clr ,Peripheral Protection 15 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS15QUAD2PROT_set/clr ,Peripheral Protection 15 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS15QUAD1PROT_set/clr ,Peripheral Protection 15 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS15QUAD0PROT_set/clr ,Peripheral Protection 15 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS14QUAD3PROT_set/clr ,Peripheral Protection 14 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS14QUAD2PROT_set/clr ,Peripheral Protection 14 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS14QUAD1PROT_set/clr ,Peripheral Protection 14 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS14QUAD0PROT_set/clr ,Peripheral Protection 14 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS13QUAD3PROT_set/clr ,Peripheral Protection 13 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS13QUAD2PROT_set/clr ,Peripheral Protection 13 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS13QUAD1PROT_set/clr ,Peripheral Protection 13 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS13QUAD0PROT_set/clr ,Peripheral Protection 13 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS12QUAD3PROT_set/clr ,Peripheral Protection 12 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS12QUAD2PROT_set/clr ,Peripheral Protection 12 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS12QUAD1PROT_set/clr ,Peripheral Protection 12 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS12QUAD0PROT_set/clr ,Peripheral Protection 12 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS11QUAD3PROT_set/clr ,Peripheral Protection 11 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS11QUAD2PROT_set/clr ,Peripheral Protection 11 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS11QUAD1PROT_set/clr ,Peripheral Protection 11 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS11QUAD0PROT_set/clr ,Peripheral Protection 11 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS10QUAD3PROT_set/clr ,Peripheral Protection 10 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS10QUAD2PROT_set/clr ,Peripheral Protection 10 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS10QUAD1PROT_set/clr ,Peripheral Protection 10 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS10QUAD0PROT_set/clr ,Peripheral Protection 10 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS9QUAD3PROT_set/clr ,Peripheral Protection 9 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS9QUAD2PROT_set/clr ,Peripheral Protection 9 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS9QUAD1PROT_set/clr ,Peripheral Protection 9 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS9QUAD0PROT_set/clr ,Peripheral Protection 9 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS8QUAD3PROT_set/clr ,Peripheral Protection 8 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS8QUAD2PROT_set/clr ,Peripheral Protection 8 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS8QUAD1PROT_set/clr ,Peripheral Protection 8 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS8QUAD0PROT_set/clr ,Peripheral Protection 8 0" "Not protected,Protected"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PPROTSET2,Set-only Register to Protect the 32 Quadrants of PS16 to PS23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS23QUAD3PROT_set/clr ,Peripheral Protection 23 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS23QUAD2PROT_set/clr ,Peripheral Protection 23 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS23QUAD1PROT_set/clr ,Peripheral Protection 23 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS23QUAD0PROT_set/clr ,Peripheral Protection 23 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS22QUAD3PROT_set/clr ,Peripheral Protection 22 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS22QUAD2PROT_set/clr ,Peripheral Protection 22 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS22QUAD1PROT_set/clr ,Peripheral Protection 22 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS22QUAD0PROT_set/clr ,Peripheral Protection 22 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS21QUAD3PROT_set/clr ,Peripheral Protection 21 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS21QUAD2PROT_set/clr ,Peripheral Protection 21 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS21QUAD1PROT_set/clr ,Peripheral Protection 21 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS21QUAD0PROT_set/clr ,Peripheral Protection 21 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS20QUAD3PROT_set/clr ,Peripheral Protection 20 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS20QUAD2PROT_set/clr ,Peripheral Protection 20 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS20QUAD1PROT_set/clr ,Peripheral Protection 20 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS20QUAD0PROT_set/clr ,Peripheral Protection 20 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS19QUAD3PROT_set/clr ,Peripheral Protection 19 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS19QUAD2PROT_set/clr ,Peripheral Protection 19 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS19QUAD1PROT_set/clr ,Peripheral Protection 19 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS19QUAD0PROT_set/clr ,Peripheral Protection 19 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS18QUAD3PROT_set/clr ,Peripheral Protection 18 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS18QUAD2PROT_set/clr ,Peripheral Protection 18 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS18QUAD1PROT_set/clr ,Peripheral Protection 18 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS18QUAD0PROT_set/clr ,Peripheral Protection 18 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS17QUAD3PROT_set/clr ,Peripheral Protection 17 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS17QUAD2PROT_set/clr ,Peripheral Protection 17 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS17QUAD1PROT_set/clr ,Peripheral Protection 17 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS17QUAD0PROT_set/clr ,Peripheral Protection 17 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS16QUAD3PROT_set/clr ,Peripheral Protection 16 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS16QUAD2PROT_set/clr ,Peripheral Protection 16 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS16QUAD1PROT_set/clr ,Peripheral Protection 16 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS16QUAD0PROT_set/clr ,Peripheral Protection 16 0" "Not protected,Protected"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PPROTSET3,Set-only Register to Protect the 32 Quadrants of PS24 to PS31"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS31QUAD3PROT_set/clr ,Peripheral Protection 31 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS31QUAD2PROT_set/clr ,Peripheral Protection 31 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS31QUAD1PROT_set/clr ,Peripheral Protection 31 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS31QUAD0PROT_set/clr ,Peripheral Protection 31 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS30QUAD3PROT_set/clr ,Peripheral Protection 30 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS30QUAD2PROT_set/clr ,Peripheral Protection 30 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS30QUAD1PROT_set/clr ,Peripheral Protection 30 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS30QUAD0PROT_set/clr ,Peripheral Protection 30 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS29QUAD3PROT_set/clr ,Peripheral Protection 29 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS29QUAD2PROT_set/clr ,Peripheral Protection 29 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS29QUAD1PROT_set/clr ,Peripheral Protection 29 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS29QUAD0PROT_set/clr ,Peripheral Protection 29 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS28QUAD3PROT_set/clr ,Peripheral Protection 28 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS28QUAD2PROT_set/clr ,Peripheral Protection 28 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS28QUAD1PROT_set/clr ,Peripheral Protection 28 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS28QUAD0PROT_set/clr ,Peripheral Protection 28 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS27QUAD3PROT_set/clr ,Peripheral Protection 27 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS27QUAD2PROT_set/clr ,Peripheral Protection 27 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS27QUAD1PROT_set/clr ,Peripheral Protection 27 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS27QUAD0PROT_set/clr ,Peripheral Protection 27 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS26QUAD3PROT_set/clr ,Peripheral Protection 26 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS26QUAD2PROT_set/clr ,Peripheral Protection 26 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS26QUAD1PROT_set/clr ,Peripheral Protection 26 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS26QUAD0PROT_set/clr ,Peripheral Protection 26 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS25QUAD3PROT_set/clr ,Peripheral Protection 25 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS25QUAD2PROT_set/clr ,Peripheral Protection 25 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS25QUAD1PROT_set/clr ,Peripheral Protection 25 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS25QUAD0PROT_set/clr ,Peripheral Protection 25 0" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS24QUAD3PROT_set/clr ,Peripheral Protection 24 3" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS24QUAD2PROT_set/clr ,Peripheral Protection 24 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS24QUAD1PROT_set/clr ,Peripheral Protection 24 1" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS24QUAD0PROT_set/clr ,Peripheral Protection 24 0" "Not protected,Protected"
|
|
tree.end
|
|
width 15.
|
|
tree "PCR Power Down Registers"
|
|
tree "PCR Memory Power Down Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PCSPWRDWNSET0,Peripheral Memory Power-Down Set Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PWRDWN_set/clr ,Peripheral Memory Power Down Enable 31" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PWRDWN_set/clr ,Peripheral Memory Power Down Enable 30" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PWRDWN_set/clr ,Peripheral Memory Power Down Enable 29" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PWRDWN_set/clr ,Peripheral Memory Power Down Enable 28" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PWRDWN_set/clr ,Peripheral Memory Power Down Enable 27" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PWRDWN_set/clr ,Peripheral Memory Power Down Enable 26" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PWRDWN_set/clr ,Peripheral Memory Power Down Enable 25" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PWRDWN_set/clr ,Peripheral Memory Power Down Enable 24" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PWRDWN_set/clr ,Peripheral Memory Power Down Enable 23" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PWRDWN_set/clr ,Peripheral Memory Power Down Enable 22" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PWRDWN_set/clr ,Peripheral Memory Power Down Enable 21" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PWRDWN_set/clr ,Peripheral Memory Power Down Enable 20" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PWRDWN_set/clr ,Peripheral Memory Power Down Enable 19" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PWRDWN_set/clr ,Peripheral Memory Power Down Enable 18" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PWRDWN_set/clr ,Peripheral Memory Power Down Enable 17" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PWRDWN_set/clr ,Peripheral Memory Power Down Enable 16" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PWRDWN_set/clr ,Peripheral Memory Power Down Enable 15" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PWRDWN_set/clr ,Peripheral Memory Power Down Enable 14" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PWRDWN_set/clr ,Peripheral Memory Power Down Enable 13" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PWRDWN_set/clr ,Peripheral Memory Power Down Enable 12" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PWRDWN_set/clr ,Peripheral Memory Power Down Enable 11" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PWRDWN_set/clr ,Peripheral Memory Power Down Enable 10" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PWRDWN_set/clr ,Peripheral Memory Power Down Enable 9" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PWRDWN_set/clr ,Peripheral Memory Power Down Enable 8" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PWRDWN_set/clr ,Peripheral Memory Power Down Enable 7" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PWRDWN_set/clr ,Peripheral Memory Power Down Enable 6" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PWRDWN_set/clr ,Peripheral Memory Power Down Enable 5" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PWRDWN_set/clr ,Peripheral Memory Power Down Enable 4" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PWRDWN_set/clr ,Peripheral Memory Power Down Enable 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PWRDWN_set/clr ,Peripheral Memory Power Down Enable 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PWRDWN_set/clr ,Peripheral Memory Power Down Enable 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PWRDWN_set/clr ,Peripheral Memory Power Down Enable 0" "No power down,Power down"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "PCSPWRDWNSET1,Peripheral Memory Power-Down Set Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PWRDWN_set/clr ,Peripheral Memory Power Down Enable 63" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PWRDWN_set/clr ,Peripheral Memory Power Down Enable 62" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PWRDWN_set/clr ,Peripheral Memory Power Down Enable 61" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PWRDWN_set/clr ,Peripheral Memory Power Down Enable 60" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PWRDWN_set/clr ,Peripheral Memory Power Down Enable 59" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PWRDWN_set/clr ,Peripheral Memory Power Down Enable 58" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PWRDWN_set/clr ,Peripheral Memory Power Down Enable 57" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PWRDWN_set/clr ,Peripheral Memory Power Down Enable 56" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PWRDWN_set/clr ,Peripheral Memory Power Down Enable 55" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PWRDWN_set/clr ,Peripheral Memory Power Down Enable 54" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PC531PWRDWN_set/clr ,Peripheral Memory Power Down Enable 53" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PWRDWN_set/clr ,Peripheral Memory Power Down Enable 52" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PWRDWN_set/clr ,Peripheral Memory Power Down Enable 51" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PWRDWN_set/clr ,Peripheral Memory Power Down Enable 50" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PWRDWN_set/clr ,Peripheral Memory Power Down Enable 49" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PWRDWN_set/clr ,Peripheral Memory Power Down Enable 48" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PWRDWN_set/clr ,Peripheral Memory Power Down Enable 47" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PWRDWN_set/clr ,Peripheral Memory Power Down Enable 46" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PWRDWN_set/clr ,Peripheral Memory Power Down Enable 45" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PWRDWN_set/clr ,Peripheral Memory Power Down Enable 44" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PWRDWN_set/clr ,Peripheral Memory Power Down Enable 43" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PWRDWN_set/clr ,Peripheral Memory Power Down Enable 42" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PWRDWN_set/clr ,Peripheral Memory Power Down Enable 41" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PWRDWN_set/clr ,Peripheral Memory Power Down Enable 40" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PWRDWN_set/clr ,Peripheral Memory Power Down Enable 39" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PWRDWN_set/clr ,Peripheral Memory Power Down Enable 38" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PWRDWN_set/clr ,Peripheral Memory Power Down Enable 37" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PWRDWN_set/clr ,Peripheral Memory Power Down Enable 36" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PWRDWN_set/clr ,Peripheral Memory Power Down Enable 35" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PWRDWN_set/clr ,Peripheral Memory Power Down Enable 34" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PWRDWN_set/clr ,Peripheral Memory Power Down Enable 33" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PWRDWN_set/clr ,Peripheral Memory Power Down Enable 32" "No power down,Power down"
|
|
tree.end
|
|
width 15.
|
|
textline " "
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PSPWRDWNSET0,Peripheral Power-Down Set Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS7QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 7 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS7QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 7 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS7QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 7 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS7QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 7 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS6QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 6 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS6QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 6 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS6QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 6 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS6QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 6 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS5QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 5 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS5QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 5 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS5QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 5 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS5QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 5 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS4QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 4 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS4QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 4 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS4QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 4 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS4QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 4 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS3QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 3 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS3QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 3 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS3QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 3 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS3QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 3 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS2QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 2 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS2QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 2 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS2QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 2 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS2QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 2 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS1QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 1 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS1QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 1 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS1QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 1 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS1QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 1 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS0QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 0 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS0QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 0 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS0QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 0 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS0QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 0 0" "No power down,Power down"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "PSPWRDWNSET1,Peripheral Power-Down Set Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS15QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 15 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS15QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 15 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS15QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 15 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS15QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 15 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS14QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 14 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS14QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 14 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS14QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 14 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS14QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 14 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS13QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 13 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS13QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 13 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS13QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 13 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS13QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 13 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS12QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 12 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS12QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 12 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS12QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 12 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS12QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 12 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS11QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 11 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS11QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 11 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS11QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 11 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS11QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 11 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS10QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 10 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS10QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 10 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS10QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 10 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS10QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 10 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS9QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 9 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS9QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 9 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS9QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 9 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS9QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 9 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS8QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 8 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS8QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 8 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS8QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 8 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS8QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 8 0" "No power down,Power down"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PSPWRDWNSET2,Peripheral Power-Down Set Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS23QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 23 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS23QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 23 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS23QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 23 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS23QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 23 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS22QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 22 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS22QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 22 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS22QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 22 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS22QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 22 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS21QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 21 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS21QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 21 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS21QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 21 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS21QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 21 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS20QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 20 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS20QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 20 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS20QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 20 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS20QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 20 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS19QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 19 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS19QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 19 2" "No power down,Power down"
|
|
textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS19QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 19 1" "No power down,Power down"
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textline " "
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setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS19QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 19 0" "No power down,Power down"
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textline " "
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setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS18QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 18 3" "No power down,Power down"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS18QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 18 2" "No power down,Power down"
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textline " "
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setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS18QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 18 1" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS18QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 18 0" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS17QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 17 3" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS17QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 17 2" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS17QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 17 1" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS17QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 17 0" "No power down,Power down"
|
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textline " "
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setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS16QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 16 3" "No power down,Power down"
|
|
textline " "
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setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS16QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 16 2" "No power down,Power down"
|
|
textline " "
|
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setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS16QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 16 1" "No power down,Power down"
|
|
textline " "
|
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setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS16QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 16 0" "No power down,Power down"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "PSPWRDWNSET3,Peripheral Power-Down Set Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS31QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 31 3" "No power down,Power down"
|
|
textline " "
|
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setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS31QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 31 2" "No power down,Power down"
|
|
textline " "
|
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setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS31QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 31 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS31QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 31 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS30QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 30 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS30QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 30 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS30QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 30 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS30QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 30 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS29QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 29 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS29QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 29 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS29QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 29 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS29QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 29 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS28QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 28 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS28QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 28 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS28QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 28 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS28QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 28 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS27QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 27 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS27QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 27 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS27QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 27 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS27QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 27 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS26QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 26 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS26QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 26 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS26QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 26 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS26QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 26 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS25QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 25 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS25QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 25 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS25QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 25 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS25QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 25 0" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS24QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 24 3" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS24QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 24 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS24QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 24 1" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS24QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 24 0" "No power down,Power down"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "RAM WRAPPER"
|
|
tree "RAM Wrapper-Even"
|
|
base ad:0xFFFFF800
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "Ctrl,Ram Control Register 1"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "Threshold,Threshold Register"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "Occur,Occurrence Register"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "IntCtrl,Interrupt Control Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ErrStatus,Memory Fault Detect Status Register"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SErrAddr,Single Error Address Register"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "ErrPosition,RAM Error Position Register"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "DErrAddr,Double Error Address Register"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "RamTest,RAMTEST Register"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "RamAddrDec,RAM Address Decode TEST Register"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "RamPErrAddr,Address Parity Error Address Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "InitDomain,Init Domain Bitmapped Space Register"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BankDomainMap0,The Lower Half of the Bank_Domain_Mapping"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "BankDomainMap1,The Upper Half of the Bank_Domain_Mapping"
|
|
width 11.
|
|
tree.end
|
|
tree "RAM Wrapper-Odd"
|
|
base ad:0xFFFFF900
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "Ctrl,Ram Control Register 1"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "Threshold,Threshold Register"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "Occur,Occurrence Register"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "IntCtrl,Interrupt Control Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ErrStatus,Memory Fault Detect Status Register"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SErrAddr,Single Error Address Register"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "ErrPosition,RAM Error Position Register"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "DErrAddr,Double Error Address Register"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "RamTest,RAMTEST Register"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "RamAddrDec,RAM Address Decode TEST Register"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "RamPErrAddr,Address Parity Error Address Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "InitDomain,Init Domain Bitmapped Space Register"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BankDomainMap0,The Lower Half of the Bank_Domain_Mapping"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "BankDomainMap1,The Upper Half of the Bank_Domain_Mapping"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
textline " "
|